coreboot - Some coreboot project code with my work

Age	Commit message (Expand)	Author
2020-06-30	soc/intel/tigerlake: Add CpuReplacementCheck to chip options	Jamie Ryu
2020-06-30	soc/intel/tigerlake: Avoid NULL pointer dereference	John Zhao
2020-06-30	src: Remove whitespaces before tabs	Elyes HAOUAS
2020-06-29	soc/amd/picasso: add NULL-pointer check to root_complex_fill_ssdt	Felix Held
2020-06-29	soc/amd/picasso/soc_util: add comment on the silicon and soc types	Felix Held
2020-06-29	soc/amd/common: Refactor GPIO SCI/SMI interrupts	Kyösti Mälkki
2020-06-29	soc/amd/common: Refactor GPIO_MASTER_SWITCH interrupt enable	Kyösti Mälkki
2020-06-29	soc/amd/common: Drop ACPIMMIO GPIO bank separation	Kyösti Mälkki
2020-06-29	soc/intel/tigerlake: Run pmc_set_acpi_mode() during .init in pmc_ops	William Wei
2020-06-28	vendorcode/intel/fsp/fsp2_0/cpx_sp: Update to FSP ww24 release and adapt soc	Jonathan Zhang
2020-06-28	soc/amd/common: Allow runtime mapping of ACPIMMIO banks	Kyösti Mälkki
2020-06-28	soc/amd/common: Access ACPIMMIO via proper symbols	Kyösti Mälkki
2020-06-28	soc/intel/common: add TCC activation functionality	Sumeet R Pawnikar
2020-06-28	soc/xeon_sp/cpx: Define MSR PPIN related registers	Johnny Lin
2020-06-28	soc/amd/picasso/soc_util: rework reduced I/O chip detection	Felix Held
2020-06-27	soc/intel/broadwell: Use common early SPI code	Angel Pons
2020-06-26	soc/rockchip: Use (Q) instead of @	Stefan Reinauer
2020-06-25	Revert "soc/amd/common/block/acpimmio: Update acpimmio for psp_verstage"	Kyösti Mälkki
2020-06-25	soc/intel/cannonlake: Add PchPmPwrCycDur to chip options	Sridhar Siricilla
2020-06-25	drivers/intel/fsp2_0: decouple FSP_PEIM_TO_PEIM_INTERFACE from FSP 2.1	Jonathan Zhang
2020-06-25	soc/intel/xeon_sp: use edk2-stable202005 headers	Jonathan Zhang
2020-06-25	soc/intel/xeon_sp/cpx: display UPDs and CPX-SP specific HOBs	Jonathan Zhang
2020-06-25	soc/intel/cannonlake: Add missing USB_PORT_WAKE_ENABLE define	Edward O'Callaghan
2020-06-24	soc/amd/picasso: fix host bridge bus numbers	Aaron Durbin
2020-06-24	soc/amd/picasso: Add UPD xhci0_force_gen1	Chris Wang
2020-06-24	soc/intel/tigerlake: Fix unresolved symbol CDW1 error	John Zhao
2020-06-24	soc/intel/broadwell/adsp: Fix 8-bit write on PCI_INTERRUPT_LINE register	Elyes HAOUAS
2020-06-24	src: Report byte-sized access for GPE0	Angel Pons
2020-06-24	soc/amd/stoneyridge: Correct ACPI CPU string prefix	Matt DeVillier
2020-06-24	ACPI: Replace smm_setup_structures()	Kyösti Mälkki
2020-06-24	ACPI: Replace uses of CBMEM_ID_ACPI_GNVS	Kyösti Mälkki
2020-06-23	src/*: Update makefiles to exclude x86 code from psp-verstage	Martin Roth
2020-06-22	soc/amd/picasso: Set BERT_SIZE to 0 when no table generated	Marshall Dawson
2020-06-22	soc/amd/picasso: Convert BERT reserved region from cbmem	Marshall Dawson
2020-06-22	soc/intel/tigerlake: Add CmdMirror option in chip.h	David Wu
2020-06-22	soc/intel/xeon_sp/cpx: rename xeon_sp_get_cpu_count()	Jonathan Zhang
2020-06-22	mb/google/volteer: Override power limits with SKU-specific limits	Tim Wawrzynczak
2020-06-22	amd/picasso/acpi: Add power resources for I2C and UART	Raul E Rangel
2020-06-22	soc/intel/xeon_sp/cpx: consider stack personality	Jonathan Zhang
2020-06-22	soc/intel/xeon_sp/cpx: update ACPI xSDT	Jonathan Zhang
2020-06-22	soc/intel/jasperlake: add processor power limits control support	Sumeet R Pawnikar
2020-06-22	soc/amd/picasso: don't increment boot count twice	Aaron Durbin
2020-06-22	soc/intel/xeon_sp/cpx: Finalize PCU configuration	Jonathan Zhang
2020-06-22	soc/intel/tigerlake: Update platform.asl to ASL2.0 syntax	V Sowmya
2020-06-22	soc/amd/picasso: Enable IDT in all stages	Furquan Shaikh
2020-06-22	device/smbus_host: Declare common early SMBus prototypes	Kyösti Mälkki
2020-06-22	cpu/x86/lapic: Support x86_64 and clean up code	Patrick Rudolph
2020-06-22	soc/amd/picasso/bootblock: Clear BSS section	Raul E Rangel
2020-06-22	soc/amd/picasso/bootblock: Write EIP to secure S3	Raul E Rangel
2020-06-22	soc/qualcomm/sc7180/qupv3_config.c: Add missing includes	Elyes HAOUAS