| Age | Commit message (Expand) | Author |
|---|
| 2021-05-10 | src: Drop "This file is part of the coreboot project" lines | Angel Pons |
| 2021-05-10 | soc/intel/cannonlake: Merge soc_memory_init_params() into its caller | Felix Singer |
| 2021-05-10 | soc/intel/skylake: Set proper defaults in chipset devicetree | Felix Singer |
| 2021-05-10 | soc/intel/adl: Allow mainboard to fill CmdMirror and DqDqsRetraining | Maulik V Vaghela |
| 2021-05-10 | soc/amd/picasso: move acpigen_dptc_call_alib to new common alib | Felix Held |
| 2021-05-10 | Revert "soc/amd/common/espi: Don't set alert pin in espi_set_initial_config" | Raul E Rangel |
| 2021-05-10 | soc/amd/cezanne: Force resets to be cold | Marshall Dawson |
| 2021-05-10 | cezanne/psp_verstage: update SRAM address | Kangheui Won |
| 2021-05-10 | amd/cezanne: verify transfer buffer in bootblock | Kangheui Won |
| 2021-05-10 | psp_verstage: differentiate bios entry | Kangheui Won |
| 2021-05-10 | psp_verstage: move platform-specific code to chipset.c | Kangheui Won |
| 2021-05-10 | cezanne/psp_verstage: clean up duplicated target | Kangheui Won |
| 2021-05-10 | cezanne/psp_verstage: populate a/b firmware | Kangheui Won |
| 2021-05-10 | soc/mediatek/mt8195: Add RTC driver | Yuchen Huang |
| 2021-05-10 | soc/mediatek/mt8195: Add clk_buf driver | Yuchen Huang |
| 2021-05-10 | soc/mediatek/mt8195: Configure eMMC and SDCard | Wenbin Mei |
| 2021-05-10 | soc/mediatek/mt8195: Add i2c driver support | kewei xu |
| 2021-05-10 | soc/mediatek/mt8195: Add mt6360 driver for LDO access | Andrew SH Cheng |
| 2021-05-09 | soc/amd/cezanne: Generate PCI GPP ACPI names | Raul E Rangel |
| 2021-05-09 | soc/amd/cezanne: Enable GNB IO-APIC _PRT | Raul E Rangel |
| 2021-05-09 | soc/amd/cezanne: add GNB IOAPIC support | Felix Held |
| 2021-05-09 | soc/amd/cezanne: Generate PCI routing table | Raul E Rangel |
| 2021-05-09 | soc/amd/cezanne: Populate PCI_INTR registers | Raul E Rangel |
| 2021-05-09 | soc/amd/common/fsp/pci: Add helper methods for PCI IRQ table | Raul E Rangel |
| 2021-05-09 | soc/amd/picasso/pci_gpp: Switch to using acpigen_write_pci_GNB_PRT | Raul E Rangel |
| 2021-05-09 | soc/amd/common/block/pci: Implement acpigen_write_pci_{GNB,FCH}_PRT | Raul E Rangel |
| 2021-05-09 | soc/amd/{picasso,common/blocks/pci}: Move populate_pirq_data | Raul E Rangel |
| 2021-05-09 | soc/amd/picasso: Migrate to struct pci_routing_info | Raul E Rangel |
| 2021-05-09 | soc/amd/common/block/pci: Introduce struct pci_routing_info | Raul E Rangel |
| 2021-05-08 | soc/amd/cezanne/acpi/soc: call WAL1 for AC/DC state ALIB call | Felix Held |
| 2021-05-08 | soc/amd/picasso/acpi/cpu: move WAL1 method that calls ALIB to common | Felix Held |
| 2021-05-08 | soc/amd/picasso,common: move ALIB DPTC parameter struct to common code | Felix Held |
| 2021-05-08 | soc/amd/picasso,common: move ALIB DPTC IDs to common code | Felix Held |
| 2021-05-08 | soc/amd/picasso/root_complex: move DPTC_TOTAL_UPDATE_PARAMS out of enum | Felix Held |
| 2021-05-08 | soc/amd: factor out ACPI ALIB function numbers to common code | Felix Held |
| 2021-05-07 | soc/amd/common/acpi/pci_int.asl: Allow IRQ sharing | Raul E Rangel |
| 2021-05-07 | soc/amd/common: Add Kconfig/Makefile support for common/fsp/* | Raul E Rangel |
| 2021-05-07 | soc/mediatek/mt8195: Turn off L2C SRAM and reconfigure as L2 cache | Yidi Lin |
| 2021-05-07 | soc/intel/{adl,tgl,jsl}: Enable power button smi after BS_CHIPS_EXIT | Kane Chen |
| 2021-05-07 | soc/intel/{adl,tgl,jsl}: Add smihandler_soc_disable_busmaster | Kane Chen |
| 2021-05-06 | soc/amd/common/espi,mb/: Allow configuring open drain ALERT# | Raul E Rangel |
| 2021-05-06 | soc/amd/common/espi: Don't set alert pin in espi_set_initial_config | Raul E Rangel |
| 2021-05-06 | soc/amd/common/espi: Print set eSPI peripheral config | Raul E Rangel |
| 2021-05-06 | soc/amd/{common/picasso}: Move pci_int.asl | Raul E Rangel |
| 2021-05-06 | soc/amd/{picasso/common}: Move populate_pirq_data prototype to common | Raul E Rangel |
| 2021-05-06 | src: Retype option API to use unsigned integers | Angel Pons |
| 2021-05-06 | Revert "soc/intel/xeon_sp: Fix devices list in the DMAR DRHD structure" | Arthur Heymans |
| 2021-05-06 | soc/intel/tgl,mb/google/volteer: Add API for Type-C aux bias pads | Tim Wawrzynczak |
| 2021-05-06 | soc/intel/tigkerlake: Add IOM PCR PID | Tim Wawrzynczak |
| 2021-05-06 | soc/intel/tigerlake: Add known CPU Port IDs for GPIO communities | Tim Wawrzynczak |
