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path: root/src/southbridge/intel/lynxpoint/acpi/usb.asl
AgeCommit message (Expand)Author
2020-11-13sb/intel/lynxpoint/acpi: Split USB into EHCI and xHCIAngel Pons
2020-11-13sb/intel/lynxpoint/acpi: Statically define _PRW valuesAngel Pons
2020-11-13sb/intel/lynxpoint/acpi: Clean up cosmeticsAngel Pons
2020-05-11treewide: Remove "this file is part of" linesPatrick Georgi
2020-04-04src/southbridge: Use SPDX for GPL-2.0-only filesAngel Pons
2020-03-17src (minus soc and mainboard): Remove copyright noticesPatrick Georgi
2017-05-31sb/lynxpoint: add missing USB port defsMatt DeVillier
2017-05-31sb/lynxpoint: add ACPI method to generate USB port infoMatt DeVillier
2015-10-31tree: drop last paragraph of GPL copyright headerPatrick Georgi
2015-05-21Remove address from GPLv2 headersPatrick Georgi
2014-07-17southbridge,ASL: Trivial - drop trailing blank lines at EOFEdward O'Callaghan
2013-12-21lynxpoint: XHCI: Don't put device in D3 in _PS0 MethodDuncan Laurie
2013-12-21lynxpoint: Fix an issue clearing port change status bitsDuncan Laurie
2013-12-21lynxpoint: XHCI: Advertise D3 as lowest wake stateDuncan Laurie
2013-12-21lynxpoint xhci: Add ACPI D0/D3 workaroundsDuncan Laurie
2013-12-03lynxpoint: Fix LPT-LP PME_B0 bit offset in ACPI _PRW objectsDuncan Laurie
2013-11-25lynxpoint: Fix XHCI controller device in ACPIDuncan Laurie
2013-03-14haswell: Add initial support for Haswell platformsAaron Durbin
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