coreboot - Some coreboot project code with my work

Age	Commit message (Expand)	Author
2021-01-25	util: Update all shebangs to use /usr/bin/env	Martin Roth
2020-05-11	treewide: Remove "this file is part of" lines	Patrick Georgi
2020-05-09	util/: Replace GPLv2 boiler plate with SPDX header	Patrick Georgi
2020-05-09	AUTHORS, util/: Drop individual copyright notices	Patrick Georgi
2018-11-22	riscv: fix bug of sifive-gpt.py	Xiang Wang
2018-11-17	treewide: use /usr/bin/env where appropriate	Yegor Timoshenko
2018-09-14	riscv: add trampoline in MBR block to support boot mode 1	Philipp Hug
2018-07-26	util: Add description.md to each util	Tom Hiller
2018-04-26	src/sifive: Add the SiFive Freedom Unleashed 540 SoC	Jonathan Neuschäfer
2018-04-25	util/riscvtools: Rename to util/riscv/	Jonathan Neuschäfer