update

1 files changed, 15 insertions, 6 deletions

diff --git a/thesis.bib b/thesis.bib
index a12f58e..5aefd8e 100644
--- a/thesis.bib
+++ b/thesis.bib
@@ -34,13 +34,22 @@
  year = {2019},
 }
 
+@misc{meltdownprime,
+    title={MeltdownPrime and SpectrePrime: Automatically-Synthesized Attacks Exploiting Invalidation-Based Coherence Protocols},
+    author={Caroline Trippel and Daniel Lustig and Margaret Martonosi},
+    year={2018},
+    eprint={1802.03802},
+    archivePrefix={arXiv},
+    primaryClass={cs.CR}
+}
+
 @inproceedings{foreshadow,
     author = {Van Bulck, Jo and Minkin, Marina and Weisse, Ofir and Genkin, Daniel and Kasikci, Baris and
               Piessens, Frank and Silberstein, Mark and Wenisch, Thomas F. and Yarom, Yuval and Strackx, Raoul},
     title = {Foreshadow: Extracting the Keys to the {Intel SGX} Kingdom with Transient Out-of-Order Execution},
     booktitle = {Proceedings of the 27th {USENIX} Security Symposium},
     year = {2018},
-    month = {August},
+    month = Aug,
     publisher = {{USENIX} Association},
     note={See also technical report Foreshadow-NG~\cite{weisse2018foreshadowNG}}
 }
@@ -162,7 +171,7 @@
 	title={Speculative Load Hardening},
 	author={Chandler Carruth},
 	year={2018},
-	month={March},
+	month=Mar,
 	url={https://releases.llvm.org/8.0.0/docs/SpeculativeLoadHardening.html}
 }
 
@@ -203,7 +212,7 @@ pages={428-441},
 keywords={cache storage;cryptography;microprocessor chips;multiprocessing systems;parallel architectures;program compilers;speculative execution invisible;side channel attacks;speculative execution attacks;microarchitectural state;hardware speculation attacks;InvisiSpec blocks microarchitectural;multiprocessor data cache hierarchy;unsafe speculative loads;speculative buffer;futuristic attacks;Spectre attacks;execution slowdown;memory consistency;Hardware;Load modeling;Receivers;Coherence;Security;Monitoring;Transient analysis;hardware security;speculation;side channel;memory hierarchy},
 doi={10.1109/MICRO.2018.00042},
 ISSN={},
-month={Oct},}
+month=Oct,}
 
 @INPROCEEDINGS{dawg,
 author={V. {Kiriansky} and I. {Lebedev} and S. {Amarasinghe} and S. {Devadas} and J. {Emer}},
@@ -216,7 +225,7 @@ pages={974-987},
 keywords={cache storage;security of data;cache timing attacks;dynamically allocated way guard;Intels Cache Allocation Technology;memory caches;generic mechanism;cache state covert channel;entire attack surface;patch specific attacks;existing defense mechanisms;exfiltration channel;cache tag state;speculative processor architectures;channel attacks;speculative execution processors;cache subsystem;minimal modifications;service mechanisms;set associative structure;DAWG;Receivers;Program processors;Security;Transmitters;Metadata;Hardware;cache partitioning;side channel attacks;speculative execution},
 doi={10.1109/MICRO.2018.00083},
 ISSN={},
-month={Oct},}
+month=Oct,}
 
 @inproceedings{context-sensitive-fencing,
   title={Context-Sensitive Fencing: Securing Speculative Execution via Microcode Customization},
@@ -354,7 +363,7 @@ This thesis highlights two aspects of the BOOM design: its industry-competitive
 	keywords={cache storage;computer architecture;microprocessor chips;program diagnostics;security of data;trusted page buffer;cachehit based hazard filter;conditional speculation;spectre vulnerabilities;false security hazards;unsafe instructions;safe instructions;classic out-of-order pipeline;suspect speculation flags;security-dependent instructions;potential security risk;speculative memory instructions;security dependence;software transparent defense mechanism;security consideration;speculative execution;spectre attacks;out-of-order execution;Security;Hazards;Out of order;Microprocessors;Registers;Spectre vulnerabilities defense;Security dependence;Speculative execution side-channel vulnerabilities},
 	doi={10.1109/HPCA.2019.00043},
 	ISSN={2378-203X},
-	month={Feb},}
+	month=Feb,}
 
 % looks useful...
 @INPROCEEDINGS{poisonivy,
@@ -368,7 +377,7 @@ This thesis highlights two aspects of the BOOM design: its industry-competitive
 	keywords={cryptography;PoisonIvy;safe speculation;secure memory;encryption;integrity trees;physical attacks;integrity verification latency;address-based side-channels;memory intensive workloads;Radiation detectors;Program processors;Encryption;Toxicology;Metadata},
 	doi={10.1109/MICRO.2016.7783741},
 	ISSN={},
-	month={Oct},
+	month=Oct,
 }
 
 % related article