diff options
Diffstat (limited to 'thesis.bib')
| -rw-r--r-- | thesis.bib | 152 |
1 files changed, 109 insertions, 43 deletions
@@ -9,6 +9,7 @@ Dmitry Evtyushkin and Daniel Gruss}, title = {A Systematic Evaluation of Transient Execution Attacks and Defenses}, + type = {J}, journal = {CoRR}, volume = {abs/1811.05441}, year = {2018}, @@ -25,6 +26,7 @@ title = {Meltdown: Reading Kernel Memory from User Space}, booktitle = {27th {USENIX} Security Symposium ({USENIX} Security 18)}, year = {2018}, + type = {C}, } @inproceedings{spectre, @@ -32,6 +34,7 @@ title = {Spectre Attacks: Exploiting Speculative Execution}, booktitle = {40th IEEE Symposium on Security and Privacy (S\&P'19)}, year = {2019}, + type = {C}, } @inproceedings{ret2libc, @@ -50,6 +53,7 @@ publisher = {ACM}, address = {New York, NY, USA}, keywords = {instruction set, return-into-libc, turing completeness}, + type = {C}, } @online{msvc, @@ -76,7 +80,8 @@ year={2018}, eprint={1802.03802}, archivePrefix={arXiv}, - primaryClass={cs.CR} + primaryClass={cs.CR}, + type = {R}, } @inproceedings{foreshadow, @@ -87,7 +92,8 @@ year = {2018}, month = Aug, publisher = {{USENIX} Association}, - note={See also technical report Foreshadow-NG~\cite{foreshadowNG}} + note= {See also technical report Foreshadow-NG~\supercite{foreshadowNG}}, + type = {C}, } @article{foreshadowNG, @@ -96,7 +102,8 @@ Piessens, Frank and Silberstein, Mark and Strackx, Raoul and Wenisch, Thomas F. and Yarom, Yuval}, journal={Technical report}, year={2018}, - note={See also {USENIX} Security paper Foreshadow~\cite{foreshadow}} + note={See also {USENIX} Security paper Foreshadow~\cite{foreshadow}}, + type = {R}, } @article{netspectre, @@ -113,7 +120,8 @@ eprint = {1807.10535}, timestamp = {Mon, 13 Aug 2018 16:46:22 +0200}, biburl = {https://dblp.org/rec/bib/journals/corr/abs-1807-10535}, - bibsource = {dblp computer science bibliography, https://dblp.org} + bibsource = {dblp computer science bibliography, https://dblp.org}, + type = {J}, } @article{sgxpectre, @@ -132,41 +140,48 @@ eprint = {1802.09085}, timestamp = {Mon, 13 Aug 2018 16:48:38 +0200}, biburl = {https://dblp.org/rec/bib/journals/corr/abs-1802-09085}, - bibsource = {dblp computer science bibliography, https://dblp.org} + bibsource = {dblp computer science bibliography, https://dblp.org}, + type = {J}, } @online{sgx, url={https://software.intel.com/en-us/sgx}, title={Intel Software Guard Extensions (Intel SGX)}, + type = {OL}, } @online{signal-sgx, url = {https://signal.org/blog/private-contact-discovery/}, title = {Technology preview: Private contact discovery for Signal}, year = {2017}, - month = 9 + month = 9, + type = {OL}, } @online{sawtooth, url = {https://sawtooth.hyperledger.org/docs/core/releases/latest/introduction.html}, - title = {Sawtooth} + title = {Sawtooth}, + type = {OL}, } @online{mobilecoin, url = {https://www.mobilecoin.com/whitepaper-en.pdf}, - title = {MobileCoin} + title = {MobileCoin}, + type = {OL}, } @online{intel-spec, title = {Intel 64 and IA-32 Architectures Software Developer Manuals}, url = {https://software.intel.com/en-us/articles/intel-sdm}, - author = {Intel} + author = {Intel}, + type = {OL}, } @online{l1tf, - title={Deep Dive: Intel Analysis of L1 Terminal Fault}, - url={https://software.intel.com/security-software-guidance/insights/deep-dive-intel-analysis-l1-terminal-fault}, - year={2018}, + title={Deep Dive: Intel Analysis of L1 Terminal Fault}, + url={https://software.intel.com/security-software-guidance/insights/deep-dive-intel-analysis-l1-terminal-fault}, + year={2018}, + type = {OL}, } @online{intel-spectre, @@ -176,6 +191,7 @@ year = {2018}, month = 7, version = {Revision 4.0}, + type = {OL}, } @online{amd-spectre, @@ -184,6 +200,7 @@ author = {AMD}, year = {2018}, version = {Revision 7.10.18}, + type = {OL}, } @inproceedings{branchscope, @@ -202,6 +219,7 @@ publisher = {ACM}, address = {New York, NY, USA}, keywords = {SGX, attack, branch predictor, microarchitecture security, performance counters, side-channel, timing attacks}, + type = {C}, } @inproceedings{flushreload, @@ -209,21 +227,24 @@ author={Yarom, Yuval and Falkner, Katrina}, booktitle={23rd $\{$USENIX$\}$ Security Symposium ($\{$USENIX$\}$ Security 14)}, pages={719--732}, - year={2014} + year={2014}, + type = {C}, } @online{spec-store-bypass, title={speculative execution, variant 4: speculative store bypass}, author={Jann Horn}, url={https://bugs.chromium.org/p/project-zero/issues/detail?id=1528}, - year={2018} + year={2018}, + type = {OL}, } @online{store-load-forwarding, title={Store-to-Load Forwarding and Memory Disambiguation in x86 Processors}, author={Henry Wong}, year={2014}, - url={http://blog.stuffedcow.net/2014/01/x86-memory-disambiguation/} + url={http://blog.stuffedcow.net/2014/01/x86-memory-disambiguation/}, + type={OL}, } @@ -233,7 +254,8 @@ booktitle={International Symposium on Engineering Secure Software and Systems}, pages={161--176}, year={2017}, - organization={Springer} + organization={Springer}, + type = {C}, } @online{retpoline, @@ -241,6 +263,7 @@ url = {https://support.google.com/faqs/answer/7625886}, author = {Paul Turner}, year = {2018}, + type = {OL}, } @online{webkit, @@ -248,14 +271,16 @@ url = {https://webkit.org/blog/8048/what-spectre-and-meltdown-mean-for-webkit/}, author = {Filip Pizlo}, year = {2018}, - month = Jan + month = Jan, + type = {OL}, } @inproceedings{js-timer, title={Fantastic Timers and Where to Find Them: High-Resolution Microarchitectural Attacks in JavaScript}, author={Michael Schwarz and Cl{\'e}mentine Maurice and Daniel Gruss and Stefan Mangard}, booktitle={Financial Cryptography}, - year={2017} + year={2017}, + type={J}, } @misc{here-to-stay, @@ -264,7 +289,8 @@ year={2019}, eprint={1902.05178}, archivePrefix={arXiv}, - primaryClass={cs.PL} + primaryClass={cs.PL}, + type={R}, } @online{spec-load-hardening, @@ -272,7 +298,8 @@ author={Chandler Carruth}, year={2018}, month=Mar, - url={https://releases.llvm.org/8.0.0/docs/SpeculativeLoadHardening.html} + url={https://releases.llvm.org/8.0.0/docs/SpeculativeLoadHardening.html}, + type={OL}, } @misc{oo7, @@ -281,7 +308,8 @@ year={2018}, eprint={1807.05843}, archivePrefix={arXiv}, - primaryClass={cs.CR} + primaryClass={cs.CR}, + type={R}, } @misc{spectector, @@ -290,13 +318,15 @@ year={2018}, eprint={1812.08639}, archivePrefix={arXiv}, - primaryClass={cs.CR} + primaryClass={cs.CR}, + type={R}, } @online{linux-spec, url={https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/speculation.txt}, year={2018}, - } + type={OL}, +} % looks like there's some useful references @@ -316,7 +346,8 @@ eprint = {1806.05179}, timestamp = {Mon, 13 Aug 2018 16:48:54 +0200}, biburl = {https://dblp.org/rec/bib/journals/corr/abs-1806-05179}, - bibsource = {dblp computer science bibliography, https://dblp.org} + bibsource = {dblp computer science bibliography, https://dblp.org}, + type={J}, } @INPROCEEDINGS{invisispec, @@ -330,7 +361,9 @@ pages={428-441}, keywords={cache storage;cryptography;microprocessor chips;multiprocessing systems;parallel architectures;program compilers;speculative execution invisible;side channel attacks;speculative execution attacks;microarchitectural state;hardware speculation attacks;InvisiSpec blocks microarchitectural;multiprocessor data cache hierarchy;unsafe speculative loads;speculative buffer;futuristic attacks;Spectre attacks;execution slowdown;memory consistency;Hardware;Load modeling;Receivers;Coherence;Security;Monitoring;Transient analysis;hardware security;speculation;side channel;memory hierarchy}, doi={10.1109/MICRO.2018.00042}, ISSN={}, -month=Oct,} +month=Oct, +type={C} +} @ARTICLE{cain-lapasti, author={H. W. {Cain} and M. H. {Lipasti}}, @@ -343,7 +376,9 @@ pages={110-117}, keywords={content-addressable storage;data integrity;data structures;instruction sets;memory architecture;reduced instruction set computing;storage management;memory ordering;value-based replay;load instructions;first-in-first-out buffer;heuristics filter;cache storage;content addressable memory;memory consistency;Insulation;Bandwidth;Hazards;Computer aided manufacturing;CADCAM;Scalability;Costs;Filters;Degradation;Computer aided instruction}, doi={10.1109/MM.2004.81}, ISSN={0272-1732}, -month={Nov},} +month=11, +type={C} +} @INPROCEEDINGS{dawg, author={V. {Kiriansky} and I. {Lebedev} and S. {Amarasinghe} and S. {Devadas} and J. {Emer}}, @@ -356,7 +391,9 @@ pages={974-987}, keywords={cache storage;security of data;cache timing attacks;dynamically allocated way guard;Intels Cache Allocation Technology;memory caches;generic mechanism;cache state covert channel;entire attack surface;patch specific attacks;existing defense mechanisms;exfiltration channel;cache tag state;speculative processor architectures;channel attacks;speculative execution processors;cache subsystem;minimal modifications;service mechanisms;set associative structure;DAWG;Receivers;Program processors;Security;Transmitters;Metadata;Hardware;cache partitioning;side channel attacks;speculative execution}, doi={10.1109/MICRO.2018.00083}, ISSN={}, -month=Oct,} +month=Oct, +type={C} +} @inproceedings{dift, title={Secure program execution via dynamic information flow tracking}, @@ -366,7 +403,8 @@ month=Oct,} number={11}, pages={85--96}, year={2004}, - organization={ACM} + organization={ACM}, + type={J}, } @inproceedings{raksha, @@ -385,13 +423,15 @@ month=Oct,} publisher = {ACM}, address = {New York, NY, USA}, keywords = {dynamic, semantic vulnerabilities, software security}, + type={C}, } @inproceedings{context-sensitive-fencing, title={Context-Sensitive Fencing: Securing Speculative Execution via Microcode Customization}, author={Taram, Mohammadkazem and Venkat, Ashish and Tullsen, Dean}, booktitle={Proceedings of the Twenty-Fourth International Conference on Architectural Support for Programming Languages and Operating Systems}, - year={2019} + year={2019}, + type={C}, } @inproceedings{context-sensitive-decoding, @@ -400,12 +440,14 @@ month=Oct,} booktitle={2018 ACM/IEEE 45th Annual International Symposium on Computer Architecture (ISCA)}, pages={624--637}, year={2018}, - organization={IEEE} + organization={IEEE}, + type={C}, } @article{csd-gomactech, title={Fast and Efficient Deployment of Security Defenses Via Context Sensitive Decoding}, - author={Taram, Mohammadkazem and Tullsen, Dean and Venkat, Ashish and Homayoun, Houman and PD, Sai Manoj} + author={Taram, Mohammadkazem and Tullsen, Dean and Venkat, Ashish and Homayoun, Houman and PD, Sai Manoj}, + type={R}, } @article{spec-buffer-overflow, @@ -420,7 +462,8 @@ month=Oct,} eprint = {1807.03757}, timestamp = {Mon, 13 Aug 2018 16:48:44 +0200}, biburl = {https://dblp.org/rec/bib/journals/corr/abs-1807-03757}, - bibsource = {dblp computer science bibliography, https://dblp.org} + bibsource = {dblp computer science bibliography, https://dblp.org}, + type={J}, } % https://www.usenix.org/conference/woot18/presentation/koruyeh @@ -428,7 +471,8 @@ month=Oct,} title={Spectre returns! speculation attacks using the return stack buffer}, author={Koruyeh, Esmaeil Mohammadian and Khasawneh, Khaled N and Song, Chengyu and Abu-Ghazaleh, Nael}, booktitle={12th $\{$USENIX$\}$ Workshop on Offensive Technologies ($\{$WOOT$\}$ 18)}, - year={2018} + year={2018}, + type={J}, } @inproceedings{ret2spec, @@ -447,6 +491,7 @@ month=Oct,} publisher = {ACM}, address = {New York, NY, USA}, keywords = {hardware security, javascript, side channel attacks}, + type={C}, } @article{lazyfp, @@ -460,7 +505,8 @@ archivePrefix = "arXiv", year = 2018, month = jun, adsurl = {http://adsabs.harvard.edu/abs/2018arXiv180607480S}, - adsnote = {Provided by the SAO/NASA Astrophysics Data System} + adsnote = {Provided by the SAO/NASA Astrophysics Data System}, + type={J}, } @inproceedings{Shen:2018:RCF:3243734.3278522, @@ -479,11 +525,13 @@ archivePrefix = "arXiv", publisher = {ACM}, address = {New York, NY, USA}, keywords = {side-channel defenses, spectre attacks, speculative execution}, + type={C}, } @article{spectrum, title={Spectrum: Classifying, Replicating and Mitigating Spectre Attacks on a Speculating RISC-V Microarchitecture}, - author={Gonzalez, Abraham and Korpan, Ben and Younis, Ed and Zhao, Jerry} + author={Gonzalez, Abraham and Korpan, Ben and Younis, Ed and Zhao, Jerry}, + type={R}, } @phdthesis{boom, @@ -501,7 +549,8 @@ To facilitate architecture research during this fallow period of Moore’s Law, Our processor generator is called BOOM, and it designed for use in education, research, and industry. Like most contemporary high-performance cores, BOOM is superscalar (able to execute multiple instructions per cycle) and out-of-order (able to execute instructions as their dependencies are resolved and not restricted to their program order). The BOOM generator was implemented using the Chisel hardware construction language, allowing for the rapid implementation of parameterized designs. The Chisel description generates synthesizable implementations of BOOM that can target both FPGAs and ASIC tool-flows. The BOOM effort culminated in a test chip that was fabricated in the TSMC 28 nm HPM process (high performance mobile) using the foundry-provided standard-cell library and memory compiler. -This thesis highlights two aspects of the BOOM design: its industry-competitive branch prediction and its configurable execution datapath. The remainder of the thesis discusses the BOOM tape-out, which was performed by two graduate students and demonstrated the ability to quickly adapt the design to the physical design issues that arose.} +This thesis highlights two aspects of the BOOM design: its industry-competitive branch prediction and its configurable execution datapath. The remainder of the thesis discusses the BOOM tape-out, which was performed by two graduate students and demonstrated the ability to quickly adapt the design to the physical design issues that arose.}, + type={D}, } @misc{oisa, @@ -510,6 +559,7 @@ This thesis highlights two aspects of the BOOM design: its industry-competitive howpublished = {Cryptology ePrint Archive, Report 2018/808}, year = {2018}, note = {\url{https://eprint.iacr.org/2018/808}}, + type={J}, } @INPROCEEDINGS{conditional-speculation, @@ -523,7 +573,9 @@ This thesis highlights two aspects of the BOOM design: its industry-competitive keywords={cache storage;computer architecture;microprocessor chips;program diagnostics;security of data;trusted page buffer;cachehit based hazard filter;conditional speculation;spectre vulnerabilities;false security hazards;unsafe instructions;safe instructions;classic out-of-order pipeline;suspect speculation flags;security-dependent instructions;potential security risk;speculative memory instructions;security dependence;software transparent defense mechanism;security consideration;speculative execution;spectre attacks;out-of-order execution;Security;Hazards;Out of order;Microprocessors;Registers;Spectre vulnerabilities defense;Security dependence;Speculative execution side-channel vulnerabilities}, doi={10.1109/HPCA.2019.00043}, ISSN={2378-203X}, - month=Feb,} + month=Feb, + type={C} +} @inproceedings{spectreguard, title={SpectreGuard : An Efficient Data-centric Defense Mechanism against Spectre Attacks}, @@ -531,6 +583,7 @@ This thesis highlights two aspects of the BOOM design: its industry-competitive year={2019}, booktitle = {Proceedings of the 56th Annual Design Automation Conference}, series = {DAC '19}, + type={C}, } % looks useful... @@ -546,6 +599,7 @@ This thesis highlights two aspects of the BOOM design: its industry-competitive doi={10.1109/MICRO.2016.7783741}, ISSN={}, month=Oct, + type={C}, } % related article @@ -557,7 +611,8 @@ This thesis highlights two aspects of the BOOM design: its industry-competitive number={1}, pages={1--27}, year={2018}, - publisher={Springer} + publisher={Springer}, + type={J}, } % about multiplier timing @@ -567,7 +622,8 @@ This thesis highlights two aspects of the BOOM design: its industry-competitive booktitle={2015 IEEE Symposium on Security and Privacy}, pages={623--639}, year={2015}, - organization={IEEE} + organization={IEEE}, + type={C}, } % side channel @@ -584,6 +640,7 @@ This thesis highlights two aspects of the BOOM design: its industry-competitive acmid = {706156}, publisher = {Springer-Verlag}, address = {London, UK, UK}, + type={C}, } @book{MOP2010, @@ -592,6 +649,7 @@ This thesis highlights two aspects of the BOOM design: its industry-competitive year = {2010}, edition = {1st}, publisher = {Springer Publishing Company, Incorporated}, + type={M}, } @misc{EMpower, @@ -600,6 +658,7 @@ This thesis highlights two aspects of the BOOM design: its industry-competitive howpublished = {Cryptology ePrint Archive, Report 2001/037}, year = {2001}, note = {\url{https://eprint.iacr.org/2001/037}}, + type={J}, } @inproceedings{hutter, @@ -608,7 +667,8 @@ This thesis highlights two aspects of the BOOM design: its industry-competitive booktitle={International Conference on Smart Card Research and Advanced Applications}, pages={219--235}, year={2013}, - organization={Springer} + organization={Springer}, + type={C}, } @inproceedings{acoustic, @@ -616,7 +676,8 @@ This thesis highlights two aspects of the BOOM design: its industry-competitive author={Backes, Michael and D{\"u}rmuth, Markus and Gerling, Sebastian and Pinkal, Manfred and Sporleder, Caroline}, booktitle={USENIX Security symposium}, pages={307--322}, - year={2010} + year={2010}, + type={C}, } @phdthesis{gruss, @@ -624,6 +685,7 @@ This thesis highlights two aspects of the BOOM design: its industry-competitive title = {Software-based Microarchitectural Attacks}, school = {Graz University of Technology}, year = 2017, + type={D}, } @article{gem5, @@ -634,7 +696,8 @@ This thesis highlights two aspects of the BOOM design: its industry-competitive number={2}, pages={1--7}, year={2011}, - publisher={ACM} + publisher={ACM}, + type={J}, } @article{m5, @@ -655,6 +718,7 @@ This thesis highlights two aspects of the BOOM design: its industry-competitive publisher = {IEEE Computer Society Press}, address = {Los Alamitos, CA, USA}, keywords = {M5, M5, network I/O, TCP/IP, networked systems, TCP/IP, network I/O, networked systems}, + type={J}, } @article{gems, @@ -674,6 +738,7 @@ This thesis highlights two aspects of the BOOM design: its industry-competitive acmid = {1105747}, publisher = {ACM}, address = {New York, NY, USA}, + type={J}, } @inproceedings{jump-over-aslr, @@ -682,7 +747,8 @@ This thesis highlights two aspects of the BOOM design: its industry-competitive booktitle={The 49th Annual IEEE/ACM International Symposium on Microarchitecture}, pages={40}, year={2016}, - organization={IEEE Press} + organization={IEEE Press}, + type={J} } % vim:ts=4:sw=4 |