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| author | Jiewen Yao <jiewen.yao@intel.com> | 2017-10-17 13:22:45 +0800 |
|---|---|---|
| committer | Jiewen Yao <jiewen.yao@intel.com> | 2017-10-24 19:42:51 +0800 |
| commit | 5e96ef6cdec8835eacdbe902309139ed07f33174 (patch) | |
| tree | fc22ec344acd3f441910ba4f6d828dfb9f34e078 | |
| parent | e3539c30d8e94934fa97082951a3f9536c865658 (diff) | |
| download | edk2-platforms-5e96ef6cdec8835eacdbe902309139ed07f33174.tar.xz | |
Performance improvement.
MemoryInit code will consume the DISB bit in PCH
(DRAM Initialization Scratchpad Bit - GEN_PMCON_A[23])
to decide if it goes optimization path.
With this change, the time of MemoryInit API is reduced from
10 seconad to 69 millisecond.
Cc: Michael A Kubacki <michael.a.kubacki@intel.com>
Cc: Amy Chan <amy.chan@intel.com>
Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Brett Wang <brett.wang@intel.com>
Cc: Daocheng Bu <daocheng.bu@intel.com>
Cc: Isaac W Oram <isaac.w.oram@intel.com>
Cc: Rangasai V Chaganty <rangasai.v.chaganty@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Amy Chan <amy.chan@intel.com>
| -rw-r--r-- | Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c b/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c index 0f7c6acb59..57a1846ad2 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c +++ b/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c @@ -25,7 +25,9 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. #include <Library/MemoryAllocationLib.h>
#include <Library/DebugLib.h>
#include <Library/DebugPrintErrorLevelLib.h>
+#include <Library/PciLib.h>
#include <Guid/MemoryOverwriteControl.h>
+#include <PchAccess.h>
/**
Performs FSP Misc UPD initialization.
@@ -61,6 +63,14 @@ PeiFspMiscUpdUpdatePreMem ( DEBUG ((DEBUG_INFO, "MemoryConfig Size - 0x%x\n", VariableSize));
FspmUpd->FspmArchUpd.NvsBufferPtr = MemorySavedData;
+ if (FspmUpd->FspmArchUpd.NvsBufferPtr != NULL) {
+ //
+ // Set the DISB bit in PCH (DRAM Initialization Scratchpad Bit - GEN_PMCON_A[23]),
+ // after memory Data is saved to NVRAM.
+ //
+ PciOr32 ((UINTN)PCI_LIB_ADDRESS (0, PCI_DEVICE_NUMBER_PCH_PMC, PCI_FUNCTION_NUMBER_PCH_PMC, R_PCH_PMC_GEN_PMCON_A), B_PCH_PMC_GEN_PMCON_A_DISB);
+ }
+
//
// MOR
//
|