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authorHeyi Guo <heyi.guo@linaro.org>2015-05-27 15:10:10 +0000
committeroliviermartin <oliviermartin@Edk2>2015-05-27 15:10:10 +0000
commit829ea9b2dd8795da26729b4cd192e3e907725809 (patch)
tree701d772ece5bdb3bb46bcbf867c766a2dd2c5fc3
parent98c9d3be0815bca3b7230a4765751f6ded74be42 (diff)
downloadedk2-platforms-829ea9b2dd8795da26729b4cd192e3e907725809.tar.xz
ArmPkg: Expand AArch64 address width to 48 bits
The VA address space has a maximum address width of 48 bits in AArch64 state; 48 bits address width limit will provide better compatibility than 40 bits for future CPU. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo <heyi.guo@linaro.org> Reviewed-by: Olivier Martin <Olivier.Martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17526 6f19259b-4bc3-4df7-8a09-765794883524
-rw-r--r--ArmPkg/Include/Chipset/AArch64Mmu.h4
1 files changed, 2 insertions, 2 deletions
diff --git a/ArmPkg/Include/Chipset/AArch64Mmu.h b/ArmPkg/Include/Chipset/AArch64Mmu.h
index 77a96ec637..2398ba2539 100644
--- a/ArmPkg/Include/Chipset/AArch64Mmu.h
+++ b/ArmPkg/Include/Chipset/AArch64Mmu.h
@@ -51,8 +51,8 @@
#define TT_ALIGNMENT_BLOCK_ENTRY BIT12
#define TT_ALIGNMENT_DESCRIPTION_TABLE BIT12
-#define TT_ADDRESS_MASK_BLOCK_ENTRY (0xFFFFFFFULL << 12)
-#define TT_ADDRESS_MASK_DESCRIPTION_TABLE (0xFFFFFFFULL << 12)
+#define TT_ADDRESS_MASK_BLOCK_ENTRY (0xFFFFFFFFFULL << 12)
+#define TT_ADDRESS_MASK_DESCRIPTION_TABLE (0xFFFFFFFFFULL << 12)
#define TT_TYPE_MASK 0x3
#define TT_TYPE_TABLE_ENTRY 0x3