diff options
| author | Guo Mang <mang.guo@intel.com> | 2016-06-02 13:57:38 +0800 |
|---|---|---|
| committer | Hao Wu <hao.a.wu@intel.com> | 2016-06-07 09:55:43 +0800 |
| commit | 027f496a7e6db871ef6590cec153004def4fc12f (patch) | |
| tree | 9d27cc4dbfdc9a0a5878e862d087d549b8514d45 | |
| parent | 2b3fb23071cc2042c023aa51466e61a1566278d9 (diff) | |
| download | edk2-platforms-027f496a7e6db871ef6590cec153004def4fc12f.tar.xz | |
ChvRefCodePkg: Add PchInit module.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Guo Mang <mang.guo@intel.com>
13 files changed, 4208 insertions, 0 deletions
diff --git a/ChvRefCodePkg/CherryViewSoc/SouthCluster/PchInit/Common/PchUsbCommon.c b/ChvRefCodePkg/CherryViewSoc/SouthCluster/PchInit/Common/PchUsbCommon.c new file mode 100644 index 0000000000..48106847c5 --- /dev/null +++ b/ChvRefCodePkg/CherryViewSoc/SouthCluster/PchInit/Common/PchUsbCommon.c @@ -0,0 +1,81 @@ +/** @file
+ Initializes PCH USB Controller.
+
+ Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "PchUsbCommon.h"
+
+/**
+ USB initialization before boot to OS
+
+ @param[in] UsbConfig The PCH Platform Policy for USB configuration
+
+**/
+VOID
+UsbInitAtBoot (
+ IN PCH_USB_CONFIG *UsbConfig
+)
+{
+ UINTN XhciPciMmBase;
+ UINT32 XhciMmioBase;
+
+ DEBUG ((EFI_D_INFO, "UsbInitAtBoot() - Start\n"));
+
+ if ((UsbConfig->SsicPortSettings[0].Enable == PCH_DEVICE_DISABLE) &&
+ (UsbConfig->SsicPortSettings[1].Enable == PCH_DEVICE_DISABLE)) {
+ DEBUG ((EFI_D_INFO, "UsbInitAtBoot() - SsicPortSettings[0] & SsicPortSettings[1] - Disabled\n"));
+ XhciPciMmBase = MmPciAddress (
+ 0,
+ 0,
+ PCI_DEVICE_NUMBER_PCH_XHCI,
+ PCI_FUNCTION_NUMBER_PCH_XHCI,
+ 0
+ );
+
+ XhciMmioBase = MmioRead32 (XhciPciMmBase + R_PCH_XHCI_MEM_BASE) & B_PCH_XHCI_MEM_BASE_BA;
+
+ //
+ // SSIC port 0: PORT_UNUSED=1 PROG_DONE=1
+ // SSIC port 1: PORT_UNUSED=0 PROG_DONE=1
+ //
+
+ //
+ // Set Port 0 un-used
+ //
+ MmioOr32 (
+ (XhciMmioBase + 0x880C),
+ (UINT32) (BIT31)
+ );
+ //
+ // Clear Port 1 un-used
+ //
+ MmioAnd32 (
+ (XhciMmioBase + 0x883C),
+ (UINT32) ~(BIT31)
+ );
+
+ //
+ // Set PROG_DONE bit,
+ // xHCIBAR + 0x880C [30] = 1b and xHCIBAR + 0x883C [30] = 1b.
+ //
+ MmioOr32 (
+ (XhciMmioBase + 0x880C),
+ (UINT32) (BIT30)
+ );
+ MmioOr32 (
+ (XhciMmioBase + 0x883C),
+ (UINT32) (BIT30)
+ );
+ }
+ DEBUG ((EFI_D_INFO, "UsbInitAtBoot() - End\n"));
+}
diff --git a/ChvRefCodePkg/CherryViewSoc/SouthCluster/PchInit/Common/PchUsbCommon.h b/ChvRefCodePkg/CherryViewSoc/SouthCluster/PchInit/Common/PchUsbCommon.h new file mode 100644 index 0000000000..0170197325 --- /dev/null +++ b/ChvRefCodePkg/CherryViewSoc/SouthCluster/PchInit/Common/PchUsbCommon.h @@ -0,0 +1,168 @@ +/** @file
+ Header file for the PCH USB Common Driver.
+
+ Copyright (c) 2012 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _USB_COMMON_H_
+#define _USB_COMMON_H_
+
+#include "PchAccess.h"
+#include <Library/PchPlatformLib.h>
+#include "PchInitCommon.h"
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+
+/**
+ Configures PCH USB controller
+
+ @param[in] UsbConfig The PCH Platform Policy for USB configuration
+ @param[in] XhciMmioBase Memory base address of XHCI Controller
+ @param[in] BusNumber PCI Bus Number of the PCH device
+ @param[in,out] FuncDisableReg Function Disable Register
+ @param[in,out] FuncDisable2Reg Function Disable 2 Register
+ @param[in] Revision The policy revision used for backward compatible check
+
+ @retval EFI_INVALID_PARAMETER The parameter of PchPlatformPolicy is invalid
+ @retval EFI_SUCCESS The function completed successfully
+**/
+EFI_STATUS
+EFIAPI
+CommonUsbInit (
+ IN PCH_USB_CONFIG *UsbConfig,
+ IN UINT32 XhciMmioBase,
+ IN UINT8 BusNumber,
+ IN OUT UINT32 *FuncDisableReg,
+ IN OUT UINT32 *FuncDisableReg2,
+ IN UINT8 Revision
+ );
+
+/**
+ Performs basic configuration of PCH USB3 (xHCI) controller.
+
+ @param[in] UsbConfig The PCH Platform Policy for USB configuration
+ @param[in] XhciMmioBase Memory base address of xHCI Controller
+ @param[in] Revision The policy revision used for backward compatible check
+ @param[in] LpcDeviceId The device ID of LPC
+ @param[in] XhciPciMmBase XHCI PCI Base Address
+
+
+**/
+VOID
+CommonXhciHcInit (
+ IN PCH_USB_CONFIG *UsbConfig,
+ IN UINT32 XhciMmioBase,
+ IN UINT8 Revision,
+ IN UINTN XhciPciMmBase
+ );
+
+/**
+ Setup XHCI Over-Current Mapping
+
+ @param[in] UsbConfig The PCH Platform Policy for USB configuration
+ @param[in] XhciPciMmBase XHCI PCI Base Address
+
+**/
+VOID
+XhciOverCurrentMapping (
+ IN PCH_USB_CONFIG *UsbConfig,
+ IN UINTN XhciPciMmBase
+ );
+
+/**
+ Program Xhci Port Disable Override
+
+ @param[in] UsbConfig The PCH Platform Policy for USB configuration
+ @param[in] XhciMmioBase Memory base address of xHCI Controller
+
+**/
+VOID
+XhciPortDisableOverride (
+ IN PCH_USB_CONFIG *UsbConfig,
+ IN UINT32 XhciMmioBase
+ );
+
+/**
+ Program and enable XHCI Memory Space
+
+ @param[in] UsbConfig The PCH Platform Policy for USB configuration
+ @param[in] XhciMmioBase Memory base address of XHCI Controller
+ @param[in] XhciPciMmBase XHCI PCI Base Address
+
+**/
+VOID
+XhciMemorySpaceOpen (
+ IN PCH_USB_CONFIG *UsbConfig,
+ IN UINT32 XhciMmioBase,
+ IN UINTN XhciPciMmBase
+ );
+
+/**
+ Clear and disable XHCI Memory Space
+
+ @param[in] UsbConfig The PCH Platform Policy for USB configuration
+ @param[in] XhciMmioBase Memory base address of XHCI Controller
+ @param[in] XhciPciMmBase XHCI PCI Base Address
+
+**/
+VOID
+XhciMemorySpaceClose (
+ IN PCH_USB_CONFIG *UsbConfig,
+ IN UINT32 XhciMmioBase,
+ IN UINTN XhciPciMmBase
+ );
+
+/**
+ USB initialization before boot to OS
+
+ @param[in] UsbConfig The PCH Platform Policy for USB configuration
+
+**/
+VOID
+UsbInitAtBoot (
+ IN PCH_USB_CONFIG *UsbConfig
+);
+
+/**
+ Lock USB registers before boot
+
+ @param[in] UsbConfig The PCH Platform Policy for USB configuration
+
+**/
+VOID
+UsbLateInit (
+ IN PCH_USB_CONFIG *UsbConfig
+);
+
+/**
+ Initialization USB Clock Gating registers
+
+ @param[in] PchPlatformPolicy The PCH Platform Policy
+
+**/
+VOID
+ConfigureUsbClockGating (
+ IN DXE_PCH_PLATFORM_POLICY_PROTOCOL *PchPlatformPolicy
+ );
+
+/**
+ Initialization XHCI Clock Gating registers
+
+ @param[in] PchPlatformPolicy The PCH Platform Policy
+
+**/
+VOID
+ConfigureXhciClockGating (
+ IN DXE_PCH_PLATFORM_POLICY_PROTOCOL *PchPlatformPolicy
+ );
+
+#endif
diff --git a/ChvRefCodePkg/CherryViewSoc/SouthCluster/PchInit/Dxe/PchDebugDump.c b/ChvRefCodePkg/CherryViewSoc/SouthCluster/PchInit/Dxe/PchDebugDump.c new file mode 100644 index 0000000000..aa741495f2 --- /dev/null +++ b/ChvRefCodePkg/CherryViewSoc/SouthCluster/PchInit/Dxe/PchDebugDump.c @@ -0,0 +1,237 @@ +/** @file
+ Dump whole DXE_PCH_PLATFORM_POLICY_PROTOCOL and serial out.
+
+ Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "PchInit.h"
+
+/**
+ Dump whole DXE_PCH_PLATFORM_POLICY_PROTOCOL and serial out.
+
+ @param[in] PchPlatformPolicy The PCH Platform Policy protocol instance
+
+**/
+VOID
+PchDumpPlatformProtocol (
+ IN DXE_PCH_PLATFORM_POLICY_PROTOCOL *PchPlatformPolicy
+ )
+{
+#ifdef EFI_DEBUG
+ UINT8 i;
+
+ DEBUG ((EFI_D_INFO, "\n"));
+ DEBUG ((EFI_D_INFO, "------------------------ PCH Dump platform protocol Start -----------------\n"));
+ DEBUG ((EFI_D_INFO, " PCH PLATFORM POLICY Revision= %x\n", PchPlatformPolicy->Revision));
+ DEBUG ((EFI_D_INFO, " PCH PLATFORM POLICY BusNumber= %x\n", PchPlatformPolicy->BusNumber));
+ DEBUG ((EFI_D_INFO, " PCH PLATFORM POLICY PnpSettings= %x\n", PchPlatformPolicy->PnpSettings));
+ DEBUG ((EFI_D_INFO, " PCH PLATFORM POLICY S0ixSupport= %x\n", PchPlatformPolicy->S0ixSupport));
+ DEBUG ((EFI_D_INFO, " PCH PLATFORM POLICY AcpiHwRed= %x\n", PchPlatformPolicy->AcpiHwRed));
+
+ DEBUG ((EFI_D_INFO, "\n"));
+ DEBUG ((EFI_D_INFO, "------------------------ PCH_DEVICE_ENABLE -----------------\n"));
+ DEBUG ((EFI_D_INFO, " PCH_DEVICE_ENABLE Azalia= %x\n", PchPlatformPolicy->DeviceEnabling->Azalia));
+#ifdef SATA_SUPPORT
+ DEBUG ((EFI_D_INFO, " PCH_DEVICE_ENABLE Sata= %x\n", PchPlatformPolicy->DeviceEnabling->Sata));
+#endif
+ DEBUG ((EFI_D_INFO, " PCH_DEVICE_ENABLE Smbus= %x\n", PchPlatformPolicy->DeviceEnabling->Smbus));
+ DEBUG ((EFI_D_INFO, " PCH_DEVICE_ENABLE LpeEnabled= %x\n", PchPlatformPolicy->DeviceEnabling->LpeEnabled));
+ DEBUG ((EFI_D_INFO, " PCH_DEVICE_ENABLE IshEnabled= %x\n", PchPlatformPolicy->DeviceEnabling->IshEnabled));
+ DEBUG ((EFI_D_INFO, " PCH_DEVICE_ENABLE PlatformClock[0]= %x\n", PchPlatformPolicy->DeviceEnabling->PlatformClock[0]));
+ DEBUG ((EFI_D_INFO, " PCH_DEVICE_ENABLE PlatformClock[1]= %x\n", PchPlatformPolicy->DeviceEnabling->PlatformClock[1]));
+ DEBUG ((EFI_D_INFO, " PCH_DEVICE_ENABLE PlatformClock[2]= %x\n", PchPlatformPolicy->DeviceEnabling->PlatformClock[2]));
+ DEBUG ((EFI_D_INFO, " PCH_DEVICE_ENABLE PlatformClock[3]= %x\n", PchPlatformPolicy->DeviceEnabling->PlatformClock[3]));
+ DEBUG ((EFI_D_INFO, " PCH_DEVICE_ENABLE PlatformClock[4]= %x\n", PchPlatformPolicy->DeviceEnabling->PlatformClock[4]));
+ DEBUG ((EFI_D_INFO, " PCH_DEVICE_ENABLE PlatformClock[5]= %x\n", PchPlatformPolicy->DeviceEnabling->PlatformClock[5]));
+
+ DEBUG ((EFI_D_INFO, "\n"));
+ DEBUG ((EFI_D_INFO, "------------------------ PCH_USB_CONFIG -----------------\n"));
+ DEBUG ((EFI_D_INFO, " PCH_USB_CONFIG SsicEnable = %x\n", PchPlatformPolicy->UsbConfig->SsicEnable));
+ for (i = 0; i < PCH_USB_MAX_PHYSICAL_PORTS; i++) {
+ DEBUG ((EFI_D_INFO, " PCH_USB_CONFIG Usb20PortSettings[%d] Enabled= %x\n", i, PchPlatformPolicy->UsbConfig->Usb20PortSettings[i].Enable));
+ }
+ for (i = 0; i < PCH_XHCI_MAX_USB3_PORTS; i++) {
+ DEBUG ((EFI_D_INFO, " PCH_USB_CONFIG Usb30PortSettings[%d] Enabled= %x\n", i, PchPlatformPolicy->UsbConfig->Usb30PortSettings[i].Enable));
+ }
+ for (i = 0; i < PCH_HSIC_MAX_PORTS; i++) {
+ DEBUG ((EFI_D_INFO, " PCH_USB_CONFIG HsicPortSettings[%d] Enabled= %x\n", i, PchPlatformPolicy->UsbConfig->HsicPortSettings[i].Enable));
+ }
+ for (i = 0; i < PCH_SSIC_MAX_PORTS; i++) {
+ DEBUG ((EFI_D_INFO, " PCH_USB_CONFIG SsicPortSettings[%d] Enabled= %x\n", i, PchPlatformPolicy->UsbConfig->SsicPortSettings[i].Enable));
+ }
+ DEBUG ((EFI_D_INFO, " PCH_USB_CONFIG Usb30Settings.Mode= %x\n", PchPlatformPolicy->UsbConfig->Usb30Settings.Mode));
+ DEBUG ((EFI_D_INFO, " PCH_USB_CONFIG UsbOtgSettings.Enable= %x\n", PchPlatformPolicy->UsbConfig->UsbOtgSettings.Enable));
+ for (i = 0; i < PCH_USB_MAX_PHYSICAL_PORTS; i++) {
+ DEBUG ((EFI_D_INFO, " PCH_USB_CONFIG Usb20OverCurrentPins[%d]= OC%x\n", i, PchPlatformPolicy->UsbConfig->Usb20OverCurrentPins[i]));
+ }
+ for (i = 0; i < PCH_XHCI_MAX_USB3_PORTS; i++) {
+ DEBUG ((EFI_D_INFO, " PCH_USB_CONFIG Usb30OverCurrentPins[%d]= OC%x\n", i, PchPlatformPolicy->UsbConfig->Usb30OverCurrentPins[i]));
+ }
+
+#ifdef PCIESC_SUPPORT
+ DEBUG ((EFI_D_INFO, "\n"));
+ DEBUG ((EFI_D_INFO, "------------------------ PCH_PCI_EXPRESS_CONFIG -----------------\n"));
+ DEBUG ((EFI_D_INFO, " PCH_PCI_EXPRESS_CONFIG TempRootPortBusNumMin= %x\n", PchPlatformPolicy->PciExpressConfig->TempRootPortBusNumMin));
+ DEBUG ((EFI_D_INFO, " PCH_PCI_EXPRESS_CONFIG TempRootPortBusNumMax= %x\n", PchPlatformPolicy->PciExpressConfig->TempRootPortBusNumMax));
+ for (i = 0; i < PCH_PCIE_MAX_ROOT_PORTS; i++) {
+ DEBUG ((EFI_D_INFO, " PCH_PCI_EXPRESS_CONFIG RootPort[%d] Enabled= %x\n", i, PchPlatformPolicy->PciExpressConfig->RootPort[i].Enable));
+ DEBUG ((EFI_D_INFO, " PCH_PCI_EXPRESS_CONFIG RootPort[%d] Hide= %x\n", i, PchPlatformPolicy->PciExpressConfig->RootPort[i].Hide));
+ DEBUG ((EFI_D_INFO, " PCH_PCI_EXPRESS_CONFIG RootPort[%d] SlotImplemented= %x\n", i, PchPlatformPolicy->PciExpressConfig->RootPort[i].SlotImplemented));
+ DEBUG ((EFI_D_INFO, " PCH_PCI_EXPRESS_CONFIG RootPort[%d] HotPlug= %x\n", i, PchPlatformPolicy->PciExpressConfig->RootPort[i].HotPlug));
+ DEBUG ((EFI_D_INFO, " PCH_PCI_EXPRESS_CONFIG RootPort[%d] PmSci= %x\n", i, PchPlatformPolicy->PciExpressConfig->RootPort[i].PmSci));
+ DEBUG ((EFI_D_INFO, " PCH_PCI_EXPRESS_CONFIG RootPort[%d] ExtSync= %x\n", i, PchPlatformPolicy->PciExpressConfig->RootPort[i].ExtSync));
+ DEBUG ((EFI_D_INFO, " PCH_PCI_EXPRESS_CONFIG RootPort[%d] UnsupportedRequestReport= %x\n", i, PchPlatformPolicy->PciExpressConfig->RootPort[i].UnsupportedRequestReport));
+ DEBUG ((EFI_D_INFO, " PCH_PCI_EXPRESS_CONFIG RootPort[%d] FatalErrorReport= %x\n", i, PchPlatformPolicy->PciExpressConfig->RootPort[i].FatalErrorReport));
+ DEBUG ((EFI_D_INFO, " PCH_PCI_EXPRESS_CONFIG RootPort[%d] NoFatalErrorReport= %x\n", i, PchPlatformPolicy->PciExpressConfig->RootPort[i].NoFatalErrorReport));
+ DEBUG ((EFI_D_INFO, " PCH_PCI_EXPRESS_CONFIG RootPort[%d] CorrectableErrorReport= %x\n", i, PchPlatformPolicy->PciExpressConfig->RootPort[i].CorrectableErrorReport));
+ DEBUG ((EFI_D_INFO, " PCH_PCI_EXPRESS_CONFIG RootPort[%d] PmeInterrupt= %x\n", i, PchPlatformPolicy->PciExpressConfig->RootPort[i].PmeInterrupt));
+ DEBUG ((EFI_D_INFO, " PCH_PCI_EXPRESS_CONFIG RootPort[%d] SystemErrorOnFatalError= %x\n", i, PchPlatformPolicy->PciExpressConfig->RootPort[i].SystemErrorOnFatalError));
+ DEBUG ((EFI_D_INFO, " PCH_PCI_EXPRESS_CONFIG RootPort[%d] SystemErrorOnNonFatalError= %x\n", i, PchPlatformPolicy->PciExpressConfig->RootPort[i].SystemErrorOnNonFatalError));
+ DEBUG ((EFI_D_INFO, " PCH_PCI_EXPRESS_CONFIG RootPort[%d] SystemErrorOnCorrectableError= %x\n", i, PchPlatformPolicy->PciExpressConfig->RootPort[i].SystemErrorOnCorrectableError));
+ DEBUG ((EFI_D_INFO, " PCH_PCI_EXPRESS_CONFIG RootPort[%d] AdvancedErrorReporting= %x\n", i, PchPlatformPolicy->PciExpressConfig->RootPort[i].AdvancedErrorReporting));
+ DEBUG ((EFI_D_INFO, " PCH_PCI_EXPRESS_CONFIG RootPort[%d] TransmitterHalfSwing= %x\n", i, PchPlatformPolicy->PciExpressConfig->RootPort[i].TransmitterHalfSwing));
+ DEBUG ((EFI_D_INFO, " PCH_PCI_EXPRESS_CONFIG RootPort[%d] FunctionNumber= %x\n", i, PchPlatformPolicy->PciExpressConfig->RootPort[i].FunctionNumber));
+ DEBUG ((EFI_D_INFO, " PCH_PCI_EXPRESS_CONFIG RootPort[%d] PhysicalSlotNumber= %x\n", i, PchPlatformPolicy->PciExpressConfig->RootPort[i].PhysicalSlotNumber));
+ DEBUG ((EFI_D_INFO, " PCH_PCI_EXPRESS_CONFIG RootPort[%d] CompletionTimeout= %x\n", i, PchPlatformPolicy->PciExpressConfig->RootPort[i].CompletionTimeout));
+ DEBUG ((EFI_D_INFO, " PCH_PCI_EXPRESS_CONFIG RootPort[%d] Aspm= %x\n", i, PchPlatformPolicy->PciExpressConfig->RootPort[i].Aspm));
+ DEBUG ((EFI_D_INFO, " PCH_PCI_EXPRESS_CONFIG RootPort[%d] L1Substates= %x\n", i, PchPlatformPolicy->PciExpressConfig->RootPort[i].L1Substates));
+ DEBUG ((EFI_D_INFO, " PCH_PCI_EXPRESS_CONFIG RootPort[%d] TxEqDeemphSelection= %x\n", i, PchPlatformPolicy->PciExpressConfig->RootPort[i].TxEqdeEmphSelection));
+ }
+ DEBUG ((EFI_D_INFO, " PCH_PCI_EXPRESS_CONFIG NumOfDevAspmOverride= %x\n", PchPlatformPolicy->PciExpressConfig->NumOfDevAspmOverride));
+ DEBUG ((EFI_D_INFO, " PCH_PCI_EXPRESS_CONFIG DevAspmOverride VendorId= %x\n", PchPlatformPolicy->PciExpressConfig->DevAspmOverride->VendorId));
+ DEBUG ((EFI_D_INFO, " PCH_PCI_EXPRESS_CONFIG DevAspmOverride DeviceId= %x\n", PchPlatformPolicy->PciExpressConfig->DevAspmOverride->DeviceId));
+ DEBUG ((EFI_D_INFO, " PCH_PCI_EXPRESS_CONFIG DevAspmOverride RevId= %x\n", PchPlatformPolicy->PciExpressConfig->DevAspmOverride->RevId));
+ DEBUG ((EFI_D_INFO, " PCH_PCI_EXPRESS_CONFIG DevAspmOverride BaseClassCode= %x\n", PchPlatformPolicy->PciExpressConfig->DevAspmOverride->BaseClassCode));
+ DEBUG ((EFI_D_INFO, " PCH_PCI_EXPRESS_CONFIG DevAspmOverride SubClassCode= %x\n", PchPlatformPolicy->PciExpressConfig->DevAspmOverride->SubClassCode));
+ DEBUG ((EFI_D_INFO, " PCH_PCI_EXPRESS_CONFIG DevAspmOverride EndPointAspm= %x\n", PchPlatformPolicy->PciExpressConfig->DevAspmOverride->EndPointAspm));
+ DEBUG ((EFI_D_INFO, " PCH_PCI_EXPRESS_CONFIG RootPortClockGating= %x\n", PchPlatformPolicy->PciExpressConfig->RootPortClockGating));
+#endif
+
+ DEBUG ((EFI_D_INFO, "\n"));
+#ifdef SATA_SUPPORT
+ DEBUG ((EFI_D_INFO, "------------------------ PCH_SATA_CONFIG -----------------\n"));
+ for (i = 0; i < PCH_AHCI_MAX_PORTS; i++) {
+ DEBUG ((EFI_D_INFO, " PCH_SATA_CONFIG PortSettings[%d] Enabled= %x\n", i, PchPlatformPolicy->SataConfig->PortSettings[i].Enable));
+ DEBUG ((EFI_D_INFO, " PCH_SATA_CONFIG PortSettings[%d] HotPlug= %x\n", i, PchPlatformPolicy->SataConfig->PortSettings[i].HotPlug));
+ DEBUG ((EFI_D_INFO, " PCH_SATA_CONFIG PortSettings[%d] MechSw= %x\n", i, PchPlatformPolicy->SataConfig->PortSettings[i].MechSw));
+ DEBUG ((EFI_D_INFO, " PCH_SATA_CONFIG PortSettings[%d] External= %x\n", i, PchPlatformPolicy->SataConfig->PortSettings[i].External));
+ DEBUG ((EFI_D_INFO, " PCH_SATA_CONFIG PortSettings[%d] DevSlp= %x\n", i, PchPlatformPolicy->SataConfig->PortSettings[i].DevSlp));
+ }
+ DEBUG ((EFI_D_INFO, " PCH_SATA_CONFIG RaidAlternateId= %x\n", PchPlatformPolicy->SataConfig->RaidAlternateId));
+ DEBUG ((EFI_D_INFO, " PCH_SATA_CONFIG Raid0= %x\n", PchPlatformPolicy->SataConfig->Raid0));
+ DEBUG ((EFI_D_INFO, " PCH_SATA_CONFIG Raid1= %x\n", PchPlatformPolicy->SataConfig->Raid1));
+ DEBUG ((EFI_D_INFO, " PCH_SATA_CONFIG Raid10= %x\n", PchPlatformPolicy->SataConfig->Raid10));
+ DEBUG ((EFI_D_INFO, " PCH_SATA_CONFIG Raid5= %x\n", PchPlatformPolicy->SataConfig->Raid5));
+ DEBUG ((EFI_D_INFO, " PCH_SATA_CONFIG Irrt= %x\n", PchPlatformPolicy->SataConfig->Irrt));
+ DEBUG ((EFI_D_INFO, " PCH_SATA_CONFIG OromUiBanner= %x\n", PchPlatformPolicy->SataConfig->OromUiBanner));
+ DEBUG ((EFI_D_INFO, " PCH_SATA_CONFIG HddUnlock= %x\n", PchPlatformPolicy->SataConfig->HddUnlock));
+ DEBUG ((EFI_D_INFO, " PCH_SATA_CONFIG LedLocate= %x\n", PchPlatformPolicy->SataConfig->LedLocate));
+ DEBUG ((EFI_D_INFO, " PCH_SATA_CONFIG IrrtOnly= %x\n", PchPlatformPolicy->SataConfig->IrrtOnly));
+ DEBUG ((EFI_D_INFO, " PCH_SATA_CONFIG TestMode= %x\n", PchPlatformPolicy->SataConfig->TestMode));
+ DEBUG ((EFI_D_INFO, " PCH_SATA_CONFIG SpeedSupport= %x\n", PchPlatformPolicy->SataConfig->SpeedSupport));
+#endif
+ DEBUG ((EFI_D_INFO, "\n"));
+ DEBUG ((EFI_D_INFO, "------------------------ PCH_AZALIA_CONFIG -----------------\n"));
+ DEBUG ((EFI_D_INFO, " PCH_AZALIA_CONFIG Pme= %x\n", PchPlatformPolicy->AzaliaConfig->Pme));
+ DEBUG ((EFI_D_INFO, " PCH_AZALIA_CONFIG DS= %x\n", PchPlatformPolicy->AzaliaConfig->DS));
+ DEBUG ((EFI_D_INFO, " PCH_AZALIA_CONFIG DA= %x\n", PchPlatformPolicy->AzaliaConfig->DA));
+ DEBUG ((EFI_D_INFO, " PCH_AZALIA_CONFIG AzaliaVerbTableNum= %x\n", PchPlatformPolicy->AzaliaConfig->AzaliaVerbTableNum));
+ DEBUG ((EFI_D_INFO, " PCH_AZALIA_CONFIG AzaliaVerbTable Header VendorDeviceId= %x\n", PchPlatformPolicy->AzaliaConfig->AzaliaVerbTable->VerbTableHeader.VendorDeviceId));
+ DEBUG ((EFI_D_INFO, " PCH_AZALIA_CONFIG AzaliaVerbTable Header SubSystemId= %x\n", PchPlatformPolicy->AzaliaConfig->AzaliaVerbTable->VerbTableHeader.SubSystemId));
+ DEBUG ((EFI_D_INFO, " PCH_AZALIA_CONFIG AzaliaVerbTable Header RevisionId= %x\n", PchPlatformPolicy->AzaliaConfig->AzaliaVerbTable->VerbTableHeader.RevisionId));
+ DEBUG ((EFI_D_INFO, " PCH_AZALIA_CONFIG AzaliaVerbTable Header FrontPanelSupport= %x\n", PchPlatformPolicy->AzaliaConfig->AzaliaVerbTable->VerbTableHeader.FrontPanelSupport));
+ DEBUG ((EFI_D_INFO, " PCH_AZALIA_CONFIG AzaliaVerbTable Header NumberOfRearJacks= %x\n", PchPlatformPolicy->AzaliaConfig->AzaliaVerbTable->VerbTableHeader.NumberOfRearJacks));
+ DEBUG ((EFI_D_INFO, " PCH_AZALIA_CONFIG AzaliaVerbTable Header NumberOfFrontJacks= %x\n", PchPlatformPolicy->AzaliaConfig->AzaliaVerbTable->VerbTableHeader.NumberOfFrontJacks));
+ DEBUG ((EFI_D_INFO, " PCH_AZALIA_CONFIG AzaliaVerbTable VerbTableData= %x\n", PchPlatformPolicy->AzaliaConfig->AzaliaVerbTable->VerbTableData));
+ DEBUG ((EFI_D_INFO, " PCH_AZALIA_CONFIG ResetWaitTimer= %x\n", PchPlatformPolicy->AzaliaConfig->ResetWaitTimer));
+ DEBUG ((EFI_D_INFO, "\n"));
+ DEBUG ((EFI_D_INFO, "------------------------ PCH_SMBUS_CONFIG -----------------\n"));
+ DEBUG ((EFI_D_INFO, " PCH_SMBUS_CONFIG NumRsvdSmbusAddresses= %x\n", PchPlatformPolicy->SmbusConfig->NumRsvdSmbusAddresses));
+ DEBUG ((EFI_D_INFO, " PCH_SMBUS_CONFIG RsvdSmbusAddressTable= %x\n", PchPlatformPolicy->SmbusConfig->RsvdSmbusAddressTable));
+ DEBUG ((EFI_D_INFO, "\n"));
+ DEBUG ((EFI_D_INFO, "------------------------ PCH_MISC_PM_CONFIG -----------------\n"));
+ DEBUG ((EFI_D_INFO, " PCH_MISC_PM_CONFIG WakeConfig PmeB0S5Dis= %x\n", PchPlatformPolicy->MiscPmConfig->WakeConfig.PmeB0S5Dis));
+ DEBUG ((EFI_D_INFO, " PCH_MISC_PM_CONFIG PchSlpS3MinAssert= %x\n", PchPlatformPolicy->MiscPmConfig->PchSlpS3MinAssert));
+ DEBUG ((EFI_D_INFO, " PCH_MISC_PM_CONFIG PchSlpS4MinAssert= %x\n", PchPlatformPolicy->MiscPmConfig->PchSlpS4MinAssert));
+ DEBUG ((EFI_D_INFO, " PCH_MISC_PM_CONFIG SlpStrchSusUp= %x\n", PchPlatformPolicy->MiscPmConfig->SlpStrchSusUp));
+ DEBUG ((EFI_D_INFO, " PCH_MISC_PM_CONFIG CfioTable location = %x\n", PchPlatformPolicy->MiscPmConfig->CfioTable));
+ DEBUG ((EFI_D_INFO, " PCH_MISC_PM_CONFIG Number of CFIO entries = %x\n", PchPlatformPolicy->MiscPmConfig->CfioEntries));
+
+ DEBUG ((EFI_D_INFO, "\n"));
+ DEBUG ((EFI_D_INFO, "------------------------ PCH_DEFAULT_SVID_SID -----------------\n"));
+ DEBUG ((EFI_D_INFO, " PCH_DEFAULT_SVID_SID SubSystemVendorId= %x\n", PchPlatformPolicy->DefaultSvidSid->SubSystemVendorId));
+ DEBUG ((EFI_D_INFO, " PCH_DEFAULT_SVID_SID SubSystemId= %x\n", PchPlatformPolicy->DefaultSvidSid->SubSystemId));
+
+ DEBUG ((EFI_D_INFO, "\n"));
+ DEBUG ((EFI_D_INFO, "------------------------ PCH_LOCK_DOWN_CONFIG -----------------\n"));
+ DEBUG ((EFI_D_INFO, " PCH_LOCK_DOWN_CONFIG GlobalSmi= %x\n", PchPlatformPolicy->LockDownConfig->GlobalSmi));
+ DEBUG ((EFI_D_INFO, " PCH_LOCK_DOWN_CONFIG BiosInterface= %x\n", PchPlatformPolicy->LockDownConfig->BiosInterface));
+ DEBUG ((EFI_D_INFO, " PCH_LOCK_DOWN_CONFIG RtcLock= %x\n", PchPlatformPolicy->LockDownConfig->RtcLock));
+ DEBUG ((EFI_D_INFO, " PCH_LOCK_DOWN_CONFIG BiosLock= %x\n", PchPlatformPolicy->LockDownConfig->BiosLock));
+ DEBUG ((EFI_D_INFO, " PCH_LOCK_DOWN_CONFIG PchBiosLockSwSmiNumber= %x\n", PchPlatformPolicy->LockDownConfig->PchBiosLockSwSmiNumber));
+
+ DEBUG ((EFI_D_INFO, "\n"));
+ DEBUG ((EFI_D_INFO, "------------------------ PCH_LPC_SIRQ_CONFIG -----------------\n"));
+ DEBUG ((EFI_D_INFO, " PCH_LPC_SIRQ_CONFIG SirqEnable= %x\n", PchPlatformPolicy->SerialIrqConfig->SirqEnable));
+ DEBUG ((EFI_D_INFO, " PCH_LPC_SIRQ_CONFIG SirqMode= %x\n", PchPlatformPolicy->SerialIrqConfig->SirqMode));
+#ifdef PCIESC_SUPPORT
+ DEBUG ((EFI_D_INFO, "\n"));
+ DEBUG ((EFI_D_INFO, "------------------------ PCH_PWR_OPT_CONFIG -----------------\n"));
+ for (i = 0; i < PCH_PCIE_MAX_ROOT_PORTS; i++) {
+ DEBUG ((EFI_D_INFO, " PCH_PWR_OPT_CONFIG RootPort[%d] LtrEnable= %x\n", i, PchPlatformPolicy->PwrOptConfig->PchPwrOptPcie[i].LtrEnable));
+ DEBUG ((EFI_D_INFO, " PCH_PWR_OPT_CONFIG RootPort[%d] ObffEnable= %x\n", i, PchPlatformPolicy->PwrOptConfig->PchPwrOptPcie[i].ObffEnable));
+ }
+ DEBUG ((EFI_D_INFO, " PCH_PWR_OPT_CONFIG NumOfDevLtrOverride= %x\n", PchPlatformPolicy->PwrOptConfig->NumOfDevLtrOverride));
+ DEBUG ((EFI_D_INFO, " PCH_PWR_OPT_CONFIG DevLtrOverride VendorId= %x\n", PchPlatformPolicy->PwrOptConfig->DevLtrOverride->VendorId));
+ DEBUG ((EFI_D_INFO, " PCH_PWR_OPT_CONFIG DevLtrOverride DeviceId= %x\n", PchPlatformPolicy->PwrOptConfig->DevLtrOverride->DeviceId));
+ DEBUG ((EFI_D_INFO, " PCH_PWR_OPT_CONFIG DevLtrOverride RevId= %x\n", PchPlatformPolicy->PwrOptConfig->DevLtrOverride->RevId));
+ DEBUG ((EFI_D_INFO, " PCH_PWR_OPT_CONFIG DevLtrOverride SnoopLatency= %x\n", PchPlatformPolicy->PwrOptConfig->DevLtrOverride->SnoopLatency));
+ DEBUG ((EFI_D_INFO, " PCH_PWR_OPT_CONFIG DevLtrOverride NonSnoopLatency= %x\n", PchPlatformPolicy->PwrOptConfig->DevLtrOverride->NonSnoopLatency));
+#endif
+ DEBUG ((EFI_D_INFO, "\n"));
+ DEBUG ((EFI_D_INFO, "------------------------- PCH_LPSS_CONFIG --------------------\n"));
+ DEBUG ((EFI_D_INFO, " PCH_LPSS_CONFIG Dma1Enabled= %x\n", PchPlatformPolicy->LpssConfig->Dma1Enabled));
+ DEBUG ((EFI_D_INFO, " PCH_LPSS_CONFIG I2C0Enabled= %x\n", PchPlatformPolicy->LpssConfig->I2C0Enabled));
+ DEBUG ((EFI_D_INFO, " PCH_LPSS_CONFIG I2C1Enabled= %x\n", PchPlatformPolicy->LpssConfig->I2C1Enabled));
+ DEBUG ((EFI_D_INFO, " PCH_LPSS_CONFIG I2C2Enabled= %x\n", PchPlatformPolicy->LpssConfig->I2C2Enabled));
+ DEBUG ((EFI_D_INFO, " PCH_LPSS_CONFIG I2C3Enabled= %x\n", PchPlatformPolicy->LpssConfig->I2C3Enabled));
+ DEBUG ((EFI_D_INFO, " PCH_LPSS_CONFIG I2C4Enabled= %x\n", PchPlatformPolicy->LpssConfig->I2C4Enabled));
+ DEBUG ((EFI_D_INFO, " PCH_LPSS_CONFIG I2C5Enabled= %x\n", PchPlatformPolicy->LpssConfig->I2C5Enabled));
+ DEBUG ((EFI_D_INFO, " PCH_LPSS_CONFIG I2C6Enabled= %x\n", PchPlatformPolicy->LpssConfig->I2C6Enabled));
+ DEBUG ((EFI_D_INFO, " PCH_LPSS_CONFIG Dma0Enabled= %x\n", PchPlatformPolicy->LpssConfig->Dma0Enabled));
+ DEBUG ((EFI_D_INFO, " PCH_LPSS_CONFIG Pwm0Enabled= %x\n", PchPlatformPolicy->LpssConfig->Pwm0Enabled));
+ DEBUG ((EFI_D_INFO, " PCH_LPSS_CONFIG Pwm1Enabled= %x\n", PchPlatformPolicy->LpssConfig->Pwm1Enabled));
+ DEBUG ((EFI_D_INFO, " PCH_LPSS_CONFIG Hsuart0Enabled= %x\n", PchPlatformPolicy->LpssConfig->Hsuart0Enabled));
+ DEBUG ((EFI_D_INFO, " PCH_LPSS_CONFIG Hsuart1Enabled= %x\n", PchPlatformPolicy->LpssConfig->Hsuart1Enabled));
+ DEBUG ((EFI_D_INFO, " PCH_LPSS_CONFIG Spi1Enabled= %x\n", PchPlatformPolicy->LpssConfig->Spi1Enabled));
+ DEBUG ((EFI_D_INFO, " PCH_LPSS_CONFIG Spi2Enabled= %x\n", PchPlatformPolicy->LpssConfig->Spi2Enabled));
+ DEBUG ((EFI_D_INFO, " PCH_LPSS_CONFIG Spi3Enabled= %x\n", PchPlatformPolicy->LpssConfig->Spi3Enabled));
+
+ DEBUG ((EFI_D_INFO, "\n"));
+ DEBUG ((EFI_D_INFO, "------------------------- PCH_SCC_CONFIG --------------------\n"));
+ DEBUG ((EFI_D_INFO, " PCH_SCC_CONFIG eMMCEnabled= %x\n", PchPlatformPolicy->SccConfig->eMMCEnabled));
+ DEBUG ((EFI_D_INFO, " PCH_SCC_CONFIG SdioEnabled= %x\n", PchPlatformPolicy->SccConfig->SdioEnabled));
+ DEBUG ((EFI_D_INFO, " PCH_SCC_CONFIG SdcardEnabled= %x\n", PchPlatformPolicy->SccConfig->SdcardEnabled));
+ DEBUG ((EFI_D_INFO, " PCH_SCC_CONFIG EmmcDriverMode= %x\n", PchPlatformPolicy->SccConfig->EmmcDriverMode));
+ DEBUG ((EFI_D_INFO, " PCH_SCC_CONFIG SccEmmcDllTuningRequired= %x\n", PchPlatformPolicy->SccConfig->SccEmmcDllTuningRequired));
+ DEBUG ((EFI_D_INFO, " PCH_SCC_CONFIG SccEmmcRxDllTuningEnabled= %x\n", PchPlatformPolicy->SccConfig->SccEmmcRxDllTuningEnabled));
+ DEBUG ((EFI_D_INFO, " PCH_SCC_CONFIG SccEmmcTxDllTuningEnabled= %x\n", PchPlatformPolicy->SccConfig->SccEmmcTxDllTuningEnabled));
+ DEBUG ((EFI_D_INFO, " PCH_SCC_CONFIG SccEmmcRxDllDataValid= %x\n", PchPlatformPolicy->SccConfig->SccEmmcRxDllDataValid));
+ DEBUG ((EFI_D_INFO, " PCH_SCC_CONFIG SccEmmcTxDllDataValid= %x\n", PchPlatformPolicy->SccConfig->SccEmmcTxDllDataValid));
+ DEBUG ((EFI_D_INFO, " PCH_SCC_CONFIG SccEmmcRxStrobeDllValue= %x\n", PchPlatformPolicy->SccConfig->SccEmmcRxStrobeDllValue));
+ DEBUG ((EFI_D_INFO, " PCH_SCC_CONFIG SccEmmcTxDataDllValue= %x\n", PchPlatformPolicy->SccConfig->SccEmmcTxDataDllValue));
+
+ DEBUG ((EFI_D_INFO, "\n"));
+ DEBUG ((EFI_D_INFO, "------------------------ PCH Dump platform protocol End -----------------\n"));
+ DEBUG ((EFI_D_INFO, "\n"));
+#endif
+}
diff --git a/ChvRefCodePkg/CherryViewSoc/SouthCluster/PchInit/Dxe/PchInit.c b/ChvRefCodePkg/CherryViewSoc/SouthCluster/PchInit/Dxe/PchInit.c new file mode 100644 index 0000000000..800d0adb2d --- /dev/null +++ b/ChvRefCodePkg/CherryViewSoc/SouthCluster/PchInit/Dxe/PchInit.c @@ -0,0 +1,538 @@ +/** @file
+ This is the driver that initializes the Intel PCH.
+
+ Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "PchInit.h"
+#ifndef FSP_FLAG
+#include <Library/UefiDriverEntryPoint.h>
+#endif
+#include <IndustryStandard/Pci22.h>
+
+//
+// Global Variables
+//
+EFI_HANDLE mImageHandle;
+
+//
+// Local function prototypes
+//
+EFI_STATUS
+InitializePchDevice (
+#ifndef FSP_FLAG
+ IN OUT PCH_INSTANCE_PRIVATE_DATA *PchInstance,
+#else
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+#endif
+ IN DXE_PCH_PLATFORM_POLICY_PROTOCOL *PchPlatformPolicy
+);
+
+EFI_STATUS
+EFIAPI
+PchExitBootServicesEvent (
+#ifndef FSP_FLAG
+ IN EFI_EVENT Event,
+ IN VOID *Context
+#else
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
+ IN VOID *Ppi
+#endif
+ );
+
+EFI_STATUS
+EFIAPI
+PchInitBeforeBoot (
+#ifndef FSP_FLAG
+ IN EFI_EVENT Event,
+ IN VOID *Context
+#else
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
+ IN VOID *Ppi
+#endif
+ );
+
+/**
+ Set an IOSF-SB extended programming S3 dispatch item, this function may assert if any error happened
+
+ @param[in] PortId Port ID of the target IOSF-SB block
+ @param[in] Register Register of the target IOSF-SB block
+ @param[in] AndData Value to be ANDed
+ @param[in] OrData Value to be ORed
+ @param[in] ReadOpCode Read Op Code
+ @param[in] WriteOpCode Write Op Code
+ @param[in] Bar BAR
+ @param[in] Device Device Number
+ @param[in] Function Function Number
+
+ @retval EFI_SUCCESS The function completed successfully
+**/
+EFI_STATUS
+SetMsgBusAndThenOrEx32S3Item (
+ IN UINT8 PortId,
+ IN UINT32 Register,
+ IN UINT32 AndData,
+ IN UINT32 OrData,
+ IN UINT8 ReadOpCode,
+ IN UINT8 WriteOpCode,
+ IN UINT8 Bar,
+ IN UINT8 Device,
+ IN UINT8 Function
+
+ )
+{
+#ifdef EFI_S3_RESUME
+ UINTN PciExBaseAddress;
+ UINT32 Buffer32;
+
+ Buffer32 = 0;
+ PciExBaseAddress = (UINTN) PcdGet64 (PcdPciExpressBaseAddress);
+
+ Buffer32 = (UINT32) (((Bar & 0x07) << 8) | (((Device << 3) | (Function)) & 0xFF));
+ S3BootScriptSaveMemWrite (
+ EfiBootScriptWidthUint32,
+ (UINTN) (PciExBaseAddress + MC_MCRXX),
+ 1,
+ &Buffer32
+ );
+ Buffer32 = (UINT32) (Register & MSGBUS_MASKHI);
+ S3BootScriptSaveMemWrite (
+ EfiBootScriptWidthUint32,
+ (UINTN) (PciExBaseAddress + MC_MCRX),
+ 1,
+ &Buffer32
+ );
+ Buffer32 = (UINT32) ((ReadOpCode << 24) | (PortId << 16) | ((Register & MSGBUS_MASKLO) << 8) | MESSAGE_DWORD_EN);
+ S3BootScriptSaveMemWrite (
+ EfiBootScriptWidthUint32,
+ (UINTN) (PciExBaseAddress + MC_MCR),
+ 1,
+ &Buffer32
+ );
+ S3BootScriptSaveMemReadWrite (
+ EfiBootScriptWidthUint32,
+ (UINTN) (PciExBaseAddress+ MC_MDR),
+ &OrData, // Data to be ORed
+ &AndData // Data to be ANDed
+ );
+ Buffer32 = (UINT32) (((Bar & 0x07) << 8) | (((Device << 3) | (Function)) & 0xFF));
+ S3BootScriptSaveMemWrite (
+ EfiBootScriptWidthUint32,
+ (UINTN) (PciExBaseAddress + MC_MCRXX),
+ 1,
+ &Buffer32
+ );
+ Buffer32 = (UINT32) (Register & MSGBUS_MASKHI);
+ S3BootScriptSaveMemWrite (
+ EfiBootScriptWidthUint32,
+ (UINTN) (PciExBaseAddress + MC_MCRX),
+ 1,
+ &Buffer32
+ );
+ Buffer32 = (UINT32) ((WriteOpCode << 24) | (PortId << 16) | ((Register & MSGBUS_MASKLO) << 8) | MESSAGE_DWORD_EN);
+ S3BootScriptSaveMemWrite (
+ EfiBootScriptWidthUint32,
+ (UINTN) (PciExBaseAddress + MC_MCR),
+ 1,
+ &Buffer32
+ );
+#endif
+ return EFI_SUCCESS;
+}
+
+/**
+ Set an IOSF-SB programming S3 dispatch item, this function may assert if any error happened
+
+ @param[in] PortId Port ID of the target IOSF-SB block
+ @param[in] Register Register of the target IOSF-SB block
+ @param[in] AndData Value to be ANDed
+ @param[in] OrData Value to be ORed
+ @param[in] ReadOpCode Read Op Code
+ @param[in] WriteOpCode Write Op Code
+
+ @retval EFI_SUCCESS The function completed successfully
+**/
+EFI_STATUS
+SetMsgBusAndThenOr32S3Item (
+ IN UINT8 PortId,
+ IN UINT32 Register,
+ IN UINT32 AndData,
+ IN UINT32 OrData,
+ IN UINT8 ReadOpCode,
+ IN UINT8 WriteOpCode
+ )
+{
+ return (SetMsgBusAndThenOrEx32S3Item (PortId, Register, AndData, OrData, ReadOpCode, WriteOpCode, 0x00, 0x00, 0x00));
+}
+
+/**
+ Configures extended IOSF-SB and stores this configuration in S3 boot script
+
+ @param[in] PortId Port ID of the target IOSF-SB block
+ @param[in] Register Register of the target IOSF-SB block
+ @param[in] AndData Value to be ANDed
+ @param[in] OrData Value to be ORed
+ @param[in] ReadOpCode Read Op Code
+ @param[in] WriteOpCode Write Op Code
+ @param[in] Bar BAR
+ @param[in] Device Device Number
+ @param[in] Function Function Number
+
+**/
+VOID
+PchMsgBusAndThenOrEx32WithScript (
+ IN UINT8 PortId,
+ IN UINT32 Register,
+ IN UINT32 AndData,
+ IN UINT32 OrData,
+ IN UINT8 ReadOpCode,
+ IN UINT8 WriteOpCode,
+ IN UINT8 Bar,
+ IN UINT8 Device,
+ IN UINT8 Function
+ )
+{
+ EFI_STATUS Status;
+
+ Status = PchMsgBusAndThenOrEx32 (PortId, Register, AndData, OrData, ReadOpCode, WriteOpCode, Bar, Device, Function);
+ ASSERT_EFI_ERROR (Status);
+
+ Status = PCH_INIT_COMMON_SCRIPT_MSG_BUS_AND_THEN_OR_EX_32_S3_ITEM (
+ PortId,
+ Register,
+ AndData,
+ OrData,
+ ReadOpCode,
+ WriteOpCode,
+ Bar,
+ Device,
+ Function
+ );
+ ASSERT_EFI_ERROR (Status);
+}
+
+/**
+ Configures IOSF-SB and stores this configuration in S3 boot script
+
+ @param[in] PortId Port ID of the target IOSF-SB block
+ @param[in] Register Register of the target IOSF-SB block
+ @param[in] AndData Value to be ANDed
+ @param[in] OrData Value to be ORed
+ @param[in] ReadOpCode Read Op Code
+ @param[in] WriteOpCode Write Op Code
+
+**/
+VOID
+PchMsgBusAndThenOr32WithScript (
+ IN UINT8 PortId,
+ IN UINT32 Register,
+ IN UINT32 AndData,
+ IN UINT32 OrData,
+ IN UINT8 ReadOpCode,
+ IN UINT8 WriteOpCode
+ )
+{
+ PchMsgBusAndThenOrEx32WithScript (PortId, Register, AndData, OrData, ReadOpCode, WriteOpCode, 0x00, 0x00, 0x00);
+ return;
+}
+
+/**
+ This is the standard EFI driver point that detects
+ whether there is a south cluster in the system
+ and if so, initializes the chip.
+
+ @param[in] ImageHandle Handle for the image of this driver
+ @param[in] SystemTable Pointer to the EFI System Table
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver
+**/
+EFI_STATUS
+EFIAPI
+PchInitEntryPoint (
+#ifndef FSP_FLAG
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+#else
+ IN EFI_PEI_FILE_HANDLE FfsHeader,
+ IN CONST EFI_PEI_SERVICES **PeiServices
+#endif
+ )
+{
+ EFI_STATUS Status;
+ UINT8 BusNumber;
+ DXE_PCH_PLATFORM_POLICY_PROTOCOL *PchPlatformPolicy;
+ UINTN NumHandles;
+ EFI_HANDLE *HandleBuffer;
+ UINT32 Index;
+ PCH_INSTANCE_PRIVATE_DATA *PchInstance;
+
+ DEBUG ((EFI_D_INFO, "PchInitEntryPoint() Start\n"));
+
+ PchInstance = NULL;
+ PchPlatformPolicy = NULL;
+
+#ifndef FSP_FLAG
+ mImageHandle = ImageHandle;
+
+ //
+ // Retrieve all instances of PCH Platform Policy protocol
+ //
+ Status = gBS->LocateHandleBuffer (
+ ByProtocol,
+ &gDxePchPlatformPolicyProtocolGuid,
+ NULL,
+ &NumHandles,
+ &HandleBuffer
+ );
+ ASSERT_EFI_ERROR (Status);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+#else
+ NumHandles = 1;
+#endif
+
+ for (Index = 0; Index < NumHandles; Index++) {
+#ifndef FSP_FLAG
+ Status = gBS->HandleProtocol (
+ HandleBuffer[Index],
+ &gDxePchPlatformPolicyProtocolGuid,
+ (VOID **) &PchPlatformPolicy
+ );
+ ASSERT_EFI_ERROR (Status);
+
+#else
+ //
+ // PCH Policy
+ //
+ Status = (**PeiServices).LocatePpi (
+ PeiServices,
+ &gDxePchPlatformPolicyProtocolGuid,
+ 0,
+ NULL,
+ (VOID **) &PchPlatformPolicy
+ );
+ ASSERT_EFI_ERROR (Status);
+#endif
+ BusNumber = PchPlatformPolicy->BusNumber;
+
+ //
+ // Dump whole DXE_PCH_PLATFORM_POLICY_PROTOCOL and serial out.
+ //
+ PchDumpPlatformProtocol (PchPlatformPolicy);
+
+ //
+ // Initialize the PCH device
+ //
+ InitializePchDevice (PchInstance, PchPlatformPolicy);
+ PchInstance = AllocateZeroPool (sizeof (PCH_INSTANCE_PRIVATE_DATA));
+ if (PchInstance == NULL) {
+ ASSERT (FALSE);
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ PchInstance->PchInfo.Revision = PCH_INFO_PROTOCOL_REVISION_1;
+ PchInstance->PchInfo.BusNumber = BusNumber;
+ PchInstance->PchInfo.RCVersion = PCH_RC_VERSION;
+ Status = gBS->InstallMultipleProtocolInterfaces (
+ &(HandleBuffer[Index]),
+ &gEfiPchInfoProtocolGuid,
+ &(PchInstance->PchInfo),
+ NULL
+ );
+ }
+
+ DEBUG ((EFI_D_INFO, "PchInitEntryPoint() End\n"));
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Initialize the PCH device according to the PCH Platform Policy protocol
+
+ @param[in] PchInstance PCH instance private data. May get updated by this function
+ @param[in] PchPlatformPolicy The PCH Platform Policy protocol instance
+ @param[in] RootComplexBar RootComplexBar value of this PCH device
+ @param[in] PmcBase PMC base address of this PCH device
+ @param[in] IlbBase iLB base address of this PCH device
+ @param[in] SpiBase SPI base address of this PCH device
+ @param[in] MphyBase MPHY base address of this PCH device
+ @param[in] AcpiBase ACPI IO base address of this PCH device
+ @param[in] IoBase CFIO base address of this PCH device
+
+ @retval EFI_SUCCESS The function completed successfully
+**/
+EFI_STATUS
+InitializePchDevice (
+#ifndef FSP_FLAG
+ IN OUT PCH_INSTANCE_PRIVATE_DATA *PchInstance,
+#else
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+#endif
+ IN DXE_PCH_PLATFORM_POLICY_PROTOCOL *PchPlatformPolicy
+ )
+{
+ EFI_STATUS Status;
+
+#ifndef FSP_FLAG
+ EFI_EVENT LegacyBootEvent;
+ EFI_EVENT ExitBootServicesEvent;
+#endif
+
+ //
+ // Create events for PCH to do the task before ExitBootServices/LegacyBoot.
+ // It is guaranteed that only one of two events below will be signalled
+ //
+ Status = gBS->CreateEventEx (
+ EVT_NOTIFY_SIGNAL,
+ TPL_NOTIFY,
+ (EFI_EVENT_NOTIFY) PchExitBootServicesEvent,
+ NULL,
+ &gEfiEventExitBootServicesGuid,
+ &ExitBootServicesEvent
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ Status = EfiCreateEventLegacyBootEx (
+ TPL_CALLBACK,
+ (EFI_EVENT_NOTIFY) PchExitBootServicesEvent,
+ NULL,
+ &LegacyBootEvent
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ if (PchPlatformPolicy->SccConfig->eMMCEnabled != PchDisabled) {
+ PchMsgBusAndThenOr32 (
+ 0x63,
+ 0x500,
+ (UINT32)(~BIT7),
+ 0x00000000,
+ 0x06,
+ 0x07
+ );
+ }
+
+ if (PchPlatformPolicy->SccConfig->SdioEnabled != PchDisabled) {
+ PchMsgBusAndThenOr32 (
+ 0x63,
+ 0x508,
+ (UINT32)(~BIT7),
+ 0x00000000,
+ 0x06,
+ 0x07
+ );
+ }
+
+ if (PchPlatformPolicy->SccConfig->SdcardEnabled != PchDisabled) {
+ PchMsgBusAndThenOr32 (
+ 0x63,
+ 0x504,
+ (UINT32)(~BIT7),
+ 0x00000000,
+ 0x06,
+ 0x07
+ );
+ }
+
+ DEBUG ((EFI_D_INFO, "InitializePchDevice() End\n"));
+
+ return Status;
+}
+
+/**
+ PCH initialization before ExitBootServices / LegacyBoot events
+ Useful for operations which must happen later than at EndOfPost event
+
+ @param[in] Event A pointer to the Event that triggered the callback.
+ @param[in] Context A pointer to private data registered with the callback function.
+
+**/
+EFI_STATUS
+EFIAPI
+PchExitBootServicesEvent (
+#ifndef FSP_FLAG
+ IN EFI_EVENT Event,
+ IN VOID *Context
+#else
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
+ IN VOID *Ppi
+#endif
+ )
+{
+ EFI_STATUS Status;
+ UINTN NumHandles;
+ DXE_PCH_PLATFORM_POLICY_PROTOCOL *PchPlatformPolicy;
+ UINTN Index;
+#ifndef FSP_FLAG
+ EFI_HANDLE *HandleBuffer;
+
+ //
+ // Closed the event to avoid call twice
+ //
+ gBS->CloseEvent (Event);
+
+ //
+ // Retrieve all instances of PCH Platform Policy protocol
+ //
+ Status = gBS->LocateHandleBuffer (
+ ByProtocol,
+ &gDxePchPlatformPolicyProtocolGuid,
+ NULL,
+ &NumHandles,
+ &HandleBuffer
+ );
+ if (EFI_ERROR (Status)) {
+ DEBUG ((EFI_D_ERROR | EFI_D_INFO, "Failed to locate handle buffer for PCH Policy protocol.\n"));
+ return Status;
+ }
+#else
+ NumHandles = 1;
+#endif
+
+ for (Index = 0; Index < NumHandles; Index++) {
+#ifndef FSP_FLAG
+ Status = gBS->HandleProtocol (
+ HandleBuffer[Index],
+ &gDxePchPlatformPolicyProtocolGuid,
+ (VOID **) &PchPlatformPolicy
+ );
+ ASSERT_EFI_ERROR (Status);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((EFI_D_ERROR | EFI_D_INFO, "Failed to find PCH Policy protocol.\n"));
+ return Status;
+ }
+#else
+ //
+ // PCH Policy
+ //
+ Status = (**PeiServices).LocatePpi (
+ PeiServices,
+ &gDxePchPlatformPolicyProtocolGuid,
+ 0,
+ NULL,
+ (VOID **) &PchPlatformPolicy
+ );
+ ASSERT_EFI_ERROR (Status);
+#endif
+
+ ConfigureLpeAtBoot (PchPlatformPolicy, FALSE);
+ ConfigureOtgAtBoot (PchPlatformPolicy, FALSE);
+ ConfigureLpssAtBoot (PchPlatformPolicy, FALSE);
+ ConfigureSccAtBoot (PchPlatformPolicy, FALSE);
+ }
+ return EFI_SUCCESS;
+}
+
diff --git a/ChvRefCodePkg/CherryViewSoc/SouthCluster/PchInit/Dxe/PchInit.h b/ChvRefCodePkg/CherryViewSoc/SouthCluster/PchInit/Dxe/PchInit.h new file mode 100644 index 0000000000..8de1a925a8 --- /dev/null +++ b/ChvRefCodePkg/CherryViewSoc/SouthCluster/PchInit/Dxe/PchInit.h @@ -0,0 +1,521 @@ +/** @file
+ Header file for PCH Initialization Driver.
+
+ Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _PCH_INITIALIZATION_DRIVER_H_
+#define _PCH_INITIALIZATION_DRIVER_H_
+
+#include <Library/S3BootScriptLib.h>
+#ifndef FSP_FLAG
+#include <Library/UefiLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/DxeServicesTableLib.h>
+#endif
+#include <Library/PcdLib.h>
+#include <Library/IoLib.h>
+#include <Library/DebugLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/BaseMemoryLib.h>
+
+#include <Guid/EventGroup.h>
+
+#ifdef FSP_FLAG
+#include <PiPei.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/PeiServicesTablePointerLib.h>
+#include <Uefi/UefiBaseType.h>
+extern EFI_GUID gDxePchPolicyUpdateProtocolGuid;
+#endif
+//
+// Driver Consumed Protocol Prototypes
+//
+#include <Protocol/GlobalNvsArea.h>
+#include <Protocol/PchPlatformPolicy.h>
+#include <Protocol/BootScriptSave.h>
+#include <Protocol/ExitPmAuth.h>
+#include <Protocol/PchInfo.h>
+#include <Protocol/PchSccTuning.h>
+
+#include "PchAccess.h"
+#include <Library/PchPlatformLib.h>
+#include <Library/AslUpdateLib.h>
+#include "PlatformBaseAddresses.h"
+#include "../Common/PchUsbCommon.h"
+#ifdef EFI_S3_RESUME
+#include "IosfSbDefinitions.h"
+#endif
+#include <Library/PchPciExpressHelpersLib.h>
+
+#define AZALIA_MAX_LOOP_TIME 10
+#define AZALIA_WAIT_PERIOD 100
+#define AZALIA_MAX_SID_NUMBER 4
+#define AZALIA_MAX_SID_MASK ((1 << AZALIA_MAX_SID_NUMBER) - 1)
+
+typedef struct {
+ EFI_PCH_INFO_PROTOCOL PchInfo;
+} PCH_INSTANCE_PRIVATE_DATA;
+
+///
+/// Data definitions
+///
+extern EFI_HANDLE mImageHandle;
+
+///
+/// SVID / SID init table entry
+///
+typedef struct {
+ UINT8 DeviceNumber;
+ UINT8 FunctionNumber;
+ UINT8 SvidRegOffset;
+} PCH_SVID_SID_INIT_ENTRY;
+
+///
+/// Function Prototype
+///
+
+/**
+ Configures extended IOSF-SB and stores this configuration in S3 boot script
+
+ @param[in] PortId Port ID of the target IOSF-SB block
+ @param[in] Register Register of the target IOSF-SB block
+ @param[in] AndData Value to be ANDed
+ @param[in] OrData Value to be ORed
+ @param[in] ReadOpCode Read Op Code
+ @param[in] WriteOpCode Write Op Code
+ @param[in] Bar BAR
+ @param[in] Device Device Number
+ @param[in] Function Function Number
+
+**/
+VOID
+PchMsgBusAndThenOrEx32WithScript (
+ IN UINT8 PortId,
+ IN UINT32 Register,
+ IN UINT32 AndData,
+ IN UINT32 OrData,
+ IN UINT8 ReadOpCode,
+ IN UINT8 WriteOpCode,
+ IN UINT8 Bar,
+ IN UINT8 Device,
+ IN UINT8 Function
+ );
+
+/**
+ Configures IOSF-SB and stores this configuration in S3 boot script
+
+ @param[in] PortId Port ID of the target IOSF-SB block
+ @param[in] Register Register of the target IOSF-SB block
+ @param[in] AndData Value to be ANDed
+ @param[in] OrData Value to be ORed
+ @param[in] ReadOpCode Read Op Code
+ @param[in] WriteOpCode Write Op Code
+
+**/
+VOID
+PchMsgBusAndThenOr32WithScript (
+ IN UINT8 PortId,
+ IN UINT32 Register,
+ IN UINT32 AndData,
+ IN UINT32 OrData,
+ IN UINT8 ReadOpCode,
+ IN UINT8 WriteOpCode
+ );
+
+/**
+ Detect and initialize the type of codec (AC'97 and HDA) present in the system.
+
+ @param[in] PchPlatformPolicy The PCH Platform Policy protocol instance
+ @param[in] RootComplexBar RootComplexBar value of this PCH device
+ @param[in] AzaliaEnable Returned with TRUE if Azalia High Definition Audio codec
+ is detected and initialized.
+
+ @retval EFI_SUCCESS Codec is detected and initialized.
+ @retval EFI_OUT_OF_RESOURCES Failed to allocate resources to initialize the codec.
+**/
+EFI_STATUS
+ConfigureAzalia (
+ IN DXE_PCH_PLATFORM_POLICY_PROTOCOL *PchPlatformPolicy,
+ IN UINT32 RootComplexBar,
+ IN OUT BOOLEAN *AzaliaEnable
+ );
+/**
+ Configure miscellaneous power management settings
+
+ @param[in] PchPlatformPolicy The PCH Platform Policy protocol instance
+ @param[in] AcpiBase The ACPI I/O Base address of the PCH
+ @param[in] PmcBase PMC base address of this PCH device
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_TIMEOUT Timeout while polling a bit in a register
+**/
+EFI_STATUS
+ConfigureMiscPm (
+ IN DXE_PCH_PLATFORM_POLICY_PROTOCOL *PchPlatformPolicy,
+ IN UINT16 AcpiBase,
+ IN UINT32 PmcBase
+ );
+
+/**
+ Configure additional power management settings
+
+ @param[in] PchPlatformPolicy The PCH Platform Policy protocol instance
+ @param[in] RootComplexBar RootComplexBar value of this PCH device
+
+ @retval EFI_SUCCESS The function completed successfully
+**/
+EFI_STATUS
+ConfigureAdditionalPm (
+ IN DXE_PCH_PLATFORM_POLICY_PROTOCOL *PchPlatformPolicy
+ );
+
+/**
+ Configure S0ix Settings
+
+ @param[in] PchPlatformPolicy The PCH Platform Policy protocol instance
+ @param[in] PmcBase PmcBase value of this PCH device
+ @param[in] IlbBase IlbBase value of this PCH device
+
+ @retval EFI_SUCCESS The function completed successfully
+**/
+EFI_STATUS
+ConfigureS0ix (
+ IN DXE_PCH_PLATFORM_POLICY_PROTOCOL *PchPlatformPolicy,
+ IN UINT32 PmcBase,
+ IN UINT32 IlbBase
+ );
+
+/**
+ Configure for platforms with ACPI Hardware Reduced Mode enabled
+
+ @param[in] AcpiBase The ACPI I/O Base address of the PCH
+ @param[in] PmcBase PmcBase value of this PCH device
+ @param[in] IlbBase IlbBase value of this PCH device
+
+ @retval EFI_SUCCESS The function completed successfully
+**/
+EFI_STATUS
+ConfigureAcpiHwRed (
+ IN UINT16 AcpiBase,
+ IN UINT32 PmcBase,
+ IN UINT32 IlbBase
+ );
+
+/**
+ Perform miscellany PCH initialization
+
+ @param[in] PchPlatformPolicy The PCH Platform Policy protocol instance
+ @param[in] RootComplexBar RootComplexBar value of this PCH device
+ @param[in] PmcBase PmcBase value of this PCH device
+ @param[in] IlbBase IlbBase value of this PCH device
+ @param[in,out] FuncDisableReg The value of Function disable register
+
+ @retval EFI_SUCCESS The function completed successfully
+**/
+EFI_STATUS
+ConfigureMiscItems (
+ IN DXE_PCH_PLATFORM_POLICY_PROTOCOL *PchPlatformPolicy,
+ IN UINT32 RootComplexBar,
+ IN UINT32 PmcBase,
+ IN UINT32 IlbBase,
+ IN OUT UINT32 *FuncDisableReg
+ );
+
+/**
+ Hide PCI config space of OTG device and do any final initialization.
+
+ @param[in] PchPlatformPolicy The PCH Platform Policy protocol instance
+ @param[in] IsSetS3BootScript Is this function called for S3 boot script save
+
+ @retval EFI_SUCCESS The function completed successfully
+**/
+EFI_STATUS
+ConfigureOtgAtBoot (
+ IN DXE_PCH_PLATFORM_POLICY_PROTOCOL *PchPlatformPolicy,
+ IN BOOLEAN IsSetS3BootScript
+ );
+
+/**
+ Configure OTG devices.
+
+ @param[in] PchPlatformPolicy The PCH Platform Policy protocol instance
+ @param[in,out] FuncDisableReg The value of Function disable register
+ @param[in,out] FuncDisabl2eReg The value of Function disable 2 register
+
+ @retval EFI_SUCCESS The function completed successfully
+**/
+EFI_STATUS
+ConfigureOtg (
+ IN DXE_PCH_PLATFORM_POLICY_PROTOCOL *PchPlatformPolicy,
+ IN OUT UINT32 *FuncDisableReg,
+ IN OUT UINT32 *FuncDisable2Reg
+ );
+
+/**
+ Hide PCI config space of LPE device and do any final initialization.
+
+ @param[in] PchPlatformPolicy The PCH Platform Policy protocol instance
+ @param[in] IsSetS3BootScript Is this function called for S3 boot script save
+
+ @retval EFI_SUCCESS The function completed successfully
+**/
+EFI_STATUS
+ConfigureLpeAtBoot (
+ IN DXE_PCH_PLATFORM_POLICY_PROTOCOL *PchPlatformPolicy,
+ IN BOOLEAN IsSetS3BootScript
+ );
+
+/**
+ Configure LPE devices.
+
+ @param[in] PchPlatformPolicy The PCH Platform Policy protocol instance
+ @param[in,out] FuncDisableReg The value of Function disable register
+
+ @retval EFI_SUCCESS The function completed successfully
+**/
+EFI_STATUS
+ConfigureLpe (
+ IN DXE_PCH_PLATFORM_POLICY_PROTOCOL *PchPlatformPolicy,
+ IN OUT UINT32 *FuncDisableReg
+ );
+
+/**
+ Hide PCI config space of LPSS device and do any final initialization.
+
+ @param[in] PchPlatformPolicy The PCH Platform Policy protocol instance
+ @param[in] IsSetS3BootScript Is this function called for S3 boot script save
+
+ @retval EFI_SUCCESS The function completed successfully
+**/
+EFI_STATUS
+ConfigureLpssAtBoot (
+ IN DXE_PCH_PLATFORM_POLICY_PROTOCOL *PchPlatformPolicy,
+ IN BOOLEAN IsSetS3BootScript
+ );
+
+/**
+ Configure LPSS devices.
+
+ @param[in] PchPlatformPolicy The PCH Platform Policy protocol instance
+ @param[in,out] FuncDisableReg The value of Function disable register
+
+ @retval EFI_SUCCESS The function completed successfully
+**/
+EFI_STATUS
+ConfigureLpss (
+ IN DXE_PCH_PLATFORM_POLICY_PROTOCOL *PchPlatformPolicy,
+ IN OUT UINT32 *FuncDisableReg
+ );
+
+/**
+ Hide PCI config space of SCC devices and do any final initialization.
+
+ @param[in] PchPlatformPolicy The PCH Platform Policy protocol instance
+ @param[in] IsSetS3BootScript Is this function called for S3 boot script save
+
+ @retval EFI_SUCCESS The function completed successfully
+**/
+EFI_STATUS
+ConfigureSccAtBoot (
+ IN DXE_PCH_PLATFORM_POLICY_PROTOCOL *PchPlatformPolicy,
+ IN BOOLEAN IsSetS3BootScript
+ );
+
+/**
+ Configure SCC devices.
+
+ @param[in] PchPlatformPolicy The PCH Platform Policy protocol instance
+ @param[in,out] FuncDisableReg The value of Function disable register
+ @param[in] IoBase IO base address of this PCH device
+
+ @retval EFI_SUCCESS The function completed successfully
+**/
+EFI_STATUS
+ConfigureScc (
+ IN DXE_PCH_PLATFORM_POLICY_PROTOCOL *PchPlatformPolicy,
+ IN OUT UINT32 *FuncDisableReg,
+ IN UINT32 IoBase
+ );
+
+/**
+ Configure eMMC Tuning Mode
+
+ @param[in] This A pointer to PCH_EMMC_TUNING_PROTOCOL structure
+ @param[in] Revision Revision parameter used to verify the layout of EMMC_INFO and TUNINGDATA.
+ @param[in] EmmcInfo A pointer to EMMC_INFO structure
+ @param[out] EmmcTuningData A pointer to EMMC_TUNING_DATA structure
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_NOT_FOUND The item was not found
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
+ @retval EFI_INVALID_PARAMETER A parameter was incorrect.
+ @retval EFI_DEVICE_ERROR Hardware Error
+ @retval EFI_NO_MEDIA No media
+ @retval EFI_MEDIA_CHANGED Media Change
+ @retval EFI_BAD_BUFFER_SIZE Buffer size is bad
+ @retval EFI_CRC_ERROR Command or Data CRC Error
+**/
+EFI_STATUS
+EFIAPI
+ConfigureEmmcTuningMode (
+ IN PCH_EMMC_TUNING_PROTOCOL *This,
+ IN UINT8 Revision,
+ IN EMMC_INFO *EmmcInfo,
+ OUT EMMC_TUNING_DATA *EmmcTuningData
+ );
+
+/**
+ Install PCH SCC Tuning Protocol
+
+ @param[in] PchPlatformPolicy A pointer to DXE_PCH_PLATFORM_POLICY_PROTOCOL
+
+**/
+VOID
+InstallPchSccTuningProtocol (
+ IN DXE_PCH_PLATFORM_POLICY_PROTOCOL *PchPlatformPolicy
+ );
+
+/**
+ Hide PCI config space of ISH device and do any final initialization.
+
+ @param[in] PchPlatformPolicy The PCH Platform Policy protocol instance
+ @param[in] IsSetS3BootScript Is this function called for S3 boot script save
+
+ @retval EFI_SUCCESS The function completed successfully
+**/
+
+/**
+ Configure ISH device.
+
+ @param[in] PchPlatformPolicy The PCH Platform Policy protocol instance
+ @param[in,out] FuncDisable2Reg The value of Function disable 2 register
+
+ @retval EFI_SUCCESS The function completed successfully
+**/
+EFI_STATUS
+ConfigureIsh (
+ IN DXE_PCH_PLATFORM_POLICY_PROTOCOL *PchPlatformPolicy,
+ IN OUT UINT32 *FuncDisable2Reg
+ );
+
+/**
+ Configures PCH USB controller
+
+ @param[in] PchPlatformPolicy The PCH Platform Policy protocol instance
+ @param[in,out] FuncDisableReg Function Disable Register
+ @param[in,out] FuncDisable2Reg Function Disable 2 Register
+
+ @retval EFI_INVALID_PARAMETER The parameter of PchPlatformPolicy is invalid
+ @retval EFI_SUCCESS The function completed successfully
+**/
+EFI_STATUS
+ConfigureUsb (
+ IN DXE_PCH_PLATFORM_POLICY_PROTOCOL *PchPlatformPolicy,
+ IN OUT UINT32 *FuncDisableReg,
+ IN OUT UINT32 *FuncDisable2Reg
+ );
+#ifdef SATA_SUPPORT
+
+/**
+ Configures PCH Sata Controller
+
+ @param[in] PchPlatformPolicy The PCH Platform Policy protocol instance
+ @param[in] RootComplexBar RootComplexBar value of this PCH device
+ @param[in,out] FuncDisableReg Function Disable Register
+ @param[in] IoBase IO base address of this PCH device
+
+ @retval EFI_SUCCESS The function completed successfully
+**/
+EFI_STATUS
+ConfigureSata (
+ IN DXE_PCH_PLATFORM_POLICY_PROTOCOL *PchPlatformPolicy,
+ IN UINT32 RootComplexBar,
+ IN OUT UINT32 *FuncDisableReg,
+ IN UINT32 IoBase
+ );
+
+/**
+ Do any final initialization on SATA controller
+
+ @param[in] PchPlatformPolicy The PCH Platform Policy protocol instance
+ @param[in] IsSetS3BootScript Is this function called for S3 boot script save
+
+ @retval EFI_SUCCESS The function completed successfully
+**/
+EFI_STATUS
+ConfigureSataAtBoot (
+ IN DXE_PCH_PLATFORM_POLICY_PROTOCOL *PchPlatformPolicy,
+ IN BOOLEAN IsSetS3BootScript
+ );
+#endif
+/**
+ Perform Clock Gating programming
+ Enables clock gating in various PCH interfaces and the registers must be restored during S3 resume.
+
+ @param[in] PchPlatformPolicy The PCH Platform Policy protocol instance
+ @param[in] RootComplexBar RootComplexBar value of this PCH device
+ @param[in] PmcBase PmcBase value of this PCH device
+ @param[in] SpiBase SpiBase value of this PCH device
+ @param[in] FuncDisableReg The Function Disable Register
+
+ @retval EFI_SUCCESS The function completed successfully
+**/
+EFI_STATUS
+ConfigureClockGating (
+ IN DXE_PCH_PLATFORM_POLICY_PROTOCOL *PchPlatformPolicy,
+ IN UINT32 RootComplexBar,
+ IN UINT32 PmcBase,
+ IN UINT32 SpiBase,
+ IN UINT32 FuncDisableReg
+ );
+
+/**
+ Configure IoApic Controller
+
+ @param[in] PchPlatformPolicy The PCH Platform Policy protocol instance
+ @param[in] RootComplexBar RootComplexBar address of this PCH device
+
+ @retval EFI_SUCCESS The function completed successfully
+**/
+EFI_STATUS
+ConfigureIoApic (
+ IN DXE_PCH_PLATFORM_POLICY_PROTOCOL *PchPlatformPolicy,
+ IN UINT32 IlbBase
+ );
+
+/**
+ Enforce S0ix for PCIe Ports.
+
+ @param[in] PchPlatformPolicy The PCH Platform Policy protocol
+ @param[in] PmcBase PmcBase of the PCH
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER The PCIe Root Port Number of D28:F0 is not found
+ or invalid
+**/
+EFI_STATUS
+PchPciEnforceS0ix (
+ IN DXE_PCH_PLATFORM_POLICY_PROTOCOL *PchPlatformPolicy,
+ IN UINT32 PmcBase
+ );
+/**
+ Dump whole DXE_PCH_PLATFORM_POLICY_PROTOCOL and serial out.
+
+ @param[in] PchPlatformPolicy The PCH Platform Policy protocol instance
+
+**/
+VOID
+PchDumpPlatformProtocol (
+ IN DXE_PCH_PLATFORM_POLICY_PROTOCOL *PchPlatformPolicy
+ );
+#endif
diff --git a/ChvRefCodePkg/CherryViewSoc/SouthCluster/PchInit/Dxe/PchInitCommon.h b/ChvRefCodePkg/CherryViewSoc/SouthCluster/PchInit/Dxe/PchInitCommon.h new file mode 100644 index 0000000000..ee0d931a99 --- /dev/null +++ b/ChvRefCodePkg/CherryViewSoc/SouthCluster/PchInit/Dxe/PchInitCommon.h @@ -0,0 +1,102 @@ +/** @file
+ Header file for PCH common Initialization Driver.
+
+ Copyright (c) 2011 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _PCH_INIT_COMMON_DRIVER_H_
+#define _PCH_INIT_COMMON_DRIVER_H_
+
+#include <Protocol/PchPlatformPolicy.h>
+#include <Library/S3BootScriptLib.h>
+
+#define PCH_INIT_COMMON_SCRIPT_IO_WRITE(TableName, Width, Address, Count, Buffer) \
+ S3BootScriptSaveIoWrite (Width, Address, Count, Buffer)
+
+#define PCH_INIT_COMMON_SCRIPT_IO_READ_WRITE(TableName, Width, Address, Data, DataMask) \
+ S3BootScriptSaveIoReadWrite (Width, Address, Data, DataMask)
+
+#define PCH_INIT_COMMON_SCRIPT_MEM_WRITE(TableName, Width, Address, Count, Buffer) \
+ S3BootScriptSaveMemWrite (Width, Address, Count, Buffer)
+
+#define PCH_INIT_COMMON_SCRIPT_MEM_READ_WRITE(TableName, Width, Address, Data, DataMask) \
+ S3BootScriptSaveMemReadWrite (Width, Address, Data, DataMask)
+
+#define PCH_INIT_COMMON_SCRIPT_PCI_CFG_WRITE(TableName, Width, Address, Count, Buffer) \
+ S3BootScriptSavePciCfgWrite (Width, Address, Count, Buffer)
+
+#define PCH_INIT_COMMON_SCRIPT_PCI_CFG_READ_WRITE(TableName, Width, Address, Data, DataMask) \
+ S3BootScriptSavePciCfgReadWrite (Width, Address, Data, DataMask)
+
+#define PCH_INIT_COMMON_SCRIPT_STALL(Duration) \
+ S3BootScriptSaveStall (Duration)
+
+#define PCH_INIT_COMMON_SCRIPT_MEM_POLL(Width, Address, BitMask, BitValue, Duration, LoopTimes) \
+ S3BootScriptSaveMemPoll (Width, Address, BitMask, BitValue, Duration, LoopTimes)
+
+#define PCH_INIT_COMMON_SCRIPT_MSG_BUS_AND_THEN_OR_32_S3_ITEM(PortId, Register, AndData, OrData, ReadOpCode, WriteOpCode) \
+ SetMsgBusAndThenOr32S3Item(PortId, Register, AndData, OrData, ReadOpCode, WriteOpCode)
+
+#define PCH_INIT_COMMON_SCRIPT_MSG_BUS_AND_THEN_OR_EX_32_S3_ITEM(PortId, Register, AndData, OrData, ReadOpCode, WriteOpCode, Bar, Device, Function) \
+ SetMsgBusAndThenOrEx32S3Item(PortId, Register, AndData, OrData, ReadOpCode, WriteOpCode, Bar, Device, Function)
+
+/**
+ Set an IOSF-SB extended programming S3 dispatch item, this function may assert if any error happened
+
+ @param[in] PortId Port ID of the target IOSF-SB block
+ @param[in] Register Register of the target IOSF-SB block
+ @param[in] AndData Value to be ANDed
+ @param[in] OrData Value to be ORed
+ @param[in] ReadOpCode Read Op Code
+ @param[in] WriteOpCode Write Op Code
+ @param[in] Bar BAR
+ @param[in] Device Device Number
+ @param[in] Function Function Number
+
+ @retval EFI_SUCCESS The function completed successfully
+**/
+EFI_STATUS
+SetMsgBusAndThenOrEx32S3Item (
+ IN UINT8 PortId,
+ IN UINT32 Register,
+ IN UINT32 AndData,
+ IN UINT32 OrData,
+ IN UINT8 ReadOpCode,
+ IN UINT8 WriteOpCode,
+ IN UINT8 Bar,
+ IN UINT8 Device,
+ IN UINT8 Function
+ );
+
+/**
+ Set an IOSF-SB programming S3 dispatch item, this function may assert if any error happened
+
+ @param[in] PortId Port ID of the target IOSF-SB block
+ @param[in] Register Register of the target IOSF-SB block
+ @param[in] AndData Value to be ANDed
+ @param[in] OrData Value to be ORed
+ @param[in] ReadOpCode Read Op Code
+ @param[in] WriteOpCode Write Op Code
+
+ @retval EFI_SUCCESS The function completed successfully
+**/
+EFI_STATUS
+SetMsgBusAndThenOr32S3Item (
+ IN UINT8 PortId,
+ IN UINT32 Register,
+ IN UINT32 AndData,
+ IN UINT32 OrData,
+ IN UINT8 ReadOpCode,
+ IN UINT8 WriteOpCode
+ );
+
+#endif
diff --git a/ChvRefCodePkg/CherryViewSoc/SouthCluster/PchInit/Dxe/PchInitDxe.inf b/ChvRefCodePkg/CherryViewSoc/SouthCluster/PchInit/Dxe/PchInitDxe.inf new file mode 100644 index 0000000000..506723cef1 --- /dev/null +++ b/ChvRefCodePkg/CherryViewSoc/SouthCluster/PchInit/Dxe/PchInitDxe.inf @@ -0,0 +1,83 @@ +## @file
+# Initializes PCH hardware.
+#
+# This module configures and initializes the PCH devices by
+# the platform policy.
+#
+# Copyright (c) 2012 - 2015, Intel Corporation. All rights reserved.<BR>
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php.
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = PchInitDxe
+ FILE_GUID = 48D30263-7D25-4AD9-855D-61FB87F2C257
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ ENTRY_POINT = PchInitEntryPoint
+
+[Sources]
+ PchInit.h
+ PchInit.c
+ PchIsh.c
+ PchLpe.c
+ PchLpss.c
+ PchSata.c
+ PchScc.c
+ PchDebugDump.c
+ PchUsbOtg.c
+ ../Common/PchUsbCommon.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ ChvRefCodePkg/ChvRefCodePkg.dec
+
+[LibraryClasses]
+ UefiBootServicesTableLib
+ DxeServicesTableLib
+ MemoryAllocationLib
+ UefiDriverEntryPoint
+ DebugLib
+ PcdLib
+ IoLib
+ PchPlatformLib
+ UefiLib
+ S3BootScriptLib
+ AslUpdateLib
+ TimerLib
+
+[Protocols]
+ ## CONSUMES
+ gDxePchPlatformPolicyProtocolGuid
+
+ ## PRODUCES
+ gEfiPchInfoProtocolGuid
+
+ ## SOMETIMES_CONSUMES
+ gEfiAcpiTableProtocolGuid
+
+ ## SOMETIMES_CONSUMES
+ gEfiGlobalNvsAreaProtocolGuid
+
+[Guids]
+ ## CONSUMES ## Event
+ gEfiEventExitBootServicesGuid
+
+[Pcd]
+ ## SOMETIMES_CONSUMES
+ gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
+
+[Depex]
+ gDxePchPlatformPolicyProtocolGuid AND
+ gEfiPciHostBridgeResourceAllocationProtocolGuid AND ## This is to ensure that PCI MMIO and IO resource has been prepared and available for this driver to allocate.
+ gEfiSmmControl2ProtocolGuid AND
+ gEndOfSaInitDxeProtocolGuid
+
diff --git a/ChvRefCodePkg/CherryViewSoc/SouthCluster/PchInit/Dxe/PchIsh.c b/ChvRefCodePkg/CherryViewSoc/SouthCluster/PchInit/Dxe/PchIsh.c new file mode 100644 index 0000000000..2dd1d2784f --- /dev/null +++ b/ChvRefCodePkg/CherryViewSoc/SouthCluster/PchInit/Dxe/PchIsh.c @@ -0,0 +1,17 @@ +/** @file
+ Initializes PCH Integrated Sensor Hub.
+
+ Copyright (c) 2012 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "PchInit.h"
+
diff --git a/ChvRefCodePkg/CherryViewSoc/SouthCluster/PchInit/Dxe/PchLpe.c b/ChvRefCodePkg/CherryViewSoc/SouthCluster/PchInit/Dxe/PchLpe.c new file mode 100644 index 0000000000..c4aba9dcf8 --- /dev/null +++ b/ChvRefCodePkg/CherryViewSoc/SouthCluster/PchInit/Dxe/PchLpe.c @@ -0,0 +1,156 @@ +/** @file
+ Initializes PCH Low Power Audio Engine Device.
+
+ @Copyright (c) 2012 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "PchInit.h"
+
+UINT32 gIndex = 0;
+
+typedef struct {
+ EFI_PHYSICAL_ADDRESS LpeBar2Base;
+ UINT32 LpeBar2Length;
+ } LPE_MEM_LIST;
+
+LPE_MEM_LIST gLpeList[] = {
+ {0x20000000, 0x00200000}, // 512M
+ {0x40000000, 0x00200000}, // 1G
+ {0x60000000, 0x00200000}, // 1.5G
+ {0x00000000, 0x00000000} // END
+};
+
+/**
+ Hide PCI config space of LPE device and do any final initialization.
+
+ @param[in] PchPlatformPolicy The PCH Platform Policy protocol instance
+ @param[in] IsSetS3BootScript Is this function called for S3 boot script save
+
+ @retval EFI_SUCCESS The function completed successfully
+**/
+EFI_STATUS
+ConfigureLpeAtBoot (
+ IN DXE_PCH_PLATFORM_POLICY_PROTOCOL *PchPlatformPolicy,
+ IN BOOLEAN IsSetS3BootScript
+ )
+{
+ UINTN LpePciMmBase;
+ UINT32 LpeMmioBase0;
+ UINT32 LpeMmioBase1;
+ UINT32 Data32And;
+ UINT32 Data32Or;
+ EFI_STATUS Status;
+#ifndef FSP_FLAG
+ EFI_GLOBAL_NVS_AREA_PROTOCOL *GlobalNvsArea;
+#endif
+ DEBUG ((EFI_D_INFO, "ConfigureLpeAtBoot() Start\n"));
+ //
+ // Initialize Variables
+ //
+ LpePciMmBase = 0;
+ LpeMmioBase0 = 0;
+ LpeMmioBase1 = 0;
+ Data32And = 0;
+ Data32Or = 0;
+ Status = EFI_SUCCESS;
+ //
+ // Update LPE device ACPI variables
+ //
+ if (PchPlatformPolicy->DeviceEnabling->LpeEnabled == PchAcpiMode) {
+#ifndef FSP_FLAG
+ //
+ // Locate GlobalNVS protocol
+ //
+ Status = gBS->LocateProtocol (
+ &gEfiGlobalNvsAreaProtocolGuid,
+ NULL,
+ (VOID **) &GlobalNvsArea
+ );
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+#endif
+
+ LpePciMmBase = MmPciAddress (
+ 0,
+ DEFAULT_PCI_BUS_NUMBER_PCH,
+ PCI_DEVICE_NUMBER_PCH_LPE,
+ PCI_FUNCTION_NUMBER_PCH_LPE,
+ 0
+ );
+ LpeMmioBase0 = MmioRead32 ((UINTN) (LpePciMmBase + R_PCH_LPE_BAR0)) & B_PCH_LPE_BAR0_BA;
+ ASSERT ((LpeMmioBase0 != 0) && (LpeMmioBase0 != B_PCH_LPE_BAR0_BA));
+ LpeMmioBase1 = MmioRead32 ((UINTN) (LpePciMmBase + R_PCH_LPE_BAR1)) & B_PCH_LPE_BAR1_BA;
+ ASSERT ((LpeMmioBase1 != 0) && (LpeMmioBase1 != B_PCH_LPE_BAR1_BA));
+ if (!IsSetS3BootScript) {
+
+ MmioOr32 (
+ (UINTN) (LpePciMmBase + R_PCH_LPE_STSCMD),
+ (UINT32) (B_PCH_LPE_STSCMD_INTR_DIS | B_PCH_LPE_STSCMD_BME | B_PCH_LPE_STSCMD_MSE)
+ );
+#ifndef FSP_FLAG
+ //
+ // Update BAR and length in ACPI table.
+ //
+ GlobalNvsArea->Area->LPEBar0 = LpeMmioBase0;
+ GlobalNvsArea->Area->LPEBar1 = LpeMmioBase1;
+ GlobalNvsArea->Area->LPEBar2 = (UINT32) gLpeList[gIndex].LpeBar2Base;
+#endif
+ DEBUG ((EFI_D_INFO, "Memory space allocated for LPE Audio is 0x%08llX with size 0x%X\n", gLpeList[gIndex].LpeBar2Base, gLpeList[gIndex].LpeBar2Length));
+
+ PchMsgBusAndThenOr32 (
+ 0x58,
+ 0x500,
+ 0xFFFFFFFF,
+ (BIT1 | BIT0),
+ 0x06,
+ 0x07
+ );
+ } else {
+ //
+ // Set S3 Boot Script
+ //
+ S3BootScriptSaveMemWrite (
+ S3BootScriptWidthUint32,
+ (UINTN) (LpePciMmBase + R_PCH_LPE_BAR0),
+ 1,
+ &LpeMmioBase0
+ );
+ S3BootScriptSaveMemWrite (
+ S3BootScriptWidthUint32,
+ (UINTN) (LpePciMmBase + R_PCH_LPE_BAR1),
+ 1,
+ &LpeMmioBase1
+ );
+ Data32Or = (UINT32) (B_PCH_LPE_STSCMD_INTR_DIS | B_PCH_LPE_STSCMD_BME | B_PCH_LPE_STSCMD_MSE);
+ Data32And = 0xFFFFFFFF;
+ S3BootScriptSaveMemReadWrite (
+ EfiBootScriptWidthUint32,
+ (UINTN) (LpePciMmBase + R_PCH_LPE_STSCMD),
+ &Data32Or, // OR mask
+ &Data32And // AND mask
+ );
+ SetMsgBusAndThenOr32S3Item (
+ 0x58,
+ 0x500,
+ 0xFFFFFFFF,
+ (BIT1 | BIT0),
+ 0x06,
+ 0x07
+ );
+ }
+ }
+
+ DEBUG ((EFI_D_INFO, "ConfigureLpeAtBoot() End\n"));
+
+ return EFI_SUCCESS;
+}
diff --git a/ChvRefCodePkg/CherryViewSoc/SouthCluster/PchInit/Dxe/PchLpss.c b/ChvRefCodePkg/CherryViewSoc/SouthCluster/PchInit/Dxe/PchLpss.c new file mode 100644 index 0000000000..36d81bdf1d --- /dev/null +++ b/ChvRefCodePkg/CherryViewSoc/SouthCluster/PchInit/Dxe/PchLpss.c @@ -0,0 +1,1561 @@ +/** @file
+ Initializes PCH LPSS Devices.
+
+ Copyright (c) 2012 - 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "PchInit.h"
+#include <IndustryStandard/Acpi.h>
+
+//
+// CSRT Definitions
+//
+#define EFI_ACPI_CSRT_TABLE_REVISION 0x00
+#define MAX_NO_CHANNEL1_SUPPORTED 7
+#define MAX_NO_CHANNEL2_SUPPORTED 9
+#define EFI_ACPI_OEM_ID "INTEL " // OEMID 6 bytes long
+#define EFI_ACPI_OEM_TABLE_ID SIGNATURE_64('E','D','K','2',' ',' ',' ',' ') // OEM table id 8 bytes long
+#define EFI_ACPI_OEM_REVISION 0x00000005
+#define EFI_ACPI_CREATOR_ID SIGNATURE_32('I','N','T','L')
+#define EFI_ACPI_CREATOR_REVISION 0x20120624
+//
+// Ensure proper structure formats for CSRT
+//
+#pragma pack (1)
+//
+// Resource Share Info
+//
+typedef struct _SHARED_INFO_SECTION {
+ UINT16 MajVersion;
+ UINT16 MinVersion;
+ UINT32 MMIOLowPart;
+ UINT32 MMIOHighPart;
+ UINT32 IntGSI;
+ UINT8 IntPol;
+ UINT8 IntMode;
+ UINT8 NoOfCh;
+ UINT8 DMAAddressWidth;
+ UINT16 BaseReqLine;
+ UINT16 NoOfHandSig;
+ UINT32 MaxBlockTransferSize;
+ } SHARED_INFO_SECTION;
+//
+// Resource Group Header
+//
+typedef struct _RESOURCE_GROUP_HEADER {
+ UINT32 Length;
+ UINT32 VendorId;
+ UINT32 SubVendorId;
+ UINT16 DeviceId;
+ UINT16 SubDeviceId;
+ UINT16 Revision;
+ UINT16 Reserved;
+ UINT32 SharedInfoLength;
+ SHARED_INFO_SECTION SharedInfoSection;
+} RESOURCE_GROUP_HEADER;
+//
+// Resource Descriptor Header
+//
+typedef struct _RESOURCE_DESCRIPTOR {
+ UINT32 Length;
+ UINT16 ResourceType;
+ UINT16 ResourceSubType;
+ UINT32 UUID;
+ } RESOURCE_DESCRIPTOR;
+
+typedef struct {
+ RESOURCE_GROUP_HEADER ResourceGroupHeaderInfo;
+ RESOURCE_DESCRIPTOR ResourceDescriptorInfo[MAX_NO_CHANNEL1_SUPPORTED];
+ } RESOURCE_GROUP_INFO1;
+
+typedef struct {
+ RESOURCE_GROUP_HEADER ResourceGroupHeaderInfo;
+ RESOURCE_DESCRIPTOR ResourceDescriptorInfo[MAX_NO_CHANNEL2_SUPPORTED];
+ } RESOURCE_GROUP_INFO2;
+//
+// Core System Resources Table Structure (CSRT)
+//
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ RESOURCE_GROUP_INFO1 ResourceGroupsInfo1;
+ RESOURCE_GROUP_INFO2 ResourceGroupsInfo2;
+} EFI_ACPI_CSRT_TABLE;
+#pragma pack ()
+
+/**
+ Hide PCI config space of LPSS devices and do any final initialization.
+
+ @param[in] PchPlatformPolicy The PCH Platform Policy protocol instance
+ @param[in] IsSetS3BootScript Is this function called for S3 boot script save
+
+ @retval EFI_SUCCESS The function completed successfully
+**/
+EFI_STATUS
+ConfigureLpssAtBoot (
+ IN DXE_PCH_PLATFORM_POLICY_PROTOCOL *PchPlatformPolicy,
+ IN BOOLEAN IsSetS3BootScript
+ )
+{
+ UINTN LpssPciMmBase;
+ UINT32 LpssMmioBase0;
+ UINT32 LpssMmioBase1;
+ UINT32 Data32And;
+ UINT32 Data32Or;
+#ifndef FSP_FLAG
+ EFI_STATUS AcpiTablePresent;
+ EFI_STATUS Status;
+ UINTN AcpiTableKey;
+ UINT8 Index;
+ EFI_ACPI_CSRT_TABLE *mCsrt;
+ EFI_ACPI_TABLE_PROTOCOL *AcpiTable;
+ EFI_GLOBAL_NVS_AREA_PROTOCOL *GlobalNvsArea;
+#endif
+ DEBUG ((EFI_D_INFO, "ConfigureLpssAtBoot() Start\n"));
+
+ //
+ // Initialize Variables
+ //
+ LpssPciMmBase = 0;
+ LpssMmioBase0 = 0;
+ LpssMmioBase1 = 0;
+ Data32And = 0;
+ Data32Or = 0;
+#ifndef FSP_FLAG
+ AcpiTablePresent = EFI_NOT_FOUND;
+ AcpiTableKey = 0;
+ Index = 0;
+ Status = EFI_SUCCESS;
+ AcpiTable = NULL;
+ mCsrt = NULL;
+#endif
+
+#ifndef FSP_FLAG
+ //
+ // Locate ACPI table
+ //
+ if (!IsSetS3BootScript) {
+ AcpiTablePresent = InitializeAslUpdateLib ();
+ if (!EFI_ERROR (AcpiTablePresent)) {
+ if (PchPlatformPolicy->LpssConfig->Dma0Enabled != PchDisabled &&
+ PchPlatformPolicy->LpssConfig->Dma1Enabled != PchDisabled) {
+ //
+ // Locate ACPI support protocol
+ //
+ DEBUG ((EFI_D_INFO, "Initialize CSRT Start\n"));
+ Status = gBS->LocateProtocol (&gEfiAcpiTableProtocolGuid, NULL, (VOID **) &AcpiTable);
+ if (EFI_ERROR (Status) || (AcpiTable == NULL)) {
+ return Status;
+ }
+ //
+ // Allocate Memory for Core System Resources Table
+ //
+ mCsrt = AllocateZeroPool (sizeof (EFI_ACPI_CSRT_TABLE));
+ if (mCsrt == NULL) {
+ return EFI_BUFFER_TOO_SMALL;
+ }
+ //
+ // Constructing CSRT
+ //
+ mCsrt->Header.Signature = EFI_ACPI_5_0_CORE_SYSTEM_RESOURCE_TABLE_SIGNATURE;
+ mCsrt->Header.Length = sizeof (EFI_ACPI_CSRT_TABLE);
+ mCsrt->Header.Revision = EFI_ACPI_CSRT_TABLE_REVISION;
+ mCsrt->Header.Checksum = 0;
+ CopyMem(&mCsrt->Header.OemId, EFI_ACPI_OEM_ID, 6);
+ mCsrt->Header.OemTableId = EFI_ACPI_OEM_TABLE_ID;
+ mCsrt->Header.OemRevision = EFI_ACPI_OEM_REVISION;
+ mCsrt->Header.CreatorId = EFI_ACPI_CREATOR_ID;
+ mCsrt->Header.CreatorRevision = EFI_ACPI_CREATOR_REVISION;
+
+ LpssPciMmBase = MmPciAddress (0, PchPlatformPolicy->BusNumber, PCI_DEVICE_NUMBER_PCH_LPSS_DMAC0, PCI_FUNCTION_NUMBER_PCH_LPSS_DMAC, 0);
+ LpssMmioBase0 = MmioRead32 ((UINTN) (LpssPciMmBase + R_PCH_LPSS_DMAC_BAR)) & B_PCH_LPSS_DMAC_BAR_BA;
+
+ mCsrt->ResourceGroupsInfo1.ResourceGroupHeaderInfo.Length = sizeof (RESOURCE_GROUP_INFO1);
+ mCsrt->ResourceGroupsInfo1.ResourceGroupHeaderInfo.VendorId = 0x4C544E49;
+ mCsrt->ResourceGroupsInfo1.ResourceGroupHeaderInfo.SubVendorId = 0x00000000;
+ mCsrt->ResourceGroupsInfo1.ResourceGroupHeaderInfo.DeviceId = 0x9C60;
+ mCsrt->ResourceGroupsInfo1.ResourceGroupHeaderInfo.SubDeviceId = 0x0000;
+ mCsrt->ResourceGroupsInfo1.ResourceGroupHeaderInfo.Revision = 0x0002;
+ mCsrt->ResourceGroupsInfo1.ResourceGroupHeaderInfo.Reserved = 0x0000;
+ mCsrt->ResourceGroupsInfo1.ResourceGroupHeaderInfo.SharedInfoLength = sizeof (SHARED_INFO_SECTION);
+ mCsrt->ResourceGroupsInfo1.ResourceGroupHeaderInfo.SharedInfoSection.MajVersion = 0x0001;
+ mCsrt->ResourceGroupsInfo1.ResourceGroupHeaderInfo.SharedInfoSection.MinVersion = 0x0000;
+ mCsrt->ResourceGroupsInfo1.ResourceGroupHeaderInfo.SharedInfoSection.MMIOLowPart = LpssMmioBase0;
+ mCsrt->ResourceGroupsInfo1.ResourceGroupHeaderInfo.SharedInfoSection.MMIOHighPart = 0x00000000;
+ mCsrt->ResourceGroupsInfo1.ResourceGroupHeaderInfo.SharedInfoSection.IntGSI = 0x0000002A;
+ mCsrt->ResourceGroupsInfo1.ResourceGroupHeaderInfo.SharedInfoSection.IntPol = 0x02;
+ mCsrt->ResourceGroupsInfo1.ResourceGroupHeaderInfo.SharedInfoSection.IntMode = 0x00;
+ mCsrt->ResourceGroupsInfo1.ResourceGroupHeaderInfo.SharedInfoSection.NoOfCh = MAX_NO_CHANNEL1_SUPPORTED - 1;
+ mCsrt->ResourceGroupsInfo1.ResourceGroupHeaderInfo.SharedInfoSection.DMAAddressWidth = 0x20;
+ mCsrt->ResourceGroupsInfo1.ResourceGroupHeaderInfo.SharedInfoSection.BaseReqLine = 0x0000;
+ mCsrt->ResourceGroupsInfo1.ResourceGroupHeaderInfo.SharedInfoSection.NoOfHandSig = 0x0010;
+ mCsrt->ResourceGroupsInfo1.ResourceGroupHeaderInfo.SharedInfoSection.MaxBlockTransferSize = 0x0000FFF;
+
+ mCsrt->ResourceGroupsInfo1.ResourceDescriptorInfo[0].Length = 0x0000000C;
+ mCsrt->ResourceGroupsInfo1.ResourceDescriptorInfo[0].ResourceType = 0x0003;
+ mCsrt->ResourceGroupsInfo1.ResourceDescriptorInfo[0].ResourceSubType = 0x0001;
+ mCsrt->ResourceGroupsInfo1.ResourceDescriptorInfo[0].UUID = 0x20495053; //SPI
+
+ for (Index = 1; Index < MAX_NO_CHANNEL1_SUPPORTED; Index++) {
+ mCsrt->ResourceGroupsInfo1.ResourceDescriptorInfo[Index].Length = 0x0000000C;
+ mCsrt->ResourceGroupsInfo1.ResourceDescriptorInfo[Index].ResourceType = 0x0003;
+ mCsrt->ResourceGroupsInfo1.ResourceDescriptorInfo[Index].ResourceSubType = 0x0000;
+ mCsrt->ResourceGroupsInfo1.ResourceDescriptorInfo[Index].UUID = 0x30414843 + ((Index - 1) << 24); //CHAn
+ }
+
+ LpssPciMmBase = MmPciAddress (0, PchPlatformPolicy->BusNumber, PCI_DEVICE_NUMBER_PCH_LPSS_DMAC1, PCI_FUNCTION_NUMBER_PCH_LPSS_DMAC, 0);
+ LpssMmioBase0 = MmioRead32 ((UINTN) (LpssPciMmBase + R_PCH_LPSS_DMAC_BAR)) & B_PCH_LPSS_DMAC_BAR_BA;
+
+ mCsrt->ResourceGroupsInfo2.ResourceGroupHeaderInfo.Length = sizeof (RESOURCE_GROUP_INFO2);
+ mCsrt->ResourceGroupsInfo2.ResourceGroupHeaderInfo.VendorId = 0x4C544E49;
+ mCsrt->ResourceGroupsInfo2.ResourceGroupHeaderInfo.SubVendorId = 0x00000000;
+ mCsrt->ResourceGroupsInfo2.ResourceGroupHeaderInfo.DeviceId = 0x9C60;
+ mCsrt->ResourceGroupsInfo2.ResourceGroupHeaderInfo.SubDeviceId = 0x0000;
+ mCsrt->ResourceGroupsInfo2.ResourceGroupHeaderInfo.Revision = 0x0003;
+ mCsrt->ResourceGroupsInfo2.ResourceGroupHeaderInfo.Reserved = 0x0000;
+ mCsrt->ResourceGroupsInfo2.ResourceGroupHeaderInfo.SharedInfoLength = sizeof (SHARED_INFO_SECTION);
+ mCsrt->ResourceGroupsInfo2.ResourceGroupHeaderInfo.SharedInfoSection.MajVersion = 0x0001;
+ mCsrt->ResourceGroupsInfo2.ResourceGroupHeaderInfo.SharedInfoSection.MinVersion = 0x0000;
+ mCsrt->ResourceGroupsInfo2.ResourceGroupHeaderInfo.SharedInfoSection.MMIOLowPart = LpssMmioBase0;
+ mCsrt->ResourceGroupsInfo2.ResourceGroupHeaderInfo.SharedInfoSection.MMIOHighPart = 0x00000000;
+ mCsrt->ResourceGroupsInfo2.ResourceGroupHeaderInfo.SharedInfoSection.IntGSI = 0x0000002B;
+ mCsrt->ResourceGroupsInfo2.ResourceGroupHeaderInfo.SharedInfoSection.IntPol = 0x02;
+ mCsrt->ResourceGroupsInfo2.ResourceGroupHeaderInfo.SharedInfoSection.IntMode = 0x00;
+ mCsrt->ResourceGroupsInfo2.ResourceGroupHeaderInfo.SharedInfoSection.NoOfCh = MAX_NO_CHANNEL2_SUPPORTED - 1;
+ mCsrt->ResourceGroupsInfo2.ResourceGroupHeaderInfo.SharedInfoSection.DMAAddressWidth = 0x20;
+ mCsrt->ResourceGroupsInfo2.ResourceGroupHeaderInfo.SharedInfoSection.BaseReqLine = 0x0010;
+ mCsrt->ResourceGroupsInfo2.ResourceGroupHeaderInfo.SharedInfoSection.NoOfHandSig = 0x0010;
+ mCsrt->ResourceGroupsInfo2.ResourceGroupHeaderInfo.SharedInfoSection.MaxBlockTransferSize = 0x0000FFF;
+
+ mCsrt->ResourceGroupsInfo2.ResourceDescriptorInfo[0].Length = 0x0000000C;
+ mCsrt->ResourceGroupsInfo2.ResourceDescriptorInfo[0].ResourceType = 0x0003;
+ mCsrt->ResourceGroupsInfo2.ResourceDescriptorInfo[0].ResourceSubType = 0x0001;
+ mCsrt->ResourceGroupsInfo2.ResourceDescriptorInfo[0].UUID = 0x20433249; //I2C
+
+ for (Index = 1; Index < MAX_NO_CHANNEL2_SUPPORTED; Index++) {
+ mCsrt->ResourceGroupsInfo2.ResourceDescriptorInfo[Index].Length = 0x0000000C;
+ mCsrt->ResourceGroupsInfo2.ResourceDescriptorInfo[Index].ResourceType = 0x0003;
+ mCsrt->ResourceGroupsInfo2.ResourceDescriptorInfo[Index].ResourceSubType = 0x0000;
+ mCsrt->ResourceGroupsInfo2.ResourceDescriptorInfo[Index].UUID = 0x30414843 + ((Index - 1) << 24); //CHAn
+ }
+ //
+ // After including CSRT.asl in Acpitables.inf we are getting 2 CSRT tables. First is from the CRST.asl and the
+ // second is by installing CSRT table below. So remove the bleow code to get only one CSRT table i.e. from CSRT.asl.
+ //
+ DEBUG ((EFI_D_INFO, "Initialize CSRT End\n"));
+ }
+ }
+ }
+ //
+ // Update LPSS devices ACPI variables
+ //
+ Status = gBS->LocateProtocol (
+ &gEfiGlobalNvsAreaProtocolGuid,
+ NULL,
+ (VOID **) &GlobalNvsArea
+ );
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+#endif
+ //
+ // LPSS2 DMA
+ //
+ if (PchPlatformPolicy->LpssConfig->Dma1Enabled != PchDisabled) {
+
+ LpssPciMmBase = MmPciAddress (
+ 0,
+ PchPlatformPolicy->BusNumber,
+ PCI_DEVICE_NUMBER_PCH_LPSS_DMAC1,
+ PCI_FUNCTION_NUMBER_PCH_LPSS_DMAC,
+ 0
+ );
+ if (MmioRead32 (LpssPciMmBase) != 0xFFFFFFFF) {
+ LpssMmioBase0 = MmioRead32 ((UINTN) (LpssPciMmBase + R_PCH_LPSS_DMAC_BAR)) & B_PCH_LPSS_DMAC_BAR_BA;
+ ASSERT ((LpssMmioBase0 != 0) && (LpssMmioBase0 != B_PCH_LPSS_DMAC_BAR_BA));
+ LpssMmioBase1 = MmioRead32 ((UINTN) (LpssPciMmBase + R_PCH_LPSS_DMAC_BAR1)) & B_PCH_LPSS_DMAC_BAR1_BA;
+ ASSERT ((LpssMmioBase1 != 0) && (LpssMmioBase1 != B_PCH_LPSS_DMAC_BAR1_BA));
+ if (!IsSetS3BootScript) {
+
+ Data32Or = (UINT32) (B_PCH_LPSS_DMAC_STSCMD_INTRDIS | B_PCH_LPSS_DMAC_STSCMD_BME | B_PCH_LPSS_DMAC_STSCMD_MSE);
+ Data32And = 0xFFFFFFFF;
+ MmioOr32 (
+ (UINTN) (LpssPciMmBase + R_PCH_LPSS_DMAC_STSCMD),
+ Data32Or
+ );
+#ifndef FSP_FLAG
+ //
+ // Update BAR and length in ACPI table.
+ //
+ GlobalNvsArea->Area->LDMA2Addr = LpssMmioBase0;
+ GlobalNvsArea->Area->LDMA2Len = V_PCH_LPSS_DMAC_BAR_SIZE;
+ GlobalNvsArea->Area->LDMA21Addr = LpssMmioBase1;
+ GlobalNvsArea->Area->LDMA21Len = V_PCH_LPSS_DMAC_BAR1_SIZE;
+#endif
+
+ PchMsgBusAndThenOr32 (
+ 0xA0,
+ 0x280,
+ 0xFFFFFFFF,
+ (BIT21 | BIT20),
+ 0x06,
+ 0x07
+ );
+
+ PchMsgBusAndThenOr32 (
+ 0xA0,
+ 0x154,
+ (UINT32) ~(BIT3),
+ (0x00),
+ 0x06,
+ 0x07
+ );
+ } else {
+ //
+ // Set S3 Boot Script
+ //
+ S3BootScriptSaveMemWrite (
+ S3BootScriptWidthUint32,
+ (UINTN) (LpssPciMmBase + R_PCH_LPSS_DMAC_BAR),
+ 1,
+ &LpssMmioBase0
+ );
+ S3BootScriptSaveMemWrite (
+ S3BootScriptWidthUint32,
+ (UINTN) (LpssPciMmBase + R_PCH_LPSS_DMAC_BAR1),
+ 1,
+ &LpssMmioBase1
+ );
+ Data32Or = (UINT32) (B_PCH_LPSS_DMAC_STSCMD_INTRDIS | B_PCH_LPSS_DMAC_STSCMD_BME | B_PCH_LPSS_DMAC_STSCMD_MSE);
+ Data32And = 0xFFFFFFFF;
+ S3BootScriptSaveMemReadWrite (
+ EfiBootScriptWidthUint32,
+ (UINTN) (LpssPciMmBase + R_PCH_LPSS_DMAC_STSCMD),
+ &Data32Or, // OR mask
+ &Data32And // AND mask
+ );
+ SetMsgBusAndThenOr32S3Item (
+ 0xa0,
+ 0x280,
+ 0xFFFFFFFF,
+ (BIT21 | BIT20),
+ 0x06,
+ 0x07
+ );
+ SetMsgBusAndThenOr32S3Item (
+ 0xa0,
+ 0x154,
+ (UINT32) ~(BIT3),
+ (0x00),
+ 0x06,
+ 0x07
+ );
+ }
+ }
+ }
+
+ //
+ // LPSS2 I2C 0
+ //
+ if (PchPlatformPolicy->LpssConfig->I2C0Enabled != PchDisabled) {
+
+ LpssPciMmBase = MmPciAddress (
+ 0,
+ PchPlatformPolicy->BusNumber,
+ PCI_DEVICE_NUMBER_PCH_LPSS_I2C,
+ PCI_FUNCTION_NUMBER_PCH_LPSS_I2C0,
+ 0
+ );
+ if (MmioRead32 (LpssPciMmBase) != 0xFFFFFFFF) {
+ LpssMmioBase0 = MmioRead32 ((UINTN) (LpssPciMmBase + R_PCH_LPSS_I2C_BAR)) & B_PCH_LPSS_I2C_BAR_BA;
+ ASSERT ((LpssMmioBase0 != 0) && (LpssMmioBase0 != B_PCH_LPSS_I2C_BAR_BA));
+ LpssMmioBase1 = MmioRead32 ((UINTN) (LpssPciMmBase + R_PCH_LPSS_I2C_BAR1)) & B_PCH_LPSS_I2C_BAR1_BA;
+ ASSERT ((LpssMmioBase1 != 0) && (LpssMmioBase1 != B_PCH_LPSS_I2C_BAR1_BA));
+ if (!IsSetS3BootScript) {
+
+ Data32Or = (UINT32) (B_PCH_LPSS_I2C_STSCMD_INTRDIS | B_PCH_LPSS_I2C_STSCMD_BME | B_PCH_LPSS_I2C_STSCMD_MSE);
+ Data32And = 0xFFFFFFFF;
+ MmioOr32 (
+ (UINTN) (LpssPciMmBase + R_PCH_LPSS_I2C_STSCMD),
+ Data32Or
+ );
+#ifndef FSP_FLAG
+ //
+ // Update BAR and length in ACPI table.
+ //
+ GlobalNvsArea->Area->I2C1Addr = LpssMmioBase0;
+ GlobalNvsArea->Area->I2C1Len = V_PCH_LPSS_I2C_BAR_SIZE;
+ GlobalNvsArea->Area->I2C11Addr = LpssMmioBase1;
+ GlobalNvsArea->Area->I2C11Len = V_PCH_LPSS_I2C_BAR1_SIZE;
+#endif
+
+ PchMsgBusAndThenOr32 (
+ 0xa0,
+ 0x288,
+ 0xFFFFFFFF,
+ (BIT21 | BIT20),
+ 0x06,
+ 0x07
+ );
+ } else {
+ //
+ // Set S3 Boot Script
+ //
+ S3BootScriptSaveMemWrite (
+ S3BootScriptWidthUint32,
+ (UINTN) (LpssPciMmBase + R_PCH_LPSS_I2C_BAR),
+ 1,
+ &LpssMmioBase0
+ );
+ S3BootScriptSaveMemWrite (
+ S3BootScriptWidthUint32,
+ (UINTN) (LpssPciMmBase + R_PCH_LPSS_I2C_BAR1),
+ 1,
+ &LpssMmioBase1
+ );
+ Data32Or = (UINT32) (B_PCH_LPSS_I2C_STSCMD_INTRDIS | B_PCH_LPSS_I2C_STSCMD_BME | B_PCH_LPSS_I2C_STSCMD_MSE);
+ Data32And = 0xFFFFFFFF;
+ S3BootScriptSaveMemReadWrite (
+ EfiBootScriptWidthUint32,
+ (UINTN) (LpssPciMmBase + R_PCH_LPSS_I2C_STSCMD),
+ &Data32Or, // OR mask
+ &Data32And // AND mask
+ );
+ SetMsgBusAndThenOr32S3Item (
+ 0xa0,
+ 0x288,
+ 0xFFFFFFFF,
+ (BIT21 | BIT20),
+ 0x06,
+ 0x07
+ );
+ }
+ }
+ }
+
+ //
+ // LPSS2 I2C 1
+ //
+ if (PchPlatformPolicy->LpssConfig->I2C1Enabled != PchDisabled) {
+
+ LpssPciMmBase = MmPciAddress (
+ 0,
+ PchPlatformPolicy->BusNumber,
+ PCI_DEVICE_NUMBER_PCH_LPSS_I2C,
+ PCI_FUNCTION_NUMBER_PCH_LPSS_I2C1,
+ 0
+ );
+ if (MmioRead32 (LpssPciMmBase) != 0xFFFFFFFF) {
+ LpssMmioBase0 = MmioRead32 ((UINTN) (LpssPciMmBase + R_PCH_LPSS_I2C_BAR)) & B_PCH_LPSS_I2C_BAR_BA;
+ ASSERT ((LpssMmioBase0 != 0) && (LpssMmioBase0 != B_PCH_LPSS_I2C_BAR_BA));
+ LpssMmioBase1 = MmioRead32 ((UINTN) (LpssPciMmBase + R_PCH_LPSS_I2C_BAR1)) & B_PCH_LPSS_I2C_BAR1_BA;
+ ASSERT ((LpssMmioBase1 != 0) && (LpssMmioBase1 != B_PCH_LPSS_I2C_BAR1_BA));
+ if (!IsSetS3BootScript) {
+
+ Data32Or = (UINT32) (B_PCH_LPSS_I2C_STSCMD_INTRDIS | B_PCH_LPSS_I2C_STSCMD_BME | B_PCH_LPSS_I2C_STSCMD_MSE);
+ Data32And = 0xFFFFFFFF;
+ MmioOr32 (
+ (UINTN) (LpssPciMmBase + R_PCH_LPSS_I2C_STSCMD),
+ Data32Or
+ );
+#ifndef FSP_FLAG
+ //
+ // Update BAR and length in ACPI table.
+ //
+ GlobalNvsArea->Area->I2C2Addr = LpssMmioBase0;
+ GlobalNvsArea->Area->I2C2Len = V_PCH_LPSS_I2C_BAR_SIZE;
+ GlobalNvsArea->Area->I2C21Addr = LpssMmioBase1;
+ GlobalNvsArea->Area->I2C21Len = V_PCH_LPSS_I2C_BAR1_SIZE;
+#endif
+
+ PchMsgBusAndThenOr32 (
+ 0xa0,
+ 0x290,
+ 0xFFFFFFFF,
+ (BIT21 | BIT20),
+ 0x06,
+ 0x07
+ );
+ } else {
+ //
+ // Set S3 Boot Script
+ //
+ S3BootScriptSaveMemWrite (
+ S3BootScriptWidthUint32,
+ (UINTN) (LpssPciMmBase + R_PCH_LPSS_I2C_BAR),
+ 1,
+ &LpssMmioBase0
+ );
+ S3BootScriptSaveMemWrite (
+ S3BootScriptWidthUint32,
+ (UINTN) (LpssPciMmBase + R_PCH_LPSS_I2C_BAR1),
+ 1,
+ &LpssMmioBase1
+ );
+ Data32Or = (UINT32) (B_PCH_LPSS_I2C_STSCMD_INTRDIS | B_PCH_LPSS_I2C_STSCMD_BME | B_PCH_LPSS_I2C_STSCMD_MSE);
+ Data32And = 0xFFFFFFFF;
+ S3BootScriptSaveMemReadWrite (
+ EfiBootScriptWidthUint32,
+ (UINTN) (LpssPciMmBase + R_PCH_LPSS_I2C_STSCMD),
+ &Data32Or, // OR mask
+ &Data32And // AND mask
+ );
+ SetMsgBusAndThenOr32S3Item (
+ 0xA0,
+ 0x290,
+ 0xFFFFFFFF,
+ (BIT21 | BIT20),
+ 0x06,
+ 0x07
+ );
+ }
+ }
+ }
+
+ //
+ // LPSS2 I2C 2
+ //
+ if (PchPlatformPolicy->LpssConfig->I2C2Enabled != PchDisabled) {
+
+ LpssPciMmBase = MmPciAddress (
+ 0,
+ PchPlatformPolicy->BusNumber,
+ PCI_DEVICE_NUMBER_PCH_LPSS_I2C,
+ PCI_FUNCTION_NUMBER_PCH_LPSS_I2C2,
+ 0
+ );
+ if (MmioRead32 (LpssPciMmBase) != 0xFFFFFFFF) {
+ LpssMmioBase0 = MmioRead32 ((UINTN) (LpssPciMmBase + R_PCH_LPSS_I2C_BAR)) & B_PCH_LPSS_I2C_BAR_BA;
+ ASSERT ((LpssMmioBase0 != 0) && (LpssMmioBase0 != B_PCH_LPSS_I2C_BAR_BA));
+ LpssMmioBase1 = MmioRead32 ((UINTN) (LpssPciMmBase + R_PCH_LPSS_I2C_BAR1)) & B_PCH_LPSS_I2C_BAR1_BA;
+ ASSERT ((LpssMmioBase1 != 0) && (LpssMmioBase1 != B_PCH_LPSS_I2C_BAR1_BA));
+ if (!IsSetS3BootScript) {
+
+ Data32Or = (UINT32) (B_PCH_LPSS_I2C_STSCMD_INTRDIS | B_PCH_LPSS_I2C_STSCMD_BME | B_PCH_LPSS_I2C_STSCMD_MSE);
+ Data32And = 0xFFFFFFFF;
+ MmioOr32 (
+ (UINTN) (LpssPciMmBase + R_PCH_LPSS_I2C_STSCMD),
+ Data32Or
+ );
+#ifndef FSP_FLAG
+ //
+ // Update BAR and length in ACPI table.
+ //
+ GlobalNvsArea->Area->I2C3Addr = LpssMmioBase0;
+ GlobalNvsArea->Area->I2C3Len = V_PCH_LPSS_I2C_BAR_SIZE;
+ GlobalNvsArea->Area->I2C31Addr = LpssMmioBase1;
+ GlobalNvsArea->Area->I2C31Len = V_PCH_LPSS_I2C_BAR1_SIZE;
+#endif
+
+ PchMsgBusAndThenOr32 (
+ 0xa0,
+ 0x298,
+ 0xFFFFFFFF,
+ (BIT21| BIT20),
+ 0x06,
+ 0x07
+ );
+ } else {
+ //
+ // Set S3 Boot Script
+ //
+ S3BootScriptSaveMemWrite (
+ S3BootScriptWidthUint32,
+ (UINTN) (LpssPciMmBase + R_PCH_LPSS_I2C_BAR),
+ 1,
+ &LpssMmioBase0
+ );
+ S3BootScriptSaveMemWrite (
+ S3BootScriptWidthUint32,
+ (UINTN) (LpssPciMmBase + R_PCH_LPSS_I2C_BAR1),
+ 1,
+ &LpssMmioBase1
+ );
+ Data32Or = (UINT32) (B_PCH_LPSS_I2C_STSCMD_INTRDIS | B_PCH_LPSS_I2C_STSCMD_BME | B_PCH_LPSS_I2C_STSCMD_MSE);
+ Data32And = 0xFFFFFFFF;
+ S3BootScriptSaveMemReadWrite (
+ EfiBootScriptWidthUint32,
+ (UINTN) (LpssPciMmBase + R_PCH_LPSS_I2C_STSCMD),
+ &Data32Or, // OR mask
+ &Data32And // AND mask
+ );
+ SetMsgBusAndThenOr32S3Item (
+ 0xa0,
+ 0x298,
+ 0xFFFFFFFF,
+ (BIT21| BIT20),
+ 0x06,
+ 0x07
+ );
+ }
+ }
+ }
+
+ //
+ // LPSS2 I2C 3
+ //
+ if (PchPlatformPolicy->LpssConfig->I2C3Enabled != PchDisabled) {
+
+ LpssPciMmBase = MmPciAddress (
+ 0,
+ PchPlatformPolicy->BusNumber,
+ PCI_DEVICE_NUMBER_PCH_LPSS_I2C,
+ PCI_FUNCTION_NUMBER_PCH_LPSS_I2C3,
+ 0
+ );
+ if (MmioRead32 (LpssPciMmBase) != 0xFFFFFFFF) {
+ LpssMmioBase0 = MmioRead32 ((UINTN) (LpssPciMmBase + R_PCH_LPSS_I2C_BAR)) & B_PCH_LPSS_I2C_BAR_BA;
+ ASSERT ((LpssMmioBase0 != 0) && (LpssMmioBase0 != B_PCH_LPSS_I2C_BAR_BA));
+ LpssMmioBase1 = MmioRead32 ((UINTN) (LpssPciMmBase + R_PCH_LPSS_I2C_BAR1)) & B_PCH_LPSS_I2C_BAR1_BA;
+ ASSERT ((LpssMmioBase1 != 0) && (LpssMmioBase1 != B_PCH_LPSS_I2C_BAR1_BA));
+ if (!IsSetS3BootScript) {
+
+ Data32Or = (UINT32) (B_PCH_LPSS_I2C_STSCMD_INTRDIS | B_PCH_LPSS_I2C_STSCMD_BME | B_PCH_LPSS_I2C_STSCMD_MSE);
+ Data32And = 0xFFFFFFFF;
+ MmioOr32 (
+ (UINTN) (LpssPciMmBase + R_PCH_LPSS_I2C_STSCMD),
+ Data32Or
+ );
+#ifndef FSP_FLAG
+ //
+ // Update BAR and length in ACPI table.
+ //
+ GlobalNvsArea->Area->I2C4Addr = LpssMmioBase0;
+ GlobalNvsArea->Area->I2C4Len = V_PCH_LPSS_I2C_BAR_SIZE;
+ GlobalNvsArea->Area->I2C41Addr = LpssMmioBase1;
+ GlobalNvsArea->Area->I2C41Len = V_PCH_LPSS_I2C_BAR1_SIZE;
+#endif
+
+ PchMsgBusAndThenOr32 (
+ 0xa0,
+ 0x2a0,
+ 0xFFFFFFFF,
+ (BIT21| BIT20),
+ 0x06,
+ 0x07
+ );
+ } else {
+ //
+ // Set S3 Boot Script
+ //
+ S3BootScriptSaveMemWrite (
+ S3BootScriptWidthUint32,
+ (UINTN) (LpssPciMmBase + R_PCH_LPSS_I2C_BAR),
+ 1,
+ &LpssMmioBase0
+ );
+ S3BootScriptSaveMemWrite (
+ S3BootScriptWidthUint32,
+ (UINTN) (LpssPciMmBase + R_PCH_LPSS_I2C_BAR1),
+ 1,
+ &LpssMmioBase1
+ );
+ Data32Or = (UINT32) (B_PCH_LPSS_I2C_STSCMD_INTRDIS | B_PCH_LPSS_I2C_STSCMD_BME | B_PCH_LPSS_I2C_STSCMD_MSE);
+ Data32And = 0xFFFFFFFF;
+ S3BootScriptSaveMemReadWrite (
+ EfiBootScriptWidthUint32,
+ (UINTN) (LpssPciMmBase + R_PCH_LPSS_I2C_STSCMD),
+ &Data32Or, // OR mask
+ &Data32And // AND mask
+ );
+ SetMsgBusAndThenOr32S3Item (
+ 0xa0,
+ 0x2a0,
+ 0xFFFFFFFF,
+ (BIT21| BIT20),
+ 0x06,
+ 0x07
+ );
+ }
+ }
+ }
+
+ //
+ // LPSS I2C 4
+ //
+ if (PchPlatformPolicy->LpssConfig->I2C4Enabled != PchDisabled) {
+
+ LpssPciMmBase = MmPciAddress (
+ 0,
+ PchPlatformPolicy->BusNumber,
+ PCI_DEVICE_NUMBER_PCH_LPSS_I2C,
+ PCI_FUNCTION_NUMBER_PCH_LPSS_I2C4,
+ 0
+ );
+ if (MmioRead32 (LpssPciMmBase) != 0xFFFFFFFF) {
+ LpssMmioBase0 = MmioRead32 ((UINTN) (LpssPciMmBase + R_PCH_LPSS_I2C_BAR)) & B_PCH_LPSS_I2C_BAR_BA;
+ ASSERT ((LpssMmioBase0 != 0) && (LpssMmioBase0 != B_PCH_LPSS_I2C_BAR_BA));
+ LpssMmioBase1 = MmioRead32 ((UINTN) (LpssPciMmBase + R_PCH_LPSS_I2C_BAR1)) & B_PCH_LPSS_I2C_BAR1_BA;
+ ASSERT ((LpssMmioBase1 != 0) && (LpssMmioBase1 != B_PCH_LPSS_I2C_BAR1_BA));
+ if (!IsSetS3BootScript) {
+
+ Data32Or = (UINT32) (B_PCH_LPSS_I2C_STSCMD_INTRDIS | B_PCH_LPSS_I2C_STSCMD_BME | B_PCH_LPSS_I2C_STSCMD_MSE);
+ Data32And = 0xFFFFFFFF;
+ MmioOr32 (
+ (UINTN) (LpssPciMmBase + R_PCH_LPSS_I2C_STSCMD),
+ Data32Or
+ );
+#ifndef FSP_FLAG
+ //
+ // Update BAR and length in ACPI table.
+ //
+ GlobalNvsArea->Area->I2C5Addr = LpssMmioBase0;
+ GlobalNvsArea->Area->I2C5Len = V_PCH_LPSS_I2C_BAR_SIZE;
+ GlobalNvsArea->Area->I2C51Addr = LpssMmioBase1;
+ GlobalNvsArea->Area->I2C51Len = V_PCH_LPSS_I2C_BAR1_SIZE;
+#endif
+
+ PchMsgBusAndThenOr32 (
+ 0xa0,
+ 0x2a8,
+ 0xFFFFFFFF,
+ (BIT21| BIT20),
+ 0x06,
+ 0x07
+ );
+ } else {
+ //
+ // Set S3 Boot Script
+ //
+ S3BootScriptSaveMemWrite (
+ S3BootScriptWidthUint32,
+ (UINTN) (LpssPciMmBase + R_PCH_LPSS_I2C_BAR),
+ 1,
+ &LpssMmioBase0
+ );
+ S3BootScriptSaveMemWrite (
+ S3BootScriptWidthUint32,
+ (UINTN) (LpssPciMmBase + R_PCH_LPSS_I2C_BAR1),
+ 1,
+ &LpssMmioBase1
+ );
+ Data32Or = (UINT32) (B_PCH_LPSS_I2C_STSCMD_INTRDIS | B_PCH_LPSS_I2C_STSCMD_BME | B_PCH_LPSS_I2C_STSCMD_MSE);
+ Data32And = 0xFFFFFFFF;
+ S3BootScriptSaveMemReadWrite (
+ EfiBootScriptWidthUint32,
+ (UINTN) (LpssPciMmBase + R_PCH_LPSS_I2C_STSCMD),
+ &Data32Or, // OR mask
+ &Data32And // AND mask
+ );
+ SetMsgBusAndThenOr32S3Item (
+ 0xa0,
+ 0x2a8,
+ 0xFFFFFFFF,
+ (BIT21| BIT20),
+ 0x06,
+ 0x07
+ );
+ }
+ }
+ }
+
+ //
+ // LPSS2 I2C 5
+ //
+ if (PchPlatformPolicy->LpssConfig->I2C5Enabled != PchDisabled) {
+
+ LpssPciMmBase = MmPciAddress (
+ 0,
+ PchPlatformPolicy->BusNumber,
+ PCI_DEVICE_NUMBER_PCH_LPSS_I2C,
+ PCI_FUNCTION_NUMBER_PCH_LPSS_I2C5,
+ 0
+ );
+ if (MmioRead32 (LpssPciMmBase) != 0xFFFFFFFF) {
+ LpssMmioBase0 = MmioRead32 ((UINTN) (LpssPciMmBase + R_PCH_LPSS_I2C_BAR)) & B_PCH_LPSS_I2C_BAR_BA;
+ ASSERT ((LpssMmioBase0 != 0) && (LpssMmioBase0 != B_PCH_LPSS_I2C_BAR_BA));
+ LpssMmioBase1 = MmioRead32 ((UINTN) (LpssPciMmBase + R_PCH_LPSS_I2C_BAR1)) & B_PCH_LPSS_I2C_BAR1_BA;
+ ASSERT ((LpssMmioBase1 != 0) && (LpssMmioBase1 != B_PCH_LPSS_I2C_BAR1_BA));
+ if (!IsSetS3BootScript) {
+
+ Data32Or = (UINT32) (B_PCH_LPSS_I2C_STSCMD_INTRDIS | B_PCH_LPSS_I2C_STSCMD_BME | B_PCH_LPSS_I2C_STSCMD_MSE);
+ Data32And = 0xFFFFFFFF;
+ MmioOr32 (
+ (UINTN) (LpssPciMmBase + R_PCH_LPSS_I2C_STSCMD),
+ Data32Or
+ );
+#ifndef FSP_FLAG
+ //
+ // Update BAR and length in ACPI table.
+ //
+ GlobalNvsArea->Area->I2C6Addr = LpssMmioBase0;
+ GlobalNvsArea->Area->I2C6Len = V_PCH_LPSS_I2C_BAR_SIZE;
+ GlobalNvsArea->Area->I2C61Addr = LpssMmioBase1;
+ GlobalNvsArea->Area->I2C61Len = V_PCH_LPSS_I2C_BAR1_SIZE;
+#endif
+
+ PchMsgBusAndThenOr32 (
+ 0xa0,
+ 0x2b0,
+ 0xFFFFFFFF,
+ (BIT21| BIT20),
+ 0x06,
+ 0x07
+ );
+ } else {
+ //
+ // Set S3 Boot Script
+ //
+ S3BootScriptSaveMemWrite (
+ S3BootScriptWidthUint32,
+ (UINTN) (LpssPciMmBase + R_PCH_LPSS_I2C_BAR),
+ 1,
+ &LpssMmioBase0
+ );
+ S3BootScriptSaveMemWrite (
+ S3BootScriptWidthUint32,
+ (UINTN) (LpssPciMmBase + R_PCH_LPSS_I2C_BAR1),
+ 1,
+ &LpssMmioBase1
+ );
+ Data32Or = (UINT32) (B_PCH_LPSS_I2C_STSCMD_INTRDIS | B_PCH_LPSS_I2C_STSCMD_BME | B_PCH_LPSS_I2C_STSCMD_MSE);
+ Data32And = 0xFFFFFFFF;
+ S3BootScriptSaveMemReadWrite (
+ EfiBootScriptWidthUint32,
+ (UINTN) (LpssPciMmBase + R_PCH_LPSS_I2C_STSCMD),
+ &Data32Or, // OR mask
+ &Data32And // AND mask
+ );
+ SetMsgBusAndThenOr32S3Item (
+ 0xa0,
+ 0x2b0,
+ 0xFFFFFFFF,
+ (BIT21| BIT20),
+ 0x06,
+ 0x07
+ );
+ }
+ }
+ }
+
+ //
+ // LPSS2 I2C 6
+ //
+ if (PchPlatformPolicy->LpssConfig->I2C6Enabled != PchDisabled) {
+
+ LpssPciMmBase = MmPciAddress (
+ 0,
+ PchPlatformPolicy->BusNumber,
+ PCI_DEVICE_NUMBER_PCH_LPSS_I2C,
+ PCI_FUNCTION_NUMBER_PCH_LPSS_I2C6,
+ 0
+ );
+ if (MmioRead32 (LpssPciMmBase) != 0xFFFFFFFF) {
+ LpssMmioBase0 = MmioRead32 ((UINTN) (LpssPciMmBase + R_PCH_LPSS_I2C_BAR)) & B_PCH_LPSS_I2C_BAR_BA;
+ ASSERT ((LpssMmioBase0 != 0) && (LpssMmioBase0 != B_PCH_LPSS_I2C_BAR_BA));
+ LpssMmioBase1 = MmioRead32 ((UINTN) (LpssPciMmBase + R_PCH_LPSS_I2C_BAR1)) & B_PCH_LPSS_I2C_BAR1_BA;
+ ASSERT ((LpssMmioBase1 != 0) && (LpssMmioBase1 != B_PCH_LPSS_I2C_BAR1_BA));
+ if (!IsSetS3BootScript) {
+
+ Data32Or = (UINT32) (B_PCH_LPSS_I2C_STSCMD_INTRDIS | B_PCH_LPSS_I2C_STSCMD_BME | B_PCH_LPSS_I2C_STSCMD_MSE);
+ Data32And = 0xFFFFFFFF;
+ MmioOr32 (
+ (UINTN) (LpssPciMmBase + R_PCH_LPSS_I2C_STSCMD),
+ Data32Or
+ );
+#ifndef FSP_FLAG
+ //
+ // Update BAR and length in ACPI table.
+ //
+ GlobalNvsArea->Area->I2C7Addr = LpssMmioBase0;
+ GlobalNvsArea->Area->I2C7Len = V_PCH_LPSS_I2C_BAR_SIZE;
+ GlobalNvsArea->Area->I2C71Addr = LpssMmioBase1;
+ GlobalNvsArea->Area->I2C71Len = V_PCH_LPSS_I2C_BAR1_SIZE;
+#endif
+
+ PchMsgBusAndThenOr32 (
+ 0xa0,
+ 0x2b8,
+ 0xFFFFFFFF,
+ (BIT21| BIT20),
+ 0x06,
+ 0x07
+ );
+ } else {
+ //
+ // Set S3 Boot Script
+ //
+ S3BootScriptSaveMemWrite (
+ S3BootScriptWidthUint32,
+ (UINTN) (LpssPciMmBase + R_PCH_LPSS_I2C_BAR),
+ 1,
+ &LpssMmioBase0
+ );
+ S3BootScriptSaveMemWrite (
+ S3BootScriptWidthUint32,
+ (UINTN) (LpssPciMmBase + R_PCH_LPSS_I2C_BAR1),
+ 1,
+ &LpssMmioBase1
+ );
+ Data32Or = (UINT32) (B_PCH_LPSS_I2C_STSCMD_INTRDIS | B_PCH_LPSS_I2C_STSCMD_BME | B_PCH_LPSS_I2C_STSCMD_MSE);
+ Data32And = 0xFFFFFFFF;
+ S3BootScriptSaveMemReadWrite (
+ EfiBootScriptWidthUint32,
+ (UINTN) (LpssPciMmBase + R_PCH_LPSS_I2C_STSCMD),
+ &Data32Or, // OR mask
+ &Data32And // AND mask
+ );
+ SetMsgBusAndThenOr32S3Item (
+ 0xa0,
+ 0x2b8,
+ 0xFFFFFFFF,
+ (BIT21| BIT20),
+ 0x06,
+ 0x07
+ );
+ }
+ }
+ }
+
+ //
+ // LPSS1 DMA
+ //
+ if (PchPlatformPolicy->LpssConfig->Dma0Enabled != PchDisabled) {
+
+ LpssPciMmBase = MmPciAddress (
+ 0,
+ PchPlatformPolicy->BusNumber,
+ PCI_DEVICE_NUMBER_PCH_LPSS_DMAC0,
+ PCI_FUNCTION_NUMBER_PCH_LPSS_DMAC,
+ 0
+ );
+ if (MmioRead32 (LpssPciMmBase) != 0xFFFFFFFF) {
+ LpssMmioBase0 = MmioRead32 ((UINTN) (LpssPciMmBase + R_PCH_LPSS_DMAC_BAR)) & B_PCH_LPSS_DMAC_BAR_BA;
+ ASSERT ((LpssMmioBase0 != 0) && (LpssMmioBase0 != B_PCH_LPSS_DMAC_BAR_BA));
+ LpssMmioBase1 = MmioRead32 ((UINTN) (LpssPciMmBase + R_PCH_LPSS_DMAC_BAR1)) & B_PCH_LPSS_DMAC_BAR1_BA;
+ ASSERT ((LpssMmioBase1 != 0) && (LpssMmioBase1 != B_PCH_LPSS_DMAC_BAR1_BA));
+ if (!IsSetS3BootScript) {
+
+ Data32Or = (UINT32) (B_PCH_LPSS_DMAC_STSCMD_INTRDIS | B_PCH_LPSS_DMAC_STSCMD_BME | B_PCH_LPSS_DMAC_STSCMD_MSE);
+ Data32And = 0xFFFFFFFF;
+ MmioOr32 (
+ (UINTN) (LpssPciMmBase + R_PCH_LPSS_DMAC_STSCMD),
+ Data32Or
+ );
+#ifndef FSP_FLAG
+ //
+ // Update BAR and length in ACPI table.
+ //
+ GlobalNvsArea->Area->LDMA1Addr = LpssMmioBase0;
+ GlobalNvsArea->Area->LDMA1Len = V_PCH_LPSS_DMAC_BAR_SIZE;
+ GlobalNvsArea->Area->LDMA11Addr = LpssMmioBase1;
+ GlobalNvsArea->Area->LDMA11Len = V_PCH_LPSS_DMAC_BAR1_SIZE;
+#endif
+
+ PchMsgBusAndThenOr32 (
+ 0xa0,
+ 0x240,
+ 0xFFFFFFFF,
+ (BIT21| BIT20),
+ 0x06,
+ 0x07
+ );
+
+ PchMsgBusAndThenOr32 (
+ 0xa0,
+ 0x154,
+ (UINT32) ~(BIT2),
+ (0x00),
+ 0x06,
+ 0x07
+ );
+ } else {
+ //
+ // Set S3 Boot Script
+ //
+ S3BootScriptSaveMemWrite (
+ S3BootScriptWidthUint32,
+ (UINTN) (LpssPciMmBase + R_PCH_LPSS_DMAC_BAR),
+ 1,
+ &LpssMmioBase0
+ );
+ S3BootScriptSaveMemWrite (
+ S3BootScriptWidthUint32,
+ (UINTN) (LpssPciMmBase + R_PCH_LPSS_DMAC_BAR1),
+ 1,
+ &LpssMmioBase1
+ );
+ Data32Or = (UINT32) (B_PCH_LPSS_DMAC_STSCMD_INTRDIS | B_PCH_LPSS_DMAC_STSCMD_BME | B_PCH_LPSS_DMAC_STSCMD_MSE);
+ Data32And = 0xFFFFFFFF;
+ S3BootScriptSaveMemReadWrite (
+ EfiBootScriptWidthUint32,
+ (UINTN) (LpssPciMmBase + R_PCH_LPSS_DMAC_STSCMD),
+ &Data32Or, // OR mask
+ &Data32And // AND mask
+ );
+ SetMsgBusAndThenOr32S3Item (
+ 0xa0,
+ 0x240,
+ 0xFFFFFFFF,
+ (BIT21| BIT20),
+ 0x06,
+ 0x07
+ );
+ SetMsgBusAndThenOr32S3Item (
+ 0xa0,
+ 0x154,
+ (UINT32) ~(BIT2),
+ (0x00),
+ 0x06,
+ 0x07
+ );
+ }
+ }
+ }
+
+ //
+ // LPSS1 PWM 0
+ //
+ if (PchPlatformPolicy->LpssConfig->Pwm0Enabled == PchAcpiMode) {
+
+ LpssPciMmBase = MmPciAddress (
+ 0,
+ PchPlatformPolicy->BusNumber,
+ PCI_DEVICE_NUMBER_PCH_LPSS_PWM,
+ PCI_FUNCTION_NUMBER_PCH_LPSS_PWM0,
+ 0
+ );
+ LpssMmioBase0 = MmioRead32 ((UINTN) (LpssPciMmBase + R_PCH_LPSS_PWM_BAR)) & B_PCH_LPSS_PWM_BAR_BA;
+ ASSERT ((LpssMmioBase0 != 0) && (LpssMmioBase0 != B_PCH_LPSS_PWM_BAR_BA));
+ LpssMmioBase1 = MmioRead32 ((UINTN) (LpssPciMmBase + R_PCH_LPSS_PWM_BAR1)) & B_PCH_LPSS_PWM_BAR1_BA;
+ ASSERT ((LpssMmioBase1 != 0) && (LpssMmioBase1 != B_PCH_LPSS_PWM_BAR1_BA));
+ if (!IsSetS3BootScript) {
+
+ Data32Or = (UINT32) (B_PCH_LPSS_PWM_STSCMD_INTRDIS | B_PCH_LPSS_PWM_STSCMD_BME | B_PCH_LPSS_PWM_STSCMD_MSE);
+ Data32And = 0xFFFFFFFF;
+ MmioOr32 (
+ (UINTN) (LpssPciMmBase + R_PCH_LPSS_PWM_STSCMD),
+ Data32Or
+ );
+#ifndef FSP_FLAG
+ //
+ // Update BAR and length in ACPI table.
+ //
+ GlobalNvsArea->Area->PWM1Addr = LpssMmioBase0;
+ GlobalNvsArea->Area->PWM1Len = V_PCH_LPSS_PWM_BAR_SIZE;
+ GlobalNvsArea->Area->PWM11Addr = LpssMmioBase1;
+ GlobalNvsArea->Area->PWM11Len = V_PCH_LPSS_PWM_BAR1_SIZE;
+#endif
+
+ PchMsgBusAndThenOr32 (
+ 0xa0,
+ 0x248,
+ 0xFFFFFFFF,
+ (BIT21| BIT20),
+ 0x06,
+ 0x07
+ );
+ } else {
+ //
+ // Set S3 Boot Script
+ //
+ S3BootScriptSaveMemWrite (
+ S3BootScriptWidthUint32,
+ (UINTN) (LpssPciMmBase + R_PCH_LPSS_PWM_BAR),
+ 1,
+ &LpssMmioBase0
+ );
+ S3BootScriptSaveMemWrite (
+ S3BootScriptWidthUint32,
+ (UINTN) (LpssPciMmBase + R_PCH_LPSS_PWM_BAR1),
+ 1,
+ &LpssMmioBase1
+ );
+ Data32Or = (UINT32) (B_PCH_LPSS_PWM_STSCMD_INTRDIS | B_PCH_LPSS_PWM_STSCMD_BME | B_PCH_LPSS_PWM_STSCMD_MSE);
+ Data32And = 0xFFFFFFFF;
+ S3BootScriptSaveMemReadWrite (
+ EfiBootScriptWidthUint32,
+ (UINTN) (LpssPciMmBase + R_PCH_LPSS_PWM_STSCMD),
+ &Data32Or, // OR mask
+ &Data32And // AND mask
+ );
+ SetMsgBusAndThenOr32S3Item (
+ 0xa0,
+ 0x248,
+ 0xFFFFFFFF,
+ (BIT21| BIT20),
+ 0x06,
+ 0x07
+ );
+ }
+ }
+
+ //
+ // LPSS1 PWM 1
+ //
+ if (PchPlatformPolicy->LpssConfig->Pwm1Enabled == PchAcpiMode) {
+
+ LpssPciMmBase = MmPciAddress (
+ 0,
+ PchPlatformPolicy->BusNumber,
+ PCI_DEVICE_NUMBER_PCH_LPSS_PWM,
+ PCI_FUNCTION_NUMBER_PCH_LPSS_PWM1,
+ 0
+ );
+ LpssMmioBase0 = MmioRead32 ((UINTN) (LpssPciMmBase + R_PCH_LPSS_PWM_BAR)) & B_PCH_LPSS_PWM_BAR_BA;
+ ASSERT ((LpssMmioBase0 != 0) && (LpssMmioBase0 != B_PCH_LPSS_PWM_BAR_BA));
+ LpssMmioBase1 = MmioRead32 ((UINTN) (LpssPciMmBase + R_PCH_LPSS_PWM_BAR1)) & B_PCH_LPSS_PWM_BAR1_BA;
+ ASSERT ((LpssMmioBase1 != 0) && (LpssMmioBase1 != B_PCH_LPSS_PWM_BAR1_BA));
+ if (!IsSetS3BootScript) {
+
+ Data32Or = (UINT32) (B_PCH_LPSS_PWM_STSCMD_INTRDIS | B_PCH_LPSS_PWM_STSCMD_BME | B_PCH_LPSS_PWM_STSCMD_MSE);
+ Data32And = 0xFFFFFFFF;
+ MmioOr32 (
+ (UINTN) (LpssPciMmBase + R_PCH_LPSS_PWM_STSCMD),
+ Data32Or
+ );
+#ifndef FSP_FLAG
+ //
+ // Update BAR and length in ACPI table.
+ //
+ GlobalNvsArea->Area->PWM2Addr = LpssMmioBase0;
+ GlobalNvsArea->Area->PWM2Len = V_PCH_LPSS_PWM_BAR_SIZE;
+ GlobalNvsArea->Area->PWM21Addr = LpssMmioBase1;
+ GlobalNvsArea->Area->PWM21Len = V_PCH_LPSS_PWM_BAR1_SIZE;
+#endif
+
+ PchMsgBusAndThenOr32 (
+ 0xa0,
+ 0x250,
+ 0xFFFFFFFF,
+ (BIT21| BIT20),
+ 0x06,
+ 0x07
+ );
+
+ } else {
+ //
+ // Set S3 Boot Script
+ //
+ S3BootScriptSaveMemWrite (
+ S3BootScriptWidthUint32,
+ (UINTN) (LpssPciMmBase + R_PCH_LPSS_PWM_BAR),
+ 1,
+ &LpssMmioBase0
+ );
+ S3BootScriptSaveMemWrite (
+ S3BootScriptWidthUint32,
+ (UINTN) (LpssPciMmBase + R_PCH_LPSS_PWM_BAR1),
+ 1,
+ &LpssMmioBase1
+ );
+ Data32Or = (UINT32) (B_PCH_LPSS_PWM_STSCMD_INTRDIS | B_PCH_LPSS_PWM_STSCMD_BME | B_PCH_LPSS_PWM_STSCMD_MSE);
+ Data32And = 0xFFFFFFFF;
+ S3BootScriptSaveMemReadWrite (
+ EfiBootScriptWidthUint32,
+ (UINTN) (LpssPciMmBase + R_PCH_LPSS_PWM_STSCMD),
+ &Data32Or, // OR mask
+ &Data32And // AND mask
+ );
+ SetMsgBusAndThenOr32S3Item (
+ 0xa0,
+ 0x250,
+ 0xFFFFFFFF,
+ (BIT21| BIT20),
+ 0x06,
+ 0x07
+ );
+ }
+ }
+
+ //
+ // LPSS1 HS-UART 0
+ //
+ if (PchPlatformPolicy->LpssConfig->Hsuart0Enabled != PchDisabled) {
+
+ LpssPciMmBase = MmPciAddress (
+ 0,
+ PchPlatformPolicy->BusNumber,
+ PCI_DEVICE_NUMBER_PCH_LPSS_HSUART,
+ PCI_FUNCTION_NUMBER_PCH_LPSS_HSUART0,
+ 0
+ );
+ if (MmioRead32 (LpssPciMmBase) != 0xFFFFFFFF) {
+ LpssMmioBase0 = MmioRead32 ((UINTN) (LpssPciMmBase + R_PCH_LPSS_HSUART_BAR)) & B_PCH_LPSS_HSUART_BAR_BA;
+ ASSERT ((LpssMmioBase0 != 0) && (LpssMmioBase0 != B_PCH_LPSS_HSUART_BAR_BA));
+ LpssMmioBase1 = MmioRead32 ((UINTN) (LpssPciMmBase + R_PCH_LPSS_HSUART_BAR1)) & B_PCH_LPSS_HSUART_BAR1_BA;
+ ASSERT ((LpssMmioBase1 != 0) && (LpssMmioBase1 != B_PCH_LPSS_HSUART_BAR1_BA));
+ if (!IsSetS3BootScript) {
+
+ Data32Or = (UINT32) (B_PCH_LPSS_HSUART_STSCMD_INTRDIS | B_PCH_LPSS_HSUART_STSCMD_BME | B_PCH_LPSS_HSUART_STSCMD_MSE);
+ Data32And = 0xFFFFFFFF;
+ MmioOr32 (
+ (UINTN) (LpssPciMmBase + R_PCH_LPSS_HSUART_STSCMD),
+ Data32Or
+ );
+#ifndef FSP_FLAG
+ //
+ // Update BAR and length in ACPI table.
+ //
+ GlobalNvsArea->Area->UART1Addr = LpssMmioBase0;
+ GlobalNvsArea->Area->UART1Len = V_PCH_LPSS_HSUART_BAR_SIZE;
+ GlobalNvsArea->Area->UART11Addr = LpssMmioBase1;
+ GlobalNvsArea->Area->UART11Len = V_PCH_LPSS_HSUART_BAR1_SIZE;
+#endif
+
+ PchMsgBusAndThenOr32 (
+ 0xa0,
+ 0x258,
+ 0xFFFFFFFF,
+ (BIT21| BIT20),
+ 0x06,
+ 0x07
+ );
+ } else {
+ //
+ // Set S3 Boot Script
+ //
+ S3BootScriptSaveMemWrite (
+ S3BootScriptWidthUint32,
+ (UINTN) (LpssPciMmBase + R_PCH_LPSS_HSUART_BAR),
+ 1,
+ &LpssMmioBase0
+ );
+ S3BootScriptSaveMemWrite (
+ S3BootScriptWidthUint32,
+ (UINTN) (LpssPciMmBase + R_PCH_LPSS_HSUART_BAR1),
+ 1,
+ &LpssMmioBase1
+ );
+ Data32Or = (UINT32) (B_PCH_LPSS_HSUART_STSCMD_INTRDIS | B_PCH_LPSS_HSUART_STSCMD_BME | B_PCH_LPSS_HSUART_STSCMD_MSE);
+ Data32And = 0xFFFFFFFF;
+ S3BootScriptSaveMemReadWrite (
+ EfiBootScriptWidthUint32,
+ (UINTN) (LpssPciMmBase + R_PCH_LPSS_HSUART_STSCMD),
+ &Data32Or, // OR mask
+ &Data32And // AND mask
+ );
+ SetMsgBusAndThenOr32S3Item (
+ 0xa0,
+ 0x258,
+ 0xFFFFFFFF,
+ (BIT21| BIT20),
+ 0x06,
+ 0x07
+ );
+ }
+ }
+ }
+
+ //
+ // LPSS1 HS-UART 1
+ //
+ if (PchPlatformPolicy->LpssConfig->Hsuart1Enabled != PchDisabled) {
+
+ LpssPciMmBase = MmPciAddress (
+ 0,
+ PchPlatformPolicy->BusNumber,
+ PCI_DEVICE_NUMBER_PCH_LPSS_HSUART,
+ PCI_FUNCTION_NUMBER_PCH_LPSS_HSUART1,
+ 0
+ );
+ if (MmioRead32 (LpssPciMmBase) != 0xFFFFFFFF) {
+ LpssMmioBase0 = MmioRead32 ((UINTN) (LpssPciMmBase + R_PCH_LPSS_HSUART_BAR)) & B_PCH_LPSS_HSUART_BAR_BA;
+ ASSERT ((LpssMmioBase0 != 0) && (LpssMmioBase0 != B_PCH_LPSS_HSUART_BAR_BA));
+ LpssMmioBase1 = MmioRead32 ((UINTN) (LpssPciMmBase + R_PCH_LPSS_HSUART_BAR1)) & B_PCH_LPSS_HSUART_BAR1_BA;
+ ASSERT ((LpssMmioBase1 != 0) && (LpssMmioBase1 != B_PCH_LPSS_HSUART_BAR1_BA));
+ if (!IsSetS3BootScript) {
+
+ Data32Or = (UINT32) (B_PCH_LPSS_HSUART_STSCMD_INTRDIS | B_PCH_LPSS_HSUART_STSCMD_BME | B_PCH_LPSS_HSUART_STSCMD_MSE);
+ Data32And = 0xFFFFFFFF;
+ MmioOr32 (
+ (UINTN) (LpssPciMmBase + R_PCH_LPSS_HSUART_STSCMD),
+ (UINT32) (B_PCH_LPSS_HSUART_STSCMD_INTRDIS | B_PCH_LPSS_HSUART_STSCMD_BME | B_PCH_LPSS_HSUART_STSCMD_MSE)
+ );
+#ifndef FSP_FLAG
+ //
+ // Update BAR and length in ACPI table.
+ //
+ GlobalNvsArea->Area->UART2Addr = LpssMmioBase0;
+ GlobalNvsArea->Area->UART2Len = V_PCH_LPSS_HSUART_BAR_SIZE;
+ GlobalNvsArea->Area->UART21Addr = LpssMmioBase1;
+ GlobalNvsArea->Area->UART21Len = V_PCH_LPSS_HSUART_BAR1_SIZE;
+#endif
+
+ PchMsgBusAndThenOr32 (
+ 0xa0,
+ 0x260,
+ 0xFFFFFFFF,
+ (BIT21| BIT20),
+ 0x06,
+ 0x07
+ );
+ } else {
+ //
+ // Set S3 Boot Script
+ //
+ S3BootScriptSaveMemWrite (
+ S3BootScriptWidthUint32,
+ (UINTN) (LpssPciMmBase + R_PCH_LPSS_HSUART_BAR),
+ 1,
+ &LpssMmioBase0
+ );
+ S3BootScriptSaveMemWrite (
+ S3BootScriptWidthUint32,
+ (UINTN) (LpssPciMmBase + R_PCH_LPSS_HSUART_BAR1),
+ 1,
+ &LpssMmioBase1
+ );
+ Data32Or = (UINT32) (B_PCH_LPSS_HSUART_STSCMD_INTRDIS | B_PCH_LPSS_HSUART_STSCMD_BME | B_PCH_LPSS_HSUART_STSCMD_MSE);
+ Data32And = 0xFFFFFFFF;
+ S3BootScriptSaveMemReadWrite (
+ EfiBootScriptWidthUint32,
+ (UINTN) (LpssPciMmBase + R_PCH_LPSS_HSUART_STSCMD),
+ &Data32Or, // OR mask
+ &Data32And // AND mask
+ );
+ SetMsgBusAndThenOr32S3Item (
+ 0xa0,
+ 0x260,
+ 0xFFFFFFFF,
+ (BIT21| BIT20),
+ 0x06,
+ 0x07
+ );
+ }
+ }
+ }
+
+ //
+ // LPSS1 SPI
+ //
+ if (PchPlatformPolicy->LpssConfig->Spi1Enabled == PchAcpiMode) {
+
+ LpssPciMmBase = MmPciAddress (
+ 0,
+ PchPlatformPolicy->BusNumber,
+ PCI_DEVICE_NUMBER_PCH_LPSS_SPI,
+ PCI_FUNCTION_NUMBER_PCH_LPSS_SPI,
+ 0
+ );
+ LpssMmioBase0 = MmioRead32 ((UINTN) (LpssPciMmBase + R_PCH_LPSS_SPI_BAR)) & B_PCH_LPSS_SPI_BAR_BA;
+ ASSERT ((LpssMmioBase0 != 0) && (LpssMmioBase0 != B_PCH_LPSS_SPI_BAR_BA));
+ LpssMmioBase1 = MmioRead32 ((UINTN) (LpssPciMmBase + R_PCH_LPSS_SPI_BAR1)) & B_PCH_LPSS_SPI_BAR1_BA;
+ ASSERT ((LpssMmioBase1 != 0) && (LpssMmioBase1 != B_PCH_LPSS_SPI_BAR1_BA));
+ if (!IsSetS3BootScript) {
+
+ Data32Or = (UINT32) (B_PCH_LPSS_SPI_STSCMD_INTRDIS | B_PCH_LPSS_SPI_STSCMD_BME | B_PCH_LPSS_SPI_STSCMD_MSE);
+ Data32And = 0xFFFFFFFF;
+ MmioOr32 (
+ (UINTN) (LpssPciMmBase + R_PCH_LPSS_SPI_STSCMD),
+ Data32Or
+ );
+#ifndef FSP_FLAG
+ //
+ // Update BAR and length in ACPI table.
+ //
+ GlobalNvsArea->Area->SPIAddr = LpssMmioBase0;
+ GlobalNvsArea->Area->SPILen = V_PCH_LPSS_SPI_BAR_SIZE;
+ GlobalNvsArea->Area->SPI1Addr = LpssMmioBase1;
+ GlobalNvsArea->Area->SPI1Len = V_PCH_LPSS_SPI_BAR1_SIZE;
+#endif
+
+ PchMsgBusAndThenOr32 (
+ 0xa0,
+ 0x268,
+ 0xFFFFFFFF,
+ (BIT21| BIT20),
+ 0x06,
+ 0x07
+ );
+ } else {
+ //
+ // Set S3 Boot Script
+ //
+ S3BootScriptSaveMemWrite (
+ S3BootScriptWidthUint32,
+ (UINTN) (LpssPciMmBase + R_PCH_LPSS_SPI_BAR),
+ 1,
+ &LpssMmioBase0
+ );
+ S3BootScriptSaveMemWrite (
+ S3BootScriptWidthUint32,
+ (UINTN) (LpssPciMmBase + R_PCH_LPSS_SPI_BAR1),
+ 1,
+ &LpssMmioBase1
+ );
+ Data32Or = (UINT32) (B_PCH_LPSS_SPI_STSCMD_INTRDIS | B_PCH_LPSS_SPI_STSCMD_BME | B_PCH_LPSS_SPI_STSCMD_MSE);
+ Data32And = 0xFFFFFFFF;
+ S3BootScriptSaveMemReadWrite (
+ EfiBootScriptWidthUint32,
+ (UINTN) (LpssPciMmBase + R_PCH_LPSS_SPI_STSCMD),
+ &Data32Or, // OR mask
+ &Data32And // AND mask
+ );
+ SetMsgBusAndThenOr32S3Item (
+ 0xa0,
+ 0x268,
+ 0xFFFFFFFF,
+ (BIT21| BIT20),
+ 0x06,
+ 0x07
+ );
+ }
+ }
+
+ //
+ // LPSS1 SPI 2
+ //
+ if (PchPlatformPolicy->LpssConfig->Spi2Enabled == PchAcpiMode) {
+
+ LpssPciMmBase = MmPciAddress (
+ 0,
+ PchPlatformPolicy->BusNumber,
+ PCI_DEVICE_NUMBER_PCH_LPSS_SPI,
+ PCI_FUNCTION_NUMBER_PCH_LPSS_SPI2,
+ 0
+ );
+ LpssMmioBase0 = MmioRead32 ((UINTN) (LpssPciMmBase + R_PCH_LPSS_SPI_BAR)) & B_PCH_LPSS_SPI_BAR_BA;
+ ASSERT ((LpssMmioBase0 != 0) && (LpssMmioBase0 != B_PCH_LPSS_SPI_BAR_BA));
+ LpssMmioBase1 = MmioRead32 ((UINTN) (LpssPciMmBase + R_PCH_LPSS_SPI_BAR1)) & B_PCH_LPSS_SPI_BAR1_BA;
+ ASSERT ((LpssMmioBase1 != 0) && (LpssMmioBase1 != B_PCH_LPSS_SPI_BAR1_BA));
+ if (!IsSetS3BootScript) {
+
+ Data32Or = (UINT32) (B_PCH_LPSS_SPI_STSCMD_INTRDIS | B_PCH_LPSS_SPI_STSCMD_BME | B_PCH_LPSS_SPI_STSCMD_MSE);
+ Data32And = 0xFFFFFFFF;
+ MmioOr32 (
+ (UINTN) (LpssPciMmBase + R_PCH_LPSS_SPI_STSCMD),
+ Data32Or
+ );
+#ifndef FSP_FLAG
+ //
+ // Update BAR and length in ACPI table.
+ //
+ GlobalNvsArea->Area->SPI2Addr = LpssMmioBase0;
+ GlobalNvsArea->Area->SPI2Len = V_PCH_LPSS_SPI_BAR_SIZE;
+ GlobalNvsArea->Area->SPI21Addr = LpssMmioBase1;
+ GlobalNvsArea->Area->SPI21Len = V_PCH_LPSS_SPI_BAR1_SIZE;
+#endif
+
+ PchMsgBusAndThenOr32 (
+ 0xa0,
+ 0x270,
+ 0xFFFFFFFF,
+ (BIT21| BIT20),
+ 0x06,
+ 0x07
+ );
+ } else {
+ //
+ // Set S3 Boot Script
+ //
+ S3BootScriptSaveMemWrite (
+ S3BootScriptWidthUint32,
+ (UINTN) (LpssPciMmBase + R_PCH_LPSS_SPI_BAR),
+ 1,
+ &LpssMmioBase0
+ );
+ S3BootScriptSaveMemWrite (
+ S3BootScriptWidthUint32,
+ (UINTN) (LpssPciMmBase + R_PCH_LPSS_SPI_BAR1),
+ 1,
+ &LpssMmioBase1
+ );
+ Data32Or = (UINT32) (B_PCH_LPSS_SPI_STSCMD_INTRDIS | B_PCH_LPSS_SPI_STSCMD_BME | B_PCH_LPSS_SPI_STSCMD_MSE);
+ Data32And = 0xFFFFFFFF;
+ S3BootScriptSaveMemReadWrite (
+ EfiBootScriptWidthUint32,
+ (UINTN) (LpssPciMmBase + R_PCH_LPSS_SPI_STSCMD),
+ &Data32Or, // OR mask
+ &Data32And // AND mask
+ );
+ SetMsgBusAndThenOr32S3Item (
+ 0xa0,
+ 0x270,
+ 0xFFFFFFFF,
+ (BIT21| BIT20),
+ 0x06,
+ 0x07
+ );
+ }
+ }
+
+ //
+ // LPSS1 SPI 3
+ //
+ if (PchPlatformPolicy->LpssConfig->Spi3Enabled == PchAcpiMode) {
+
+ LpssPciMmBase = MmPciAddress (
+ 0,
+ PchPlatformPolicy->BusNumber,
+ PCI_DEVICE_NUMBER_PCH_LPSS_SPI,
+ PCI_FUNCTION_NUMBER_PCH_LPSS_SPI3,
+ 0
+ );
+ LpssMmioBase0 = MmioRead32 ((UINTN) (LpssPciMmBase + R_PCH_LPSS_SPI_BAR)) & B_PCH_LPSS_SPI_BAR_BA;
+ ASSERT ((LpssMmioBase0 != 0) && (LpssMmioBase0 != B_PCH_LPSS_SPI_BAR_BA));
+ LpssMmioBase1 = MmioRead32 ((UINTN) (LpssPciMmBase + R_PCH_LPSS_SPI_BAR1)) & B_PCH_LPSS_SPI_BAR1_BA;
+ ASSERT ((LpssMmioBase1 != 0) && (LpssMmioBase1 != B_PCH_LPSS_SPI_BAR1_BA));
+ if (!IsSetS3BootScript) {
+
+ Data32Or = (UINT32) (B_PCH_LPSS_SPI_STSCMD_INTRDIS | B_PCH_LPSS_SPI_STSCMD_BME | B_PCH_LPSS_SPI_STSCMD_MSE);
+ Data32And = 0xFFFFFFFF;
+ MmioOr32 (
+ (UINTN) (LpssPciMmBase + R_PCH_LPSS_SPI_STSCMD),
+ Data32Or
+ );
+#ifndef FSP_FLAG
+ //
+ // Update BAR and length in ACPI table.
+ //
+ GlobalNvsArea->Area->SPI3Addr = LpssMmioBase0;
+ GlobalNvsArea->Area->SPI3Len = V_PCH_LPSS_SPI_BAR_SIZE;
+ GlobalNvsArea->Area->SPI31Addr = LpssMmioBase1;
+ GlobalNvsArea->Area->SPI31Len = V_PCH_LPSS_SPI_BAR1_SIZE;
+#endif
+
+ PchMsgBusAndThenOr32 (
+ 0xa0,
+ 0x278,
+ 0xFFFFFFFF,
+ (BIT21| BIT20),
+ 0x06,
+ 0x07
+ );
+ } else {
+ //
+ // Set S3 Boot Script
+ //
+ S3BootScriptSaveMemWrite (
+ S3BootScriptWidthUint32,
+ (UINTN) (LpssPciMmBase + R_PCH_LPSS_SPI_BAR),
+ 1,
+ &LpssMmioBase0
+ );
+ S3BootScriptSaveMemWrite (
+ S3BootScriptWidthUint32,
+ (UINTN) (LpssPciMmBase + R_PCH_LPSS_SPI_BAR1),
+ 1,
+ &LpssMmioBase1
+ );
+ Data32Or = (UINT32) (B_PCH_LPSS_SPI_STSCMD_INTRDIS | B_PCH_LPSS_SPI_STSCMD_BME | B_PCH_LPSS_SPI_STSCMD_MSE);
+ Data32And = 0xFFFFFFFF;
+ S3BootScriptSaveMemReadWrite (
+ EfiBootScriptWidthUint32,
+ (UINTN) (LpssPciMmBase + R_PCH_LPSS_SPI_STSCMD),
+ &Data32Or, // OR mask
+ &Data32And // AND mask
+ );
+ SetMsgBusAndThenOr32S3Item (
+ 0xa0,
+ 0x278,
+ 0xFFFFFFFF,
+ (BIT21| BIT20),
+ 0x06,
+ 0x07
+ );
+ }
+ }
+
+ DEBUG ((EFI_D_INFO, "ConfigureLpssAtBoot() End\n"));
+
+ return EFI_SUCCESS;
+}
diff --git a/ChvRefCodePkg/CherryViewSoc/SouthCluster/PchInit/Dxe/PchSata.c b/ChvRefCodePkg/CherryViewSoc/SouthCluster/PchInit/Dxe/PchSata.c new file mode 100644 index 0000000000..a6b2f1550a --- /dev/null +++ b/ChvRefCodePkg/CherryViewSoc/SouthCluster/PchInit/Dxe/PchSata.c @@ -0,0 +1,243 @@ +/** @file
+ Configures PCH SATA Controller.
+
+ Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifdef SATA_SUPPORT
+
+#include "PchInit.h"
+
+/**
+ Do any final initialization on SATA controller
+
+ @param[in] PchPlatformPolicy The PCH Platform Policy protocol instance
+ @param[in] IsSetS3BootScript Is this function called for S3 boot script save
+
+ @retval EFI_SUCCESS The function completed successfully
+**/
+EFI_STATUS
+ConfigureSataAtBoot (
+ IN DXE_PCH_PLATFORM_POLICY_PROTOCOL *PchPlatformPolicy,
+ IN BOOLEAN IsSetS3BootScript
+ )
+{
+ UINT8 Index;
+ UINT32 AhciBar;
+ UINTN PciD19F0RegBase;
+ UINT16 SataModeSelect;
+ UINT32 PxSctlDet;
+ UINT32 PxCmdSud;
+ UINT32 OrgCmdWord;
+ UINT32 Data32And;
+ UINT32 Data32Or;
+
+ DEBUG ((EFI_D_INFO, "ConfigureSataAtBoot() Start\n"));
+ //
+ // eSATA port support only up to Gen2
+ //
+ PciD19F0RegBase = MmPciAddress (0, PchPlatformPolicy->BusNumber, PCI_DEVICE_NUMBER_PCH_SATA, PCI_FUNCTION_NUMBER_PCH_SATA, 0);
+ //
+ // Make sure SATA device exists.
+ //
+ if (MmioRead16 (PciD19F0RegBase + R_PCH_SATA_ID) != 0xFFFF) {
+ SataModeSelect = MmioRead16 (PciD19F0RegBase + R_PCH_SATA_MAP) & B_PCH_SATA_MAP_SMS_MASK;
+ if ((SataModeSelect == V_PCH_SATA_MAP_SMS_AHCI) ||
+ (SataModeSelect == V_PCH_SATA_MAP_SMS_RAID)) {
+ AhciBar = MmioRead32 (PciD19F0RegBase + R_PCH_SATA_ABAR) & B_PCH_SATA_ABAR_BA;
+ //
+ // Make sure the AhciBar is valid.
+ //
+ if ((AhciBar != 0x00000000) && (AhciBar != B_PCH_SATA_ABAR_BA)) {
+ //
+ // Keep original CMD word, and enable MSE
+ //
+ OrgCmdWord = MmioRead32 (PciD19F0RegBase + R_PCH_SATA_COMMAND);
+ if ((OrgCmdWord & B_PCH_SATA_COMMAND_MSE) == 0) {
+ Data32And = (UINT32) 0xFFFFFFFF;
+ Data32Or = (UINT32) B_PCH_SATA_COMMAND_MSE;
+ if (!IsSetS3BootScript) {
+ MmioOr32 ((PciD19F0RegBase + R_PCH_SATA_COMMAND), Data32Or);
+ } else {
+ //
+ // Set S3 Boot Script
+ //
+ S3BootScriptSaveMemReadWrite (
+ EfiBootScriptWidthUint32,
+ (UINTN) (PciD19F0RegBase + R_PCH_SATA_COMMAND),
+ &Data32Or, /// Data to be ORed
+ &Data32And /// Data to be ANDed
+ );
+ }
+ }
+ for (Index = 0; Index < PCH_AHCI_MAX_PORTS; Index++) {
+ if (PchPlatformPolicy->SataConfig->PortSettings[Index].External == PCH_DEVICE_ENABLE) {
+ PxSctlDet = MmioRead32(AhciBar + (R_PCH_SATA_AHCI_P0SCTL + (0x80 * Index))) & B_PCH_SATA_AHCI_PXSCTL_DET;
+ PxCmdSud = MmioRead32(AhciBar + (R_PCH_SATA_AHCI_P0CMD + (0x80 * Index))) & B_PCH_SATA_AHCI_PxCMD_SUD;
+ //
+ // Limit speed to Gen2
+ //
+ Data32And = (UINT32)~(B_PCH_SATA_AHCI_PXSCTL_SPD);
+ Data32Or = (UINT32) V_PCH_SATA_AHCI_PXSCTL_SPD_2;
+ if (!IsSetS3BootScript) {
+ MmioAndThenOr32 (
+ (UINTN) (AhciBar + (R_PCH_SATA_AHCI_P0SCTL + (0x80 * Index))),
+ Data32And,
+ Data32Or
+ );
+ } else {
+ //
+ // Set S3 Boot Script
+ //
+ S3BootScriptSaveMemReadWrite (
+ EfiBootScriptWidthUint32,
+ (UINTN) (AhciBar + (R_PCH_SATA_AHCI_P0SCTL + (0x80 * Index))),
+ &Data32Or, /// Data to be ORed
+ &Data32And /// Data to be ANDed
+ );
+ }
+ //
+ // If port is not offline, and it's spin up, need to port reset.
+ // After port reset, clear the SERR.
+ // - Set DET=1, and then set DET=0.
+ // - Finally, set FRE=1.
+ //
+ if ((PxSctlDet == V_PCH_SATA_AHCI_PXSCTL_DET_0) &&
+ (PxCmdSud == B_PCH_SATA_AHCI_PxCMD_SUD))
+ {
+ if (!IsSetS3BootScript) {
+ MmioOr32 (AhciBar + (R_PCH_SATA_AHCI_P0SCTL + (0x80 * Index)), V_PCH_SATA_AHCI_PXSCTL_DET_1);
+ PchPmTimerStall (1000);
+ MmioAnd32(AhciBar + (R_PCH_SATA_AHCI_P0SCTL + (0x80 * Index)), (UINT32) ~(B_PCH_SATA_AHCI_PXSCTL_DET));
+ MmioWrite32 (AhciBar + (R_PCH_SATA_AHCI_P0SERR + (0x80 * Index)), (UINT32)~0u);
+ MmioOr32 (AhciBar + (R_PCH_SATA_AHCI_P0CMD + (0x80 * Index)), B_PCH_SATA_AHCI_PxCMD_FRE);
+ } else {
+ //
+ // Set S3 Boot Script
+ //
+ Data32And = (UINT32) 0xFFFFFFFF;
+ Data32Or = (UINT32) V_PCH_SATA_AHCI_PXSCTL_DET_1;
+ S3BootScriptSaveMemReadWrite (
+ EfiBootScriptWidthUint32,
+ (UINTN) (AhciBar + (R_PCH_SATA_AHCI_P0SCTL + (0x80 * Index))),
+ &Data32Or, /// Data to be ORed
+ &Data32And /// Data to be ANDed
+ );
+ S3BootScriptSaveStall (1000);
+ Data32And = (UINT32) ~(B_PCH_SATA_AHCI_PXSCTL_DET);
+ Data32Or = (UINT32) 0x00000000;
+ S3BootScriptSaveMemReadWrite (
+ EfiBootScriptWidthUint32,
+ (UINTN) (AhciBar + (R_PCH_SATA_AHCI_P0SCTL + (0x80 * Index))),
+ &Data32Or, /// Data to be ORed
+ &Data32And /// Data to be ANDed
+ );
+ Data32And = (UINT32) 0xFFFFFFFF;
+ Data32Or = (UINT32) 0xFFFFFFFF;
+ S3BootScriptSaveMemReadWrite (
+ EfiBootScriptWidthUint32,
+ (UINTN) (AhciBar + (R_PCH_SATA_AHCI_P0SERR + (0x80 * Index))),
+ &Data32Or, /// Data to be ORed
+ &Data32And /// Data to be ANDed
+ );
+ Data32And = (UINT32) 0xFFFFFFFF;
+ Data32Or = (UINT32) B_PCH_SATA_AHCI_PxCMD_FRE;
+ S3BootScriptSaveMemReadWrite (
+ EfiBootScriptWidthUint32,
+ (UINTN) (AhciBar + (R_PCH_SATA_AHCI_P0CMD + (0x80 * Index))),
+ &Data32Or, /// Data to be ORed
+ &Data32And /// Data to be ANDed
+ );
+ }
+ }
+ //
+ // If port is offline, and it's not spin up, meets the power bug.
+ // Need to do the W/A to spin up the port and then spin down.
+ // Then entering back to offline and listen.
+ // - Set DET=0, SUD=1, and then set SUD=0, DET=4.
+ //
+ if ((PxSctlDet == V_PCH_SATA_AHCI_PXSCTL_DET_4) &&
+ (PxCmdSud == 0))
+ {
+ if (!IsSetS3BootScript) {
+ MmioAnd32(AhciBar + (R_PCH_SATA_AHCI_P0SCTL + (0x80 * Index)), (UINT32) ~(B_PCH_SATA_AHCI_PXSCTL_DET));
+ MmioOr32 (AhciBar + (R_PCH_SATA_AHCI_P0CMD + (0x80 * Index)), B_PCH_SATA_AHCI_PxCMD_SUD);
+ PchPmTimerStall (1000);
+ MmioAnd32(AhciBar + (R_PCH_SATA_AHCI_P0CMD + (0x80 * Index)), (UINT32) ~(B_PCH_SATA_AHCI_PxCMD_SUD));
+ MmioOr32 (AhciBar + (R_PCH_SATA_AHCI_P0SCTL + (0x80 * Index)), V_PCH_SATA_AHCI_PXSCTL_DET_4);
+ } else {
+ //
+ // Set S3 Boot Script
+ //
+ Data32And = (UINT32) ~(B_PCH_SATA_AHCI_PXSCTL_DET);
+ Data32Or = (UINT32) 0x00000000;
+ S3BootScriptSaveMemReadWrite (
+ EfiBootScriptWidthUint32,
+ (UINTN) (AhciBar + (R_PCH_SATA_AHCI_P0SCTL + (0x80 * Index))),
+ &Data32Or, /// Data to be ORed
+ &Data32And /// Data to be ANDed
+ );
+ Data32And = (UINT32) 0xFFFFFFFF;
+ Data32Or = (UINT32) B_PCH_SATA_AHCI_PxCMD_SUD;
+ S3BootScriptSaveMemReadWrite (
+ EfiBootScriptWidthUint32,
+ (UINTN) (AhciBar + (R_PCH_SATA_AHCI_P0CMD + (0x80 * Index))),
+ &Data32Or, /// Data to be ORed
+ &Data32And /// Data to be ANDed
+ );
+ S3BootScriptSaveStall (1000);
+ Data32And = (UINT32) ~(B_PCH_SATA_AHCI_PxCMD_SUD);
+ Data32Or = (UINT32) 0x00000000;
+ S3BootScriptSaveMemReadWrite (
+ EfiBootScriptWidthUint32,
+ (UINTN) (AhciBar + (R_PCH_SATA_AHCI_P0CMD + (0x80 * Index))),
+ &Data32Or, /// Data to be ORed
+ &Data32And /// Data to be ANDed
+ );
+ Data32And = (UINT32) 0xFFFFFFFF;
+ Data32Or = (UINT32) V_PCH_SATA_AHCI_PXSCTL_DET_4;
+ S3BootScriptSaveMemReadWrite (
+ EfiBootScriptWidthUint32,
+ (UINTN) (AhciBar + (R_PCH_SATA_AHCI_P0SCTL + (0x80 * Index))),
+ &Data32Or, /// Data to be ORed
+ &Data32And /// Data to be ANDed
+ );
+ }
+ }
+ }
+ }
+ //
+ // Restore original CMD word.
+ //
+ if ((OrgCmdWord & B_PCH_SATA_COMMAND_MSE) == 0) {
+ Data32And = (UINT32) 0xFFFFFFFF;
+ Data32Or = (UINT32) OrgCmdWord;
+ if (!IsSetS3BootScript) {
+ MmioWrite32 ((PciD19F0RegBase + R_PCH_SATA_COMMAND), Data32Or);
+ } else {
+ S3BootScriptSaveMemReadWrite (
+ EfiBootScriptWidthUint32,
+ (UINTN) (PciD19F0RegBase + R_PCH_SATA_COMMAND),
+ &Data32Or, /// Data to be ORed
+ &Data32And /// Data to be ANDed
+ );
+ }
+ }
+ } // AhciBar is vaild
+ } // SATA mode is AHCI or RAID
+ } // if D19F0 is existed
+
+ DEBUG ((EFI_D_INFO, "ConfigureSataAtBoot() End\n"));
+ return EFI_SUCCESS;
+}
+
+#endif
diff --git a/ChvRefCodePkg/CherryViewSoc/SouthCluster/PchInit/Dxe/PchScc.c b/ChvRefCodePkg/CherryViewSoc/SouthCluster/PchInit/Dxe/PchScc.c new file mode 100644 index 0000000000..891c8ea72b --- /dev/null +++ b/ChvRefCodePkg/CherryViewSoc/SouthCluster/PchInit/Dxe/PchScc.c @@ -0,0 +1,361 @@ +/** @file
+ Initializes PCH SCC Devices.
+
+ Copyright (c) 2012 - 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "PchInit.h"
+#include <Protocol/GlobalNvsArea.h>
+#include <Library/TimerLib.h>
+
+/**
+ Hide PCI config space of SCC devices and do any final initialization
+
+ @param[in] PchPlatformPolicy The PCH Platform Policy protocol instance
+ @param[in] IsSetS3BootScript Is this function called for S3 boot script save
+
+ @retval EFI_SUCCESS The function completed successfully
+**/
+EFI_STATUS
+ConfigureSccAtBoot (
+ IN DXE_PCH_PLATFORM_POLICY_PROTOCOL *PchPlatformPolicy,
+ IN BOOLEAN IsSetS3BootScript
+ )
+{
+ UINTN SccPciMmBase;
+ UINT32 SccMmioBase0;
+ UINT32 SccMmioBase1;
+ UINT32 Data32And;
+ UINT32 Data32Or;
+ EFI_STATUS Status;
+#ifndef FSP_FLAG
+ EFI_GLOBAL_NVS_AREA_PROTOCOL *GlobalNvsArea;
+#endif
+ UINTN PciD31F0RegBase;
+ UINT32 IoBase;
+ UINT16 Timeout;
+
+ DEBUG ((EFI_D_INFO, "ConfigureSccAtBoot() Start\n"));
+
+ //
+ // Initialize Variables
+ //
+ SccPciMmBase = 0;
+ SccMmioBase0 = 0;
+ SccMmioBase1 = 0;
+ Data32And = 0;
+ Data32Or = 0;
+ Status = EFI_SUCCESS;
+#ifndef FSP_FLAG
+ //
+ // Update SCC devices ACPI variables
+ //
+ Status = gBS->LocateProtocol (
+ &gEfiGlobalNvsAreaProtocolGuid,
+ NULL,
+ (VOID **) &GlobalNvsArea
+ );
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+#endif
+ //
+ // SCC eMMC
+ //
+ if (PchPlatformPolicy->SccConfig->eMMCEnabled != PchDisabled) {
+
+ SccPciMmBase = MmPciAddress (0,
+ DEFAULT_PCI_BUS_NUMBER_PCH,
+ PCI_DEVICE_NUMBER_PCH_SCC_SDIO_0,
+ PCI_FUNCTION_NUMBER_PCH_SCC_SDIO,
+ 0
+ );
+ if (MmioRead32 (SccPciMmBase) != 0xFFFFFFFF) {
+ SccMmioBase0 = MmioRead32 ((UINTN) (SccPciMmBase + R_PCH_SCC_SDIO_BAR)) & B_PCH_SCC_SDIO_BAR_BA;
+ ASSERT ((SccMmioBase0 != 0) && (SccMmioBase0 != B_PCH_SCC_SDIO_BAR_BA));
+ if (!IsSetS3BootScript) {
+
+ Data32Or = (UINT32) (B_PCH_SCC_SDIO_STSCMD_INTRDIS | B_PCH_SCC_SDIO_STSCMD_BME | B_PCH_SCC_SDIO_STSCMD_MSE);
+ Data32And = 0xFFFFFFFF;
+ MmioOr32 (
+ (UINTN) (SccPciMmBase + R_PCH_SCC_SDIO_STSCMD),
+ Data32Or
+ );
+#ifndef FSP_FLAG
+ //
+ // Update BAR and length in ACPI table.
+ //
+ GlobalNvsArea->Area->eMMCAddr = SccMmioBase0;
+ GlobalNvsArea->Area->eMMCLen = V_PCH_SCC_SDIO_BAR_SIZE;
+#endif
+
+ PchMsgBusAndThenOr32 (
+ PCH_SCC_EP_PORT_ID,
+ R_PCH_SCC_EP_PCICFGCTR1,
+ 0xFFFFFFFF,
+ (B_PCH_SCC_EP_PCICFGCTR1_ACPI_INT_EN1 | B_PCH_SCC_EP_PCICFGCTR1_PCI_CFG_DIS1),
+ PCH_SCC_EP_PRIVATE_READ_OPCODE,
+ PCH_SCC_EP_PRIVATE_WRITE_OPCODE
+ );
+ } else {
+ //
+ // Set S3 Boot Script
+ //
+ S3BootScriptSaveMemWrite (
+ S3BootScriptWidthUint32,
+ (UINTN) (SccPciMmBase + R_PCH_SCC_SDIO_BAR),
+ 1,
+ &SccMmioBase0
+ );
+ Data32Or = (UINT32) (B_PCH_SCC_SDIO_STSCMD_INTRDIS | B_PCH_SCC_SDIO_STSCMD_BME | B_PCH_SCC_SDIO_STSCMD_MSE);
+ Data32And = 0xFFFFFFFF;
+ S3BootScriptSaveMemReadWrite (
+ EfiBootScriptWidthUint32,
+ (UINTN) (SccPciMmBase + R_PCH_SCC_SDIO_STSCMD),
+ &Data32Or, // OR mask
+ &Data32And // AND mask
+ );
+ SetMsgBusAndThenOr32S3Item (
+ PCH_SCC_EP_PORT_ID,
+ R_PCH_SCC_EP_PCICFGCTR1,
+ 0xFFFFFFFF,
+ (B_PCH_SCC_EP_PCICFGCTR1_ACPI_INT_EN1 | B_PCH_SCC_EP_PCICFGCTR1_PCI_CFG_DIS1),
+ PCH_SCC_EP_PRIVATE_READ_OPCODE,
+ PCH_SCC_EP_PRIVATE_WRITE_OPCODE
+ );
+ }
+ }
+ }
+
+ //
+ // SCC SDIO
+ //
+ if (PchPlatformPolicy->SccConfig->SdioEnabled != PchDisabled) {
+
+ SccPciMmBase = MmPciAddress (0,
+ DEFAULT_PCI_BUS_NUMBER_PCH,
+ PCI_DEVICE_NUMBER_PCH_SCC_SDIO_1,
+ PCI_FUNCTION_NUMBER_PCH_SCC_SDIO,
+ 0
+ );
+ if (MmioRead32 (SccPciMmBase) != 0xFFFFFFFF) {
+ SccMmioBase0 = MmioRead32 ((UINTN) (SccPciMmBase + R_PCH_SCC_SDIO_BAR)) & B_PCH_SCC_SDIO_BAR_BA;
+ ASSERT ((SccMmioBase0 != 0) && (SccMmioBase0 != B_PCH_SCC_SDIO_BAR_BA));
+ if (!IsSetS3BootScript) {
+
+ Data32Or = (UINT32) (B_PCH_SCC_SDIO_STSCMD_INTRDIS | B_PCH_SCC_SDIO_STSCMD_BME | B_PCH_SCC_SDIO_STSCMD_MSE);
+ Data32And = 0xFFFFFFFF;
+ MmioOr32 (
+ (UINTN) (SccPciMmBase + R_PCH_SCC_SDIO_STSCMD),
+ Data32Or
+ );
+#ifndef FSP_FLAG
+ //
+ // Update BAR and length in ACPI table.
+ //
+ GlobalNvsArea->Area->SDIOAddr = SccMmioBase0;
+ GlobalNvsArea->Area->SDIOLen = V_PCH_SCC_SDIO_BAR_SIZE;
+#endif
+
+ PchMsgBusAndThenOr32 (
+ PCH_SCC_EP_PORT_ID,
+ R_PCH_SCC_EP_PCICFGCTR3,
+ 0xFFFFFFFF,
+ (B_PCH_SCC_EP_PCICFGCTR3_ACPI_INT_EN1 | B_PCH_SCC_EP_PCICFGCTR3_PCI_CFG_DIS1),
+ PCH_SCC_EP_PRIVATE_READ_OPCODE,
+ PCH_SCC_EP_PRIVATE_WRITE_OPCODE
+ );
+ } else {
+ ///
+ /// Set S3 Boot Script
+ ///
+ S3BootScriptSaveMemWrite (
+ S3BootScriptWidthUint32,
+ (UINTN) (SccPciMmBase + R_PCH_SCC_SDIO_BAR),
+ 1,
+ &SccMmioBase0
+ );
+ Data32Or = (UINT32) (B_PCH_SCC_SDIO_STSCMD_INTRDIS | B_PCH_SCC_SDIO_STSCMD_BME | B_PCH_SCC_SDIO_STSCMD_MSE);
+ Data32And = 0xFFFFFFFF;
+ S3BootScriptSaveMemReadWrite (
+ EfiBootScriptWidthUint32,
+ (UINTN) (SccPciMmBase + R_PCH_SCC_SDIO_STSCMD),
+ &Data32Or, // OR mask
+ &Data32And // AND mask
+ );
+ SetMsgBusAndThenOr32S3Item (
+ PCH_SCC_EP_PORT_ID,
+ R_PCH_SCC_EP_PCICFGCTR3,
+ 0xFFFFFFFF,
+ (B_PCH_SCC_EP_PCICFGCTR3_ACPI_INT_EN1 | B_PCH_SCC_EP_PCICFGCTR3_PCI_CFG_DIS1),
+ PCH_SCC_EP_PRIVATE_READ_OPCODE,
+ PCH_SCC_EP_PRIVATE_WRITE_OPCODE
+ );
+ }
+ }
+ }
+
+ //
+ // SCC SD Card
+ //
+ if (PchPlatformPolicy->SccConfig->SdcardEnabled != PchDisabled) {
+ SccPciMmBase = MmPciAddress (0,
+ DEFAULT_PCI_BUS_NUMBER_PCH,
+ PCI_DEVICE_NUMBER_PCH_SCC_SDIO_2,
+ PCI_FUNCTION_NUMBER_PCH_SCC_SDIO,
+ 0
+ );
+ if (MmioRead32 (SccPciMmBase) != 0xFFFFFFFF) {
+ SccMmioBase0 = MmioRead32 ((UINTN) (SccPciMmBase + R_PCH_SCC_SDIO_BAR)) & B_PCH_SCC_SDIO_BAR_BA;
+ ASSERT ((SccMmioBase0 != 0) && (SccMmioBase0 != B_PCH_SCC_SDIO_BAR_BA));
+ //
+ // SDCard RCOMP - Stage 2
+ // Stage 1 done in PchInitPeim.c PchInitialize ()
+ // 1. Disable 1.8V buffer mode
+ // 2. Memory space enable
+ // 3. Wait for the card detect level, card state stable and card inserted.
+ // 4. Turn on 3.3V power.
+ // 5. Wait 5ms for power to stable.
+ // 6. Enable SDCard RCOMP to start calibration
+ // 7. Wait for calibration done.
+ // 8. Turn off power
+ // 9. Turn off card insertion simulation
+ //
+ PciD31F0RegBase = MmPciAddress (
+ 0,
+ PchPlatformPolicy->BusNumber,
+ PCI_DEVICE_NUMBER_PCH_LPC,
+ PCI_FUNCTION_NUMBER_PCH_LPC,
+ 0
+ );
+ IoBase = MmioRead32 (PciD31F0RegBase + R_PCH_LPC_IO_BASE) & B_PCH_LPC_IO_BASE_BAR;
+ Timeout = 3000;
+ if (!IsSetS3BootScript) {
+ if ((MmioRead32 ((UINTN) (IoBase + R_PCH_CFIO_SOUTHEAST + 0x1180)) & BIT31) != BIT31) {
+ MmioAnd32 (((UINTN) (IoBase + R_PCH_CFIO_SOUTHEAST + 0x1194)), (UINT32)~BIT21);
+ MmioOr32 ((UINTN) (SccPciMmBase + R_PCH_SCC_SDIO_STSCMD), (UINT32) (B_PCH_SCC_SDIO_STSCMD_MSE));
+ while (((MmioRead32 ((UINTN) (SccMmioBase0 + R_PCH_SCC_SDIO_MEM_PRE_STATE)) & 0x70000) != 0x70000) && Timeout != 0) {
+ MicroSecondDelay (1000);
+ Timeout--;
+ }
+ MmioWrite8 (
+ (UINTN) (SccMmioBase0 + R_PCH_SCC_SDIO_MEM_PWR_CTL),
+ (UINT8) (V_PCH_SCC_SDIO_MEM_PWR_CTL_SD_VOLSEL_3P3 | B_PCH_SCC_SDIO_MEM_PWR_CTL_SD_PWR)
+ );
+ PchPmTimerStall (5000);
+ MmioOr32 (((UINTN) (IoBase + R_PCH_CFIO_SOUTHEAST + 0x1180)), (UINT32) BIT31);
+ PchPmTimerStall (10);
+ MmioOr32 (((UINTN) (IoBase + R_PCH_CFIO_SOUTHEAST + 0x1180)), (UINT32) BIT30);
+ PchPmTimerStall (10);
+ MmioAnd32 (((UINTN) (IoBase + R_PCH_CFIO_SOUTHEAST + 0x1180)), (UINT32)~BIT30);
+ MmioWrite8 ((UINTN) (SccMmioBase0 + R_PCH_SCC_SDIO_MEM_PWR_CTL), (UINT8) 0x00);
+ MmioWrite8 ((UINTN) (SccMmioBase0 + R_PCH_SCC_SDIO_MEM_HOST_CTL), (UINT8) 0x00);
+ }
+ } else {
+ //
+ // Set S3 Boot Script
+ //
+ S3BootScriptSaveMemWrite (
+ S3BootScriptWidthUint32,
+ (UINTN) (SccPciMmBase + R_PCH_SCC_SDIO_BAR),
+ 1,
+ &SccMmioBase0
+ );
+ Data32Or = (UINT32) (B_PCH_SCC_SDIO_STSCMD_MSE);
+ Data32And = 0xFFFFFFFF;
+ S3BootScriptSaveMemReadWrite (
+ EfiBootScriptWidthUint32,
+ (UINTN) (SccPciMmBase + R_PCH_SCC_SDIO_STSCMD),
+ &Data32Or, // OR mask
+ &Data32And // AND mask
+ );
+ Data32Or = (UINT32) (0x00);
+ Data32And = 0xFFFFFF00;
+ S3BootScriptSaveMemReadWrite (
+ EfiBootScriptWidthUint32,
+ (UINTN) (SccMmioBase0 + 0x28),
+ &Data32Or, // OR mask
+ &Data32And // AND mask
+ );
+ }
+ }
+ }
+
+ if (PchPlatformPolicy->SccConfig->SdcardEnabled != PchDisabled) {
+ SccPciMmBase = MmPciAddress (0,
+ DEFAULT_PCI_BUS_NUMBER_PCH,
+ PCI_DEVICE_NUMBER_PCH_SCC_SDIO_2,
+ PCI_FUNCTION_NUMBER_PCH_SCC_SDIO,
+ 0
+ );
+ if (MmioRead32 (SccPciMmBase) != 0xFFFFFFFF) {
+ SccMmioBase0 = MmioRead32 ((UINTN) (SccPciMmBase + R_PCH_SCC_SDIO_BAR)) & B_PCH_SCC_SDIO_BAR_BA;
+ ASSERT ((SccMmioBase0 != 0) && (SccMmioBase0 != B_PCH_SCC_SDIO_BAR_BA));
+
+ if (!IsSetS3BootScript) {
+
+ Data32Or = (UINT32) (B_PCH_SCC_SDIO_STSCMD_INTRDIS | B_PCH_SCC_SDIO_STSCMD_BME | B_PCH_SCC_SDIO_STSCMD_MSE);
+ Data32And = 0xFFFFFFFF;
+ MmioOr32 (
+ (UINTN) (SccPciMmBase + R_PCH_SCC_SDIO_STSCMD),
+ Data32Or
+ );
+#ifndef FSP_FLAG
+ //
+ // Update BAR and length in ACPI table.
+ //
+ GlobalNvsArea->Area->SDCardAddr = SccMmioBase0;
+ GlobalNvsArea->Area->SDCardLen = V_PCH_SCC_SDIO_BAR_SIZE;
+#endif
+
+ PchMsgBusAndThenOr32 (
+ PCH_SCC_EP_PORT_ID,
+ R_PCH_SCC_EP_PCICFGCTR2,
+ 0xFFFFFFFF,
+ (B_PCH_SCC_EP_PCICFGCTR2_ACPI_INT_EN1 | B_PCH_SCC_EP_PCICFGCTR2_PCI_CFG_DIS1),
+ PCH_SCC_EP_PRIVATE_READ_OPCODE,
+ PCH_SCC_EP_PRIVATE_WRITE_OPCODE
+ );
+ } else {
+ //
+ // Set S3 Boot Script
+ //
+ S3BootScriptSaveMemWrite (
+ S3BootScriptWidthUint32,
+ (UINTN) (SccPciMmBase + R_PCH_SCC_SDIO_BAR),
+ 1,
+ &SccMmioBase0
+ );
+ Data32Or = (UINT32) (B_PCH_SCC_SDIO_STSCMD_INTRDIS | B_PCH_SCC_SDIO_STSCMD_BME | B_PCH_SCC_SDIO_STSCMD_MSE);
+ Data32And = 0xFFFFFFFF;
+ S3BootScriptSaveMemReadWrite (
+ EfiBootScriptWidthUint32,
+ (UINTN) (SccPciMmBase + R_PCH_SCC_SDIO_STSCMD),
+ &Data32Or, // OR mask
+ &Data32And // AND mask
+ );
+ SetMsgBusAndThenOr32S3Item (
+ PCH_SCC_EP_PORT_ID,
+ R_PCH_SCC_EP_PCICFGCTR2,
+ 0xFFFFFFFF,
+ (B_PCH_SCC_EP_PCICFGCTR2_ACPI_INT_EN1 | B_PCH_SCC_EP_PCICFGCTR2_PCI_CFG_DIS1),
+ PCH_SCC_EP_PRIVATE_READ_OPCODE,
+ PCH_SCC_EP_PRIVATE_WRITE_OPCODE
+ );
+ }
+ }
+ }
+
+ DEBUG ((EFI_D_INFO, "ConfigureSccAtBoot() End\n"));
+
+ return EFI_SUCCESS;
+}
diff --git a/ChvRefCodePkg/CherryViewSoc/SouthCluster/PchInit/Dxe/PchUsbOtg.c b/ChvRefCodePkg/CherryViewSoc/SouthCluster/PchInit/Dxe/PchUsbOtg.c new file mode 100644 index 0000000000..856c28500e --- /dev/null +++ b/ChvRefCodePkg/CherryViewSoc/SouthCluster/PchInit/Dxe/PchUsbOtg.c @@ -0,0 +1,140 @@ +/** @file
+ Initializes PCH USB On-The-Go Device.
+
+ Copyright (c) 2012 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "PchInit.h"
+
+/**
+ Hide PCI config space of OTG device and do any final initialization.
+
+ @param[in] PchPlatformPolicy The PCH Platform Policy protocol instance
+ @param[in] IsSetS3BootScript Is this function called for S3 boot script save
+
+ @retval EFI_SUCCESS The function completed successfully
+**/
+EFI_STATUS
+ConfigureOtgAtBoot (
+ IN DXE_PCH_PLATFORM_POLICY_PROTOCOL *PchPlatformPolicy,
+ IN BOOLEAN IsSetS3BootScript
+ )
+{
+ UINTN OtgPciMmBase;
+ UINT32 OtgMmioBase0;
+ UINT32 OtgMmioBase1;
+ UINT32 Data32And;
+ UINT32 Data32Or;
+ EFI_STATUS Status;
+#ifndef FSP_FLAG
+ EFI_GLOBAL_NVS_AREA_PROTOCOL *GlobalNvsArea;
+#endif
+ DEBUG ((EFI_D_INFO, "ConfigureOtgAtBoot() Start\n"));
+ //
+ // Initialize Variables
+ //
+ OtgPciMmBase = 0;
+ OtgMmioBase0 = 0;
+ OtgMmioBase1 = 0;
+ Data32And = 0;
+ Data32Or = 0;
+ Status = EFI_SUCCESS;
+ //
+ // Update OTG device ACPI variables
+ //
+ if (PchPlatformPolicy->UsbConfig->UsbOtgSettings.Enable == PchAcpiMode) {
+#ifndef FSP_FLAG
+ //
+ // Locate GlobalNVS protocol
+ //
+ Status = gBS->LocateProtocol (
+ &gEfiGlobalNvsAreaProtocolGuid,
+ NULL,
+ (VOID **) &GlobalNvsArea
+ );
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+#endif
+
+ OtgPciMmBase = MmPciAddress (
+ 0,
+ DEFAULT_PCI_BUS_NUMBER_PCH,
+ PCI_DEVICE_NUMBER_PCH_OTG,
+ PCI_FUNCTION_NUMBER_PCH_OTG,
+ 0
+ );
+ OtgMmioBase0 = MmioRead32 ((UINTN) (OtgPciMmBase + R_PCH_OTG_BAR0)) & B_PCH_OTG_BAR0_BA;
+ ASSERT ((OtgMmioBase0 != 0) && (OtgMmioBase0 != B_PCH_OTG_BAR0_BA));
+ OtgMmioBase1 = MmioRead32 ((UINTN) (OtgPciMmBase + R_PCH_OTG_BAR1)) & B_PCH_OTG_BAR1_BA;
+ ASSERT ((OtgMmioBase1 != 0) && (OtgMmioBase1 != B_PCH_OTG_BAR1_BA));
+ if (!IsSetS3BootScript) {
+
+ MmioOr32 (
+ (UINTN) (OtgPciMmBase + R_PCH_OTG_STSCMD),
+ (UINT32) (B_PCH_OTG_STSCMD_INTR_DIS | B_PCH_OTG_STSCMD_BME | B_PCH_OTG_STSCMD_MSE)
+ );
+#ifndef FSP_FLAG
+ //
+ // Update BAR and length in ACPI table.
+ //
+ GlobalNvsArea->Area->UsbOtgAddr = OtgMmioBase0;
+ GlobalNvsArea->Area->UsbOtgAddr1 = OtgMmioBase1;
+#endif
+
+ PchMsgBusAndThenOr32 (
+ 0x59,
+ 0x500,
+ 0xFFFFFFFF,
+ (BIT1 | BIT0),
+ 0x06,
+ 0x07
+ );
+ } else {
+ //
+ // Set S3 Boot Script
+ //
+ S3BootScriptSaveMemWrite (
+ S3BootScriptWidthUint32,
+ (UINTN) (OtgPciMmBase + R_PCH_OTG_BAR0),
+ 1,
+ &OtgMmioBase0
+ );
+ S3BootScriptSaveMemWrite (
+ S3BootScriptWidthUint32,
+ (UINTN) (OtgPciMmBase + R_PCH_OTG_BAR1),
+ 1,
+ &OtgMmioBase1
+ );
+ Data32Or = (UINT32) (B_PCH_OTG_STSCMD_INTR_DIS | B_PCH_OTG_STSCMD_BME | B_PCH_OTG_STSCMD_MSE);
+ Data32And = 0xFFFFFFFF;
+ S3BootScriptSaveMemReadWrite (
+ EfiBootScriptWidthUint32,
+ (UINTN) (OtgPciMmBase + R_PCH_OTG_STSCMD),
+ &Data32Or, // OR mask
+ &Data32And // AND mask
+ );
+ SetMsgBusAndThenOr32S3Item (
+ 0x59,
+ 0x500,
+ 0xFFFFFFFF,
+ (BIT1 | BIT0),
+ 0x06,
+ 0x07
+ );
+ }
+ }
+
+ DEBUG ((EFI_D_INFO, "ConfigureOtgAtBoot() End\n"));
+
+ return EFI_SUCCESS;
+}
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