diff options
| author | Feng Tian <feng.tian@intel.com> | 2016-09-14 09:48:40 +0800 |
|---|---|---|
| committer | Feng Tian <feng.tian@intel.com> | 2016-09-21 12:42:06 +0800 |
| commit | 1f87985ab7958664a84da78095b5892f88acf3f1 (patch) | |
| tree | 857c4f245ae09ade12cc9be55713838d815e7ce2 | |
| parent | dbe10619bc443215477c5c0c4c949410bf68b1ec (diff) | |
| download | edk2-platforms-1f87985ab7958664a84da78095b5892f88acf3f1.tar.xz | |
MdeModulePkg/XhciPei:1ms delay before access MMIO reg during reset
Some XHCI host controllers require to have extra 1ms delay before
accessing any MMIO register during HC reset.
As this delay is not defined by XHCI spec, we use this workaround
to fix the issue.
Cc: Star Zeng <star.zeng@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Feng Tian <feng.tian@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
| -rw-r--r-- | MdeModulePkg/Bus/Pci/XhciPei/XhcPeim.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/MdeModulePkg/Bus/Pci/XhciPei/XhcPeim.c b/MdeModulePkg/Bus/Pci/XhciPei/XhcPeim.c index a58739fb4a..57e70701e8 100644 --- a/MdeModulePkg/Bus/Pci/XhciPei/XhcPeim.c +++ b/MdeModulePkg/Bus/Pci/XhciPei/XhcPeim.c @@ -407,6 +407,12 @@ XhcPeiResetHC ( }
XhcPeiSetOpRegBit (Xhc, XHC_USBCMD_OFFSET, XHC_USBCMD_RESET);
+ //
+ // Some XHCI host controllers require to have extra 1ms delay before accessing any MMIO register during reset.
+ // Otherwise there may have the timeout case happened.
+ // The below is a workaround to solve such problem.
+ //
+ MicroSecondDelay (1000);
Status = XhcPeiWaitOpRegBit (Xhc, XHC_USBCMD_OFFSET, XHC_USBCMD_RESET, FALSE, Timeout);
ON_EXIT:
DEBUG ((EFI_D_INFO, "XhcPeiResetHC: %r\n", Status));
|