Fix MRC parameters restore failure issue

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Guo Mang <mang.guo@intel.com>

7 files changed, 105 insertions, 20 deletions

diff --git a/Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPreMem/BoardInitMiscs.c b/Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPreMem/BoardInitMiscs.c
index 0a932015e0..fe8ece0b88 100644
--- a/Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPreMem/BoardInitMiscs.c
+++ b/Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPreMem/BoardInitMiscs.c
@@ -1,7 +1,7 @@
 /** @file

   This file does Multiplatform initialization.

 

-  Copyright (c) 2010 - 2016, Intel Corporation. All rights reserved.<BR>

+  Copyright (c) 2010 - 2017, Intel Corporation. All rights reserved.<BR>

 

   This program and the accompanying materials

   are licensed and made available under the terms and conditions of the BSD License

@@ -14,6 +14,7 @@
 **/

 

 #include "BoardInitMiscs.h"

+#include "MmrcData.h"

 

 UPDATE_FSPM_UPD_FUNC mLhUpdateFspmUpdPtr = LhUpdateFspmUpd;

 DRAM_CREATE_POLICY_DEFAULTS_FUNC   mLhDramCreatePolicyDefaultsPtr = LhDramCreatePolicyDefaults;

@@ -29,6 +30,9 @@ LhUpdateFspmUpd (
   EFI_PLATFORM_INFO_HOB          *PlatformInfo = NULL;

   DRAM_POLICY_PPI                *DramPolicy;

   EFI_STATUS                     Status;

+  MRC_NV_DATA_FRAME              *MrcNvData;

+  MRC_PARAMS_SAVE_RESTORE        *MrcParamsHob;

+  BOOT_VARIABLE_NV_DATA          *BootVariableNvDataHob;

 

   Status = (*PeiServices)->LocatePpi (

                              PeiServices,

@@ -64,11 +68,20 @@ LhUpdateFspmUpd (
     FspUpdRgn->FspmConfig.InterleavedMode                   = DramPolicy->InterleavedMode;

     FspUpdRgn->FspmConfig.MinRefRate2xEnable                = DramPolicy->MinRefRate2xEnabled;

     FspUpdRgn->FspmConfig.DualRankSupportEnable             = DramPolicy->DualRankSupportEnabled;

-    FspUpdRgn->FspmArchUpd.NvsBufferPtr                     = (VOID *)(UINT32)DramPolicy->MrcTrainingDataPtr;

-    FspUpdRgn->FspmConfig.MrcBootDataPtr                    = (VOID *)(UINT32)DramPolicy->MrcBootDataPtr;

 

     CopyMem (&(FspUpdRgn->FspmConfig.Ch0_RankEnable), &DramPolicy->ChDrp, sizeof (DramPolicy->ChDrp));

     CopyMem (&(FspUpdRgn->FspmConfig.Ch0_Bit_swizzling), &DramPolicy->ChSwizzle, sizeof (DramPolicy->ChSwizzle));

+

+    if (((VOID *)(UINT32)DramPolicy->MrcTrainingDataPtr != 0) &&

+        ((VOID *)(UINT32)DramPolicy->MrcBootDataPtr     != 0)) {

+      MrcNvData = (MRC_NV_DATA_FRAME *) AllocateZeroPool (sizeof (MRC_NV_DATA_FRAME));

+      MrcParamsHob = (MRC_PARAMS_SAVE_RESTORE*)((UINT32)DramPolicy->MrcTrainingDataPtr);

+      BootVariableNvDataHob = (BOOT_VARIABLE_NV_DATA*)((UINT32)DramPolicy->MrcBootDataPtr);

+      CopyMem(&(MrcNvData->MrcParamsSaveRestore), MrcParamsHob, sizeof (MRC_PARAMS_SAVE_RESTORE));

+      CopyMem(&(MrcNvData->BootVariableNvData), BootVariableNvDataHob, sizeof (BOOT_VARIABLE_NV_DATA));

+      FspUpdRgn->FspmArchUpd.NvsBufferPtr = (VOID *)(UINT32)MrcNvData;

+    }

+

   }

   //

   // override RankEnable settings for Minnow

diff --git a/Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPreMem/BoardInitPreMem.inf b/Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPreMem/BoardInitPreMem.inf
index 97ed7b2342..c526bc2c09 100644
--- a/Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPreMem/BoardInitPreMem.inf
+++ b/Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPreMem/BoardInitPreMem.inf
@@ -2,7 +2,7 @@
 #  Board detected module for Intel(R) Atom(TM) x5 Processor Series.

 #  It will detect the board ID.

 #

-#  Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.<BR>

+#  Copyright (c) 2014 - 2017, Intel Corporation. All rights reserved.<BR>

 #

 #  This program and the accompanying materials

 #  are licensed and made available under the terms and conditions of the BSD License

@@ -39,6 +39,7 @@
   IntelFsp2Pkg/IntelFsp2Pkg.dec

   BroxtonPlatformPkg/Common/SampleCode/IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec

   IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec

+  Silicon\BroxtonSoC\BroxtonSiPkg\NorthCluster\MemoryInit\MemoryInit.dec

 

 [Pcd]

   gPlatformModuleTokenSpaceGuid.PcdBoardId

diff --git a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPreMem/BoardInitMiscs.c b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPreMem/BoardInitMiscs.c
index edf6147b18..9e535ca8e9 100644
--- a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPreMem/BoardInitMiscs.c
+++ b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPreMem/BoardInitMiscs.c
@@ -1,7 +1,7 @@
 /** @file

   This file does Multiplatform initialization.

 

-  Copyright (c) 2010 - 2016, Intel Corporation. All rights reserved.<BR>

+  Copyright (c) 2010 - 2017, Intel Corporation. All rights reserved.<BR>

 

   This program and the accompanying materials

   are licensed and made available under the terms and conditions of the BSD License

@@ -14,6 +14,7 @@
 **/

 

 #include "BoardInitMiscs.h"

+#include "MmrcData.h"

 

 UPDATE_FSPM_UPD_FUNC mMb3UpdateFspmUpdPtr = Mb3UpdateFspmUpd;

 DRAM_CREATE_POLICY_DEFAULTS_FUNC   mMb3DramCreatePolicyDefaultsPtr = Mb3DramCreatePolicyDefaults;

@@ -29,6 +30,9 @@ Mb3UpdateFspmUpd (
   EFI_PLATFORM_INFO_HOB          *PlatformInfo = NULL;

   DRAM_POLICY_PPI                *DramPolicy;

   EFI_STATUS                     Status;

+  MRC_NV_DATA_FRAME              *MrcNvData;

+  MRC_PARAMS_SAVE_RESTORE        *MrcParamsHob;

+  BOOT_VARIABLE_NV_DATA          *BootVariableNvDataHob;

 

   Status = (*PeiServices)->LocatePpi (

                              PeiServices,

@@ -64,11 +68,20 @@ Mb3UpdateFspmUpd (
     FspUpdRgn->FspmConfig.InterleavedMode                   = DramPolicy->InterleavedMode;

     FspUpdRgn->FspmConfig.MinRefRate2xEnable                = DramPolicy->MinRefRate2xEnabled;

     FspUpdRgn->FspmConfig.DualRankSupportEnable             = DramPolicy->DualRankSupportEnabled;

-    FspUpdRgn->FspmArchUpd.NvsBufferPtr                     = (VOID *)(UINT32)DramPolicy->MrcTrainingDataPtr;

-    FspUpdRgn->FspmConfig.MrcBootDataPtr                    = (VOID *)(UINT32)DramPolicy->MrcBootDataPtr;

 

     CopyMem (&(FspUpdRgn->FspmConfig.Ch0_RankEnable), &DramPolicy->ChDrp, sizeof(DramPolicy->ChDrp));

     CopyMem (&(FspUpdRgn->FspmConfig.Ch0_Bit_swizzling), &DramPolicy->ChSwizzle, sizeof (DramPolicy->ChSwizzle));

+

+    if (((VOID *)(UINT32)DramPolicy->MrcTrainingDataPtr != 0) &&

+        ((VOID *)(UINT32)DramPolicy->MrcBootDataPtr     != 0)) {

+      MrcNvData = (MRC_NV_DATA_FRAME *) AllocateZeroPool (sizeof (MRC_NV_DATA_FRAME));

+      MrcParamsHob = (MRC_PARAMS_SAVE_RESTORE*)((UINT32)DramPolicy->MrcTrainingDataPtr);

+      BootVariableNvDataHob = (BOOT_VARIABLE_NV_DATA*)((UINT32)DramPolicy->MrcBootDataPtr);

+      CopyMem(&(MrcNvData->MrcParamsSaveRestore), MrcParamsHob, sizeof (MRC_PARAMS_SAVE_RESTORE));

+      CopyMem(&(MrcNvData->BootVariableNvData), BootVariableNvDataHob, sizeof (BOOT_VARIABLE_NV_DATA));

+      FspUpdRgn->FspmArchUpd.NvsBufferPtr = (VOID *)(UINT32)MrcNvData;

+    }

+

   }

   //

   // override RankEnable settings for Minnow

diff --git a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPreMem/BoardInitPreMem.inf b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPreMem/BoardInitPreMem.inf
index 81448e365b..9135fb8612 100644
--- a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPreMem/BoardInitPreMem.inf
+++ b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPreMem/BoardInitPreMem.inf
@@ -2,7 +2,7 @@
 #  Board detected module for Intel(R) Atom(TM) x5 Processor Series.

 #  It will detect the board ID.

 #

-#  Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.<BR>

+#  Copyright (c) 2014 - 2017, Intel Corporation. All rights reserved.<BR>

 #

 #  This program and the accompanying materials

 #  are licensed and made available under the terms and conditions of the BSD License

@@ -39,6 +39,7 @@
   IntelFsp2Pkg/IntelFsp2Pkg.dec

   BroxtonPlatformPkg/Common/SampleCode/IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec

   IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec

+  Silicon\BroxtonSoC\BroxtonSiPkg\NorthCluster\MemoryInit\MemoryInit.dec

 

 [Pcd]

   gPlatformModuleTokenSpaceGuid.PcdBoardId

diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/Include/Ppi/DramPolicyPpi.h b/Silicon/BroxtonSoC/BroxtonSiPkg/Include/Ppi/DramPolicyPpi.h
index 0d9b1d6e01..6d610a5fdb 100644
--- a/Silicon/BroxtonSoC/BroxtonSiPkg/Include/Ppi/DramPolicyPpi.h
+++ b/Silicon/BroxtonSoC/BroxtonSiPkg/Include/Ppi/DramPolicyPpi.h
@@ -1,8 +1,9 @@
+

 /** @file

   Dram Policy PPI is used for specifying platform

   related Intel silicon information and policy setting.

 

-  Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.<BR>

+  Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>

 

   This program and the accompanying materials

   are licensed and made available under the terms and conditions of the BSD License

@@ -56,10 +57,12 @@ typedef struct {
   UINT8                 RmtMode;

   UINT8                 RmtCheckRun;

   UINT16                RmtMarginCheckScaleHighThreshold;

+  UINT8                 Reserved1;

   UINT32                MsgLevelMask;

   UINT8                 SpdAddress[DRAM_POLICY_NUMBER_SPD_ADDRESSES];

   UINT8                 ChSwizzle[DRAM_POLICY_NUMBER_CHANNELS][DRAM_POLICY_NUMBER_BITS];

   DRP_DRAM_POLICY       ChDrp[DRAM_POLICY_NUMBER_CHANNELS];

+  UINT8                 Reserved2;

   UINT8                 DebugMsgLevel;

   UINT8                 reserved[13];

 } DRAM_POLICY_PPI;

diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/MemoryInit/BXT/Include/MrcEfiDefinitions.h b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/MemoryInit/BXT/Include/MrcEfiDefinitions.h
index e1342a07dd..1bf9d0ffec 100644
--- a/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/MemoryInit/BXT/Include/MrcEfiDefinitions.h
+++ b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/MemoryInit/BXT/Include/MrcEfiDefinitions.h
@@ -1,5 +1,5 @@
 /** @file

-  Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>

+  Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>

 

   This program and the accompanying materials

   are licensed and made available under the terms and conditions of the BSD License

@@ -64,10 +64,12 @@ typedef struct {
   UINT8                 RmtMode;

   UINT8                 RmtCheckRun;

   UINT16                RmtMarginCheckScaleHighThreshold;

+  UINT8                 Reserved1;

   UINT32                MsgLevelMask;

   UINT8                 SpdAddress[DRAM_POLICY_NUMBER_SPD_ADDRESSES];

   UINT8                 ChSwizzle[DRAM_POLICY_NUMBER_CHANNELS][DRAM_POLICY_NUMBER_BITS];

   DRP_DRAM_POLICY       ChDrp[DRAM_POLICY_NUMBER_CHANNELS];

+  UINT8                 Reserved2;

   UINT8                 DebugMsgLevel;

   UINT8                 reserved[13];

 } DRAM_POLICY_PPI;

@@ -79,7 +81,6 @@ typedef struct {
 typedef enum {

   Bxt          = 0x00,

   Bxt1,

-  BxtX,

   BxtP,

   BxtSeriesMax = 0xFF

 } BXT_SERIES;

diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/MemoryInit/Mmrc/ProjectIndependent/Include/MmrcData.h b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/MemoryInit/Mmrc/ProjectIndependent/Include/MmrcData.h
index 0a7672bbfe..5f65ba7c62 100644
--- a/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/MemoryInit/Mmrc/ProjectIndependent/Include/MmrcData.h
+++ b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/MemoryInit/Mmrc/ProjectIndependent/Include/MmrcData.h
@@ -1,7 +1,7 @@
 /** @file

   Internal and external data structures, Macros, and enumerations.

 

-  Copyright (c) 2005 - 2016, Intel Corporation. All rights reserved.<BR>

+  Copyright (c) 2005 - 2017, Intel Corporation. All rights reserved.<BR>

 

   This program and the accompanying materials

   are licensed and made available under the terms and conditions of the BSD License

@@ -12,7 +12,6 @@
   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

 

 **/

-

 #ifndef _MMRCDATA_H_

 #define _MMRCDATA_H_

 

@@ -28,12 +27,10 @@
 #else

 #define UINTX UINT32

 #endif

-

 typedef UINT32           MMRC_STATUS;

-

-//

-// MRC version description.

-//

+///

+/// MRC version description.

+///

 typedef union {

   struct{

     UINT8      Major;             ///< Major version number

@@ -54,6 +51,60 @@ typedef union {
   UINT8      Data8[4];

 } MrcVersion;

 

+typedef union {

+  UINT8      Data;

+  struct {

+    //

+    // Rank Select Interleaving Enable.  See Address Mapping section for full description.

+    //     0 - Rank Select Interleaving disabled

+    //     1 - Rank Select Interleaving enabled

+    //

+    // Bits[0:0]

+    //

+    UINT8    RankSelectInterleavingEnable : 1;

+    //

+    // Bank Address Hashing Enable.  See Address Mapping section for full description.

+    //     0 - Bank Address Hashing disabled

+    //     1 - Bank Address Hashing enabled

+    //

+    // Bits[1:1]

+    //

+    UINT8    BankAddressHashingEnable : 1;

+    //

+    // CH1 CLK Disable. Disables the CH1 CLK PHY Signal when set to 1. This is used

+    // on board designs where the CH1 CLK is not routed and left floating or stubbed out.

+    //     0 = CH1 CLK is enabled

+    //     1 = CH1 CLK is disabled

+    //

+    // Bits[2:2]

+    //

+    UINT8    Ch1ClkDisable : 1;

+    //

+    // Reserved

+    //

+    // Bits[3]

+    //

+    UINT8    Reserved : 1;

+    //

+    // Specifies the address mapping to be used.

+    //       00b - 1KB,

+    //       01b - 2KB,

+    //       10b - 4KB,

+    //       11b - Reserved

+    //

+    // Bits[5:4]

+    //

+    UINT8    AddressMapping : 2;

+    //

+    // Reserved

+    //

+    // Bits[7:6]

+    //

+    UINT8    Reserved0 : 2;

+  } Bits;

+} CHANNEL_OPTION;

+

+

 #ifndef ABSOLUTE

 #define ABSOLUTE                      1

 #define RELATIVE                      2

@@ -106,6 +157,9 @@ typedef enum {
 #define BIT31                 0x80000000

 #endif

 

+

+#pragma pack(1)

+

 typedef enum  {

   Pfct =  0,

   PfctT,

@@ -134,7 +188,6 @@ typedef struct {
 /**

   Final training values stored on a per blueprint level. Needs to be per blueprint

   in case of a system with more than 1 level of memory per channel.

-

 **/

 typedef struct {

   UINT16    Values[MAX_BLUEPRINTS][MAX_NUM_ALGOS][MAX_RANKS][MAX_STROBES];

@@ -214,6 +267,7 @@ typedef struct {
   UINT8                     OdtHigh;

   UINT16                    LP4_MR0VALUE;

   UINT16                    LP4_MR4VALUE;

+  CHANNEL_OPTION            ChOption;

 } CHANNEL;

 

 typedef struct {

@@ -244,7 +298,6 @@ typedef struct {
   BOOT_VARIABLE_NV_DATA   BootVariableNvData;

 } MRC_NV_DATA_FRAME;

 

-#pragma pack()

 #pragma pack(pop)

 #endif