BroxtonSiPkg: Add Cpu/AcpiTables

Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Guo Mang <mang.guo@intel.com>
author: Guo Mang <mang.guo@intel.com> 2016-12-23 10:44:35 +0800
committer: Guo Mang <mang.guo@intel.com> 2016-12-26 19:15:03 +0800
commit: 53c716058fdca56a2c82efdb4011a84f6eae5746 (patch)
tree: 00cf5ee4bca0212943da1a4355a496111899b851
parent: a674eea1c47a6aa0170b2beb07d4f2bbefc798e0 (diff)
download: edk2-platforms-53c716058fdca56a2c82efdb4011a84f6eae5746.tar.xz
8 files changed, 1608 insertions, 0 deletions
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/AcpiTables/CpuAcpiTables.inf b/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/AcpiTables/CpuAcpiTables.inf
new file mode 100644
index 0000000000..bc5c72a936
--- /dev/null
+++ b/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/AcpiTables/CpuAcpiTables.inf
@@ -0,0 +1,35 @@
+## @file
+#  CPU Power Management ACPI Tables Module.
+#
+#  Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved.<BR>
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution. The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php.
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+[Defines]
+  INF_VERSION                       = 0x00010017
+  BASE_NAME                         = CpuAcpiTables
+  FILE_GUID                         = C38FB0E2-0C43-49c9-B544-9B17AA4DCBA3
+  MODULE_TYPE                       = USER_DEFINED
+  VERSION_STRING                    = 1.0
+
+[Packages]
+  MdePkg/MdePkg.dec
+  BroxtonSiPkg/BroxtonSiPkg.dec
+  BroxtonSiPkg/BroxtonSiPrivate.dec
+
+[Sources]
+  CpuSsdt/Cpu0Cst.asl
+  CpuSsdt/Cpu0Ist.asl
+  CpuSsdt/Cpu0Tst.asl
+  CpuSsdt/ApCst.asl
+  CpuSsdt/ApIst.asl
+  CpuSsdt/ApTst.asl
+  CpuSsdt/CpuSsdt.asl
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/AcpiTables/CpuSsdt/ApCst.asl b/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/AcpiTables/CpuSsdt/ApCst.asl
new file mode 100644
index 0000000000..cd3ac836a4
--- /dev/null
+++ b/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/AcpiTables/CpuSsdt/ApCst.asl
@@ -0,0 +1,63 @@
+/** @file
+  Intel Processor Power Management CST ACPI Code.
+
+  Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved.<BR>
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php.
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+DefinitionBlock (
+  "APCST.aml",
+  "SSDT",
+  2,
+  "PmRef",
+  "ApCst",
+  0x3000
+  )
+{
+  External(\_PR.CPU1, DeviceObj)
+  External(\_PR.CPU2, DeviceObj)
+  External(\_PR.CPU3, DeviceObj)
+  External(\_PR.CPU0._CST)
+
+  Scope(\_PR.CPU1)
+  {
+    Method(_CST,0)
+    {
+      //
+      // Return P0's _CST object.
+      //
+      Return(\_PR.CPU0._CST)
+    }
+  }
+
+  Scope(\_PR.CPU2)
+  {
+    Method(_CST,0)
+    {
+      //
+      // Return P0's _CST object.
+      //
+      Return(\_PR.CPU0._CST)
+    }
+  }
+
+  Scope(\_PR.CPU3)
+  {
+    Method(_CST,0)
+    {
+      //
+      // Return P0's _CST object.
+      //
+      Return(\_PR.CPU0._CST)
+    }
+  }
+}  // End of Definition Block
+
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/AcpiTables/CpuSsdt/ApIst.asl b/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/AcpiTables/CpuSsdt/ApIst.asl
new file mode 100644
index 0000000000..1c3fb15689
--- /dev/null
+++ b/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/AcpiTables/CpuSsdt/ApIst.asl
@@ -0,0 +1,105 @@
+/** @file
+  Intel Processor Power Management IST ACPI Code.
+
+  Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved.<BR>
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php.
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+DefinitionBlock (
+  "APIST.aml",
+  "SSDT",
+  2,
+  "PmRef",
+  "ApIst",
+  0x3000
+  )
+{
+  External(\_PR.CPU0._PSS, MethodObj)
+  External(\_PR.CPU0._PCT, MethodObj)
+  External(\_PR.CPU0._PPC, IntObj)
+  External(\_PR.CPU0._PSD, MethodObj)
+  External(\_PR.CPU1, DeviceObj)
+  External(\_PR.CPU2, DeviceObj)
+  External(\_PR.CPU3, DeviceObj)
+  External(\_PR.CFGD, IntObj)
+  External (PDC0)
+
+  Scope(\_PR.CPU1)
+  {
+    Method(_PPC,0)
+    {
+      Return(\_PR.CPU0._PPC)  // Return P0 _PPC value.
+    }
+
+    Method(_PCT,0)
+    {
+      Return(\_PR.CPU0._PCT)  // Return P0 _PCT.
+    }
+
+    Method(_PSS,0)
+    {
+      //Return the same table as CPU0 for CMP cases.
+      Return(\_PR.CPU0._PSS)
+    }
+    Method(_PSD,0)
+    {
+      Return(\_PR.CPU0._PSD)  // Return P0 _PSD.
+    }
+  }
+
+  Scope(\_PR.CPU2)
+  {
+    Method(_PPC,0)
+    {
+      Return(\_PR.CPU0._PPC)  // Return CPU0 _PPC value.
+    }
+
+    Method(_PCT,0)
+    {
+      Return(\_PR.CPU0._PCT)  // Return CPU0 _PCT value.
+    }
+
+    Method(_PSS,0)
+    {
+      Return(\_PR.CPU0._PSS)  // Return CPU0 _PSS.
+    }
+
+    Method(_PSD,0)
+    {
+      Return(\_PR.CPU0._PSD)  // Return P0 _PSD.
+    }
+  }
+
+  Scope(\_PR.CPU3)
+  {
+    Method(_PPC,0)
+    {
+      Return(\_PR.CPU0._PPC)  // Return CPU0 _PPC value.
+    }
+
+    Method(_PCT,0)
+    {
+      Return(\_PR.CPU0._PCT)  // Return CPU0 _PCT value.
+    }
+
+    Method(_PSS,0)
+    {
+      Return(\_PR.CPU0._PSS)  // Return CPU0 _PSS.
+    }
+
+    Method(_PSD,0)
+    {
+      Return(\_PR.CPU0._PSD)  // Return P0 _PSD.
+    }
+  }
+
+} // End of Definition Block
+
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/AcpiTables/CpuSsdt/ApTst.asl b/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/AcpiTables/CpuSsdt/ApTst.asl
new file mode 100644
index 0000000000..44f4063eaf
--- /dev/null
+++ b/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/AcpiTables/CpuSsdt/ApTst.asl
@@ -0,0 +1,207 @@
+/** @file
+  Intel Processor AP TST ACPI Code.
+
+  Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved.<BR>
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php.
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+DefinitionBlock(
+  "APTST.aml",
+  "SSDT",
+  0x02,
+  "PmRef",
+  "ApTst",
+  0x3000
+  )
+{
+  External(\_PR.CPU1, DeviceObj)
+  External(\_PR.CPU2, DeviceObj)
+  External(\_PR.CPU3, DeviceObj)
+  External(\_PR.CPU0._PTC)
+  External(\_PR.CPU0._TSS)
+  External(PDC0)
+  External(\_PR.CFGD, IntObj)
+  External(NLPC)
+
+  Scope(\_PR.CPU1)
+  {
+    Name(_TPC, 0) // All T-States are available
+
+    //
+    // T-State Control/Status interface
+    //
+    Method(_PTC, 0)
+    {
+      Return(\_PR.CPU0._PTC)
+    }
+
+    Method(_TSS, 0)
+    {
+      Return(\_PR.CPU0._TSS)
+    }
+
+    //
+    // T-State Dependency
+    //
+    Method(_TSD, 0)
+    {
+      //
+      // IF four cores are supported/enabled && !(direct access to MSR)
+      //    Report 4 processors and SW_ANY as the coordination
+      // IF two cores are supported/enabled && !(direct access to MSR)
+      //    Report 2 processors and SW_ANY as the coordination type
+      //  ELSE
+      //    Report 1 processor and SW_ALL as the coordination type (domain 1)
+      //
+      //  PDCx[2] = OSPM is capable of direct access to On
+      //    Demand throttling MSR
+      //
+
+      If (LNot(And(PDC0,4))) {
+        Return(Package() { // SW_ANY
+          Package(){
+            5,            // # entries.
+            0,            // Revision.
+            0,            // Domain #.
+            0xFD,         // Coord Type- SW_ANY
+            NLPC          // # processors.
+          }
+        })
+      }
+      Return(Package() {   // SW_ALL
+        Package(){
+          5,              // # entries.
+          0,              // Revision.
+          1,              // Domain #.
+          0xFC,           // Coord Type- SW_ALL
+          1               // # processors.
+        }
+      })
+    }
+  }  // End of CPU1
+
+
+  Scope(\_PR.CPU2)
+  {
+    Name(_TPC, 0) // All T-States are available
+
+    //
+    // T-State Control/Status interface
+    //
+    Method(_PTC, 0)
+    {
+      Return(\_PR.CPU0._PTC)
+    }
+
+    Method(_TSS, 0)
+    {
+      Return(\_PR.CPU0._TSS)
+    }
+
+    //
+    // T-State Dependency
+    //
+    Method(_TSD, 0)
+    {
+      //
+      // IF four cores are supported/enabled && !(direct access to MSR)
+      //    Report 4 processors and SW_ANY as the coordination
+      // IF two cores are supported/enabled && !(direct access to MSR)
+      //    Report 2 processors and SW_ANY as the coordination type
+      //  ELSE
+      //    Report 1 processor and SW_ALL as the coordination type (domain 2)
+      //
+      //  PDCx[2] = OSPM is capable of direct access to On
+      //    Demand throttling MSR
+      //
+
+      If (LNot(And(PDC0,4))) {
+        Return(Package() { // SW_ANY
+          Package(){
+            5,            // # entries.
+            0,            // Revision.
+            0,            // Domain #.
+            0xFD,         // Coord Type- SW_ANY
+            NLPC          // # processors.
+          }
+        })
+      }
+      Return(Package() {   // SW_ALL
+        Package(){
+          5,              // # entries.
+          0,              // Revision.
+          2,              // Domain #.
+          0xFC,           // Coord Type- SW_ALL
+          1               // # processors.
+        }
+      })
+    }
+  }  // End of CPU2
+
+
+  Scope(\_PR.CPU3)
+  {
+    Name(_TPC, 0) // All T-States are available
+
+    //
+    // T-State Control/Status interface
+    //
+    Method(_PTC, 0)
+    {
+      Return(\_PR.CPU0._PTC)
+    }
+
+    Method(_TSS, 0)
+    {
+      Return(\_PR.CPU0._TSS)
+    }
+
+    //
+    // T-State Dependency
+    //
+    Method(_TSD, 0)
+    {
+      //
+      // IF four cores are supported/enabled && !(direct access to MSR)
+      //    Report 4 processors and SW_ANY as the coordination
+      // IF two cores are supported/enabled && !(direct access to MSR)
+      //    Report 2 processors and SW_ANY as the coordination type
+      //  ELSE
+      //    Report 1 processor and SW_ALL as the coordination type (domain 3)
+      //
+      //  PDCx[2] = OSPM is capable of direct access to On
+      //    Demand throttling MSR
+      //
+
+      If (LNot(And(PDC0,4))) {
+        Return(Package() { // SW_ANY
+          Package(){
+            5,            // # entries.
+            0,            // Revision.
+            0,            // Domain #.
+            0xFD,         // Coord Type- SW_ANY
+            NLPC          // # processors.
+          }
+        })
+      }
+      Return(Package() {   // SW_ALL
+        Package(){
+          5,              // # entries.
+          0,              // Revision.
+          3,              // Domain #.
+          0xFC,           // Coord Type- SW_ALL
+          1               // # processors.
+        }
+      })
+    }
+  }  // End of CPU3
+} // End of Definition Block
+
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/AcpiTables/CpuSsdt/Cpu0Cst.asl b/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/AcpiTables/CpuSsdt/Cpu0Cst.asl
new file mode 100644
index 0000000000..aaf1ac5808
--- /dev/null
+++ b/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/AcpiTables/CpuSsdt/Cpu0Cst.asl
@@ -0,0 +1,113 @@
+/** @file
+  Intel Processor Power Management ACPI Code.
+
+  Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved.<BR>
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php.
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "CpuPowerMgmt.h"
+
+DefinitionBlock (
+  "CPU0CST.aml",
+  "SSDT",
+  2,
+  "PmRef",
+  "Cpu0Cst",
+  0x3001
+  )
+{
+  External(\_PR.CPU0, DeviceObj)
+  External(PWRS)
+  External(\_PR.CFGD, IntObj)
+  External(PDC0)
+  External(FMBL)
+  External(FEMD)
+  External(PFLV)
+  External(C3MW)       // Mwait Hint value for C3
+  External(C6MW)       // Mwait Hint value for C6
+  External(C7MW)       // Mwait Hint value for C7
+  External(CDMW)       // Mwait Hint value for C8/C9/C10
+  External(C3LT)       // Latency value for C3
+  External(C6LT)       // Latency Value for C6
+  External(C7LT)       // Latency Value for C7
+  External(CDLT)       // Latency Value for C8/C9/C10
+  External(CDLV)       // IO Level value for C8/C9/C10
+  External(CDPW)       // Power value for  C8/C9/C10
+  External(MWEN)
+
+  External(BDID)
+  External(BTDT)
+  External(BTMB)
+
+  Scope(\_PR.CPU0)
+  {
+    Method (_CST, 0)
+    {
+      If (LEqual(MWEN, 0)) {
+        Return( Package()
+        {
+          3,
+          Package()
+          { // C1, LVT
+            ResourceTemplate(){Register(FFixedHW, 0, 0, 0)},
+            1,
+            1,
+            1000
+          },
+          Package()
+          {
+            // C6L, LVT
+            ResourceTemplate(){Register(SystemIO, 8, 0, 0x415)},
+            2,
+            50,
+            10
+          },
+          Package()
+          {
+            // C10, LVT
+            ResourceTemplate(){Register(SystemIO, 8, 0, 0x419)},
+            3,
+            150,   //Pre-silicon setting, 11 ms for worst-case exit latency
+            10
+          }
+        })
+      }
+        Return( Package()
+        {
+          3,
+          Package()
+          { // C1, MWAIT
+            ResourceTemplate(){Register(FFixedHW, 1, 2, 0x01, 1)},
+            1,
+            1,
+            1000
+          },
+          Package()
+          {
+            // C6L, MWAIT Extension
+            ResourceTemplate(){Register(FFixedHW, 1, 2, 0x21, 1)},
+            2,
+            50,
+            10
+          },
+          Package()
+          {
+            // C10, MWAIT Extension
+            ResourceTemplate(){Register(FFixedHW, 1, 2, 0x60, 1)},
+            3,
+            150,   //Pre-silicon setting, 11 ms for worst-case exit latency
+            10
+          }
+        })
+      }
+    }
+}
+
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/AcpiTables/CpuSsdt/Cpu0Ist.asl b/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/AcpiTables/CpuSsdt/Cpu0Ist.asl
new file mode 100644
index 0000000000..6d2e148484
--- /dev/null
+++ b/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/AcpiTables/CpuSsdt/Cpu0Ist.asl
@@ -0,0 +1,142 @@
+/** @file
+  Intel Processor Power Management ACPI Code.
+
+  Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved.<BR>
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php.
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+DefinitionBlock (
+  "CPU0IST.aml",
+  "SSDT",
+  0x02,
+  "PmRef",
+  "Cpu0Ist",
+  0x3000
+  )
+{
+  External (\_PR.CPU0, DeviceObj)
+  External (PDC0)
+  External(\_PR.CFGD, IntObj)
+  External (TCNT)
+  External (OSSL)
+  External (NLPC)
+  Scope(\_PR.CPU0)
+  {
+    //
+    // Report supported P-States.
+    //
+    Name(_PPC, 0)
+
+    //
+    // NOTE:  For CMP systems; this table is not loaded unless
+    //        the required driver support is present.
+    //        So, we do not check for those cases here.
+    //
+    // CFGD[0]  = EIST Capable/Enabled
+    // PDCx[0]  = OS Capable of Hardware P-State control
+    //
+    Method(_PCT,0)
+    {
+      // Update the _PPC value
+      //
+      Store (0x00, \_PR.CPU0._PPC)
+
+      If (LAnd(And(\_PR.CFGD,0x0001), And(PDC0,0x0001))) {
+        Return(Package()  // Native Mode
+        {
+          ResourceTemplate(){Register(FfixedHW, 0, 0, 0)},
+          ResourceTemplate(){Register(FfixedHW, 0, 0, 0)}
+        })
+      }
+      // For all other cases, report control through the
+      // SMI interface.  (The port used for SMM control is fixed up
+      // by the initialization code.)
+      //
+      Return(Package()        // SMM Mode
+      {
+        ResourceTemplate(){Register(FfixedHW, 0, 0, 0)},
+        ResourceTemplate(){Register(FfixedHW, 0, 0, 0)}
+      })
+    }
+
+    Method(_PSS,0)
+    {
+      // OSSL means OS Selection, WOS is Zero, AOS is One
+      If (LEqual(OSSL, 1)) {
+        Return(SPSS)    // PSS entry for AOS
+      } else {
+        Return(NPSS)    // PSS entry for WOS
+      }
+    }
+
+    Name(NPSS,Package()
+    {
+      Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
+      Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
+      Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
+      Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
+      Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
+      Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
+      Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
+      Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
+      Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
+      Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
+      Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
+      Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
+      Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
+      Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
+      Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
+      Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
+      Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
+      Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
+      Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
+      Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000}
+    })
+
+    Name(SPSS,Package()
+    {
+      Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
+      Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
+      Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
+      Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
+      Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
+      Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
+      Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
+      Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
+      Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
+      Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
+      Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
+      Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
+      Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
+      Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
+      Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
+      Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
+      Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
+      Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
+      Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
+      Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000}
+    })
+
+    Method(_PSD,0)
+    {
+      Return(Package() {    // HW_ALL
+        Package() {
+          5,              // # entries.
+          0,              // Revision.
+          0,              // Domain #.
+          0xFE,           // Coord Type- HW_ALL.
+          NLPC            // # processors.
+        }
+      })
+    }
+  }
+} // End of Definition Block
+
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/AcpiTables/CpuSsdt/Cpu0Tst.asl b/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/AcpiTables/CpuSsdt/Cpu0Tst.asl
new file mode 100644
index 0000000000..93ffa31dc1
--- /dev/null
+++ b/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/AcpiTables/CpuSsdt/Cpu0Tst.asl
@@ -0,0 +1,249 @@
+/** @file
+  Intel Processor Power Management ACPI Code.
+
+  Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved.<BR>
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php.
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "CpuPowerMgmt.h"
+
+DefinitionBlock(
+  "CPU0TST.aml",
+  "SSDT",
+  0x02,
+  "PmRef",
+  "Cpu0Tst",
+  0x3000
+  )
+{
+  External(\_PR.CPU0, DeviceObj)
+  External(PDC0)
+  External(\_PR.CFGD, IntObj)
+  External(_PSS)
+  External (NLPC)
+
+  Scope(\_PR.CPU0)
+  {
+    Name(_TPC, 0)  // All T-States are available
+
+    //
+    // T-State Control/Status interface
+    //
+    Method(_PTC, 0)
+    {
+      //
+      // IF OSPM is capable of direct access to MSR
+      //    Report MSR interface
+      // ELSE
+      //    Report I/O interface
+      //
+      //  PDCx[2] = OSPM is capable of direct access to On
+      //    Demand throttling MSR
+      //
+      If (And(PDC0, 0x0004)) {
+        Return(Package() {
+          ResourceTemplate(){Register(FFixedHW, 0, 0, 0)},
+          ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}
+        })
+      }
+
+      Return(Package() {
+        ResourceTemplate(){Register(SystemIO, 5, 0, 0x1810)},
+        ResourceTemplate(){Register(SystemIO, 5, 0, 0x1810)}
+      })
+    }
+
+    //
+    // _TSS package for fine-grained T-State control.
+    // "Power" fields are replaced with real values by the first
+    // call of _TSS method.
+    //
+    Name(TSMF, Package() {
+        Package(){100, 1000, 0, 0x00, 0},
+        Package(){ 94,  940, 0, 0x1F, 0},
+        Package(){ 88,  880, 0, 0x1E, 0},
+        Package(){ 82,  820, 0, 0x1D, 0},
+        Package(){ 75,  760, 0, 0x1C, 0},
+        Package(){ 69,  700, 0, 0x1B, 0},
+        Package(){ 63,  640, 0, 0x1A, 0},
+        Package(){ 57,  580, 0, 0x19, 0},
+        Package(){ 50,  520, 0, 0x18, 0},
+        Package(){ 44,  460, 0, 0x17, 0},
+        Package(){ 38,  400, 0, 0x16, 0},
+        Package(){ 32,  340, 0, 0x15, 0},
+        Package(){ 25,  280, 0, 0x14, 0},
+        Package(){ 19,  220, 0, 0x13, 0},
+        Package(){ 13,  160, 0, 0x12, 0},
+        Package(){  7,  100, 0, 0x11, 0}
+    })
+
+    //
+    // _TSS package for T-State control (Coarse grained)
+    // "Power" fields are replaced with real values by the first
+    // call of _TSS method.
+    //
+    Name(TSMC, Package() {
+        Package(){100, 1000, 0, 0x00, 0},
+        Package(){ 88,  875, 0, 0x1E, 0},
+        Package(){ 75,  750, 0, 0x1C, 0},
+        Package(){ 63,  625, 0, 0x1A, 0},
+        Package(){ 50,  500, 0, 0x18, 0},
+        Package(){ 38,  375, 0, 0x16, 0},
+        Package(){ 25,  250, 0, 0x14, 0},
+        Package(){ 13,  125, 0, 0x12, 0}
+    })
+
+    Name(TSSF, 0)  // Flag for TSIF/TSIC/TSMF/TSMC initialization
+    Mutex(TSMO, 0) // Mutex object to ensure the _TSS initalization code is only executed once
+
+    Name (DTST, "_TSS :")
+
+    Method(_TSS, 0, Serialized)
+    {
+      //
+      // Update "Power" fields of TSIC or TSIF or TSMC or TSMF with the LFM
+      // power data IF _PSS is available
+      //    Power caluclation:
+      //               n - Number of T-states available
+      //              _TSS(x).power = LFM.Power * (n-x)/n
+      //
+      IF (LAnd(LNot(TSSF),CondRefOf(_PSS))) {
+        //
+        // Acquire Mutex to make sure the initialization happens only once.
+        //
+        Acquire (TSMO, 0xFFFF)
+        //
+        // Only one thread will be able to acquire the mutex at a time, but the other threads which have acquired the mutex previously, will eventually try to execute the TSS initalization code.
+        // So, let's check if TSS has already been initalized once again. If its initalized, skip the initalization.
+        //
+        IF (LAnd(LNot(TSSF),CondRefOf(_PSS))) {
+          Name (LFMI, 0)
+          Store (_PSS, Local0)
+          Store (SizeOf(Local0), LFMI)
+          Decrement(LFMI)    // Index of LFM entry in _PSS
+          Name (LFMP, 0) //LFM Power from _PSS
+          Store (DerefOf(Index(DerefOf(Index(Local0,LFMI)),1)) , LFMP)
+          Store (0, Local0)
+
+          //
+          // Copy reference of appropiate TSS package based on Fine grained T-state support
+          // We'll update the power in the package directly (via the reference variable Local1)
+          //
+          // If Fine Grained T-states is enabled
+          //      TSMF
+          //    ELSE
+          //      TSMC
+          //
+          If (And(\_PR.CFGD,PPM_TSTATE_FINE_GRAINED)) {
+            Store (RefOf(TSMF), Local1)
+            Store (SizeOf(TSMF),Local2)
+          } Else {
+            Store (RefOf(TSMC), Local1)
+            Store (SizeOf(TSMC),Local2)
+          }
+
+          While (LLess(Local0, Local2)) {
+            Store(Divide(Multiply(LFMP, Subtract(Local2, Local0)), Local2),
+                  Local4)    // Power for this entry
+            Store(Local4,Index(DerefOf(Index(DerefOf(Local1),Local0)),1))
+            Increment(Local0)
+          }
+
+          Store(Ones, TSSF)    // Set flag to indicate TSS table initalization is complete
+        }
+
+        Release (TSMO)
+
+      }
+      //
+      //  If Fine Grained T-states is enabled
+      //    Report TSMF
+      //  ELSE
+      //    Report TSMC
+      //
+      If (And(\_PR.CFGD, PPM_TSTATE_FINE_GRAINED)) {
+
+        Store (DTST, Debug)
+        Store (TSMF, Debug)
+
+        Return(TSMF)
+      } Else {
+
+        Store (DTST, Debug)
+        Store (TSMC, Debug)
+
+        Return(TSMC)
+      }
+    }
+
+    //
+    // _TDL (T-state Depth Limit)
+    //
+    // This optional object evaluates to the _TSS entry number of the lowest power throttling state that OSPM may use.
+    //
+    // Arguments: (0)
+    //   None
+    // Return Value:
+    //   An Integer containing the Throttling Depth Limit _TSS entry number:
+    //   0 - throttling disabled.
+    //   1 - state 1 is the lowest power T-state available.
+    //   2 - state 2 is the lowest power T-state available.
+    //   ...
+    //   n - state n is the lowest power T-state available.
+    //
+    Method(_TDL, 0)
+    {
+      Store ("Cpu0: _TDL Called", Debug)
+      If (And(\_PR.CFGD, PPM_TSTATE_FINE_GRAINED)) {
+        Return(Subtract(SizeOf(TSMF),1))
+      } Else {
+        Return(Subtract(SizeOf(TSMC),1))
+      }
+    }
+
+    //
+    // T-State Dependency
+    //
+    Method(_TSD, 0)
+    {
+      //
+      // IF !(direct access to MSR)
+      //    Report SW_ANY as the coordination type
+      // ELSE
+      //   Report SW_ALL as the coordination type
+      //
+      //  PDCx[2] = OSPM is capable of direct access to On
+      //    Demand throttling MSR
+      //
+      If (LNot(And(PDC0,4))) {
+        Return(Package() {     // SW_ANY
+          Package(){
+            5,                // # entries.
+            0,                // Revision.
+            0,                // Domain #.
+            0xFD,             // Coord Type- SW_ANY
+            NLPC              // # processors.
+          }
+        })
+      }
+      Return(Package() {       // SW_ALL
+        Package(){
+          5,                  // # entries.
+          0,                  // Revision.
+          0,                  // Domain #.
+          0xFC,               // Coord Type- SW_ALL
+          1                   // # processors.
+        }
+      })
+    }
+  }
+} // End of Definition Block
+
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/AcpiTables/CpuSsdt/CpuSsdt.asl b/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/AcpiTables/CpuSsdt/CpuSsdt.asl
new file mode 100644
index 0000000000..d57092e2fb
--- /dev/null
+++ b/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/AcpiTables/CpuSsdt/CpuSsdt.asl
@@ -0,0 +1,694 @@
+/** @file
+  Intel Processor SSDT ACPI Code.
+
+  Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved.<BR>
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php.
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "CpuPowerMgmt.h"
+
+DefinitionBlock (
+  "CPUSSDT.aml",
+  "SSDT",
+  0x02,
+  "CpuRef",
+  "CpuSsdt",
+  0x3000
+  )
+{
+  External(\_PR.CPU0, DeviceObj)
+  External(\_PR.CPU1, DeviceObj)
+  External(\_PR.CPU2, DeviceObj)
+  External(\_PR.CPU3, DeviceObj)
+  External(\_PR.CPU0._PPC, IntObj)
+
+Scope(\)
+{
+  // Package of pointers to SSDT's
+  //
+  // First column is SSDT name, used for debug only.
+  // (First column must be EXACTLY eight characters.)
+  // Second column is physical address.
+  // Third column is table length.
+  //
+  // IF modifying this file, see warnings listed in ppminit.asm.
+  //
+  Name(SSDT,Package()
+  {
+    "CPU0IST ", 0x80000000, 0x80000000,
+    "APIST   ", 0x80000000, 0x80000000,
+    "CPU0CST ", 0x80000000, 0x80000000,
+    "APCST   ", 0x80000000, 0x80000000
+  })
+
+  Name(\PDC0,0x80000000)  // CPU0 _PDC Flags.
+  Name(\PDC1,0x80000000)  // CPU1 _PDC Flags.
+  Name(\PDC2,0x80000000)  // CPU2 _PDC Flags.
+  Name(\PDC3,0x80000000)  // CPU3 _PDC Flags.
+
+  Name(\SDTL,0x00)        // Loaded SSDT Flags.
+  // SDTL[1]   = CPU0 CST SSDT Loaded
+  // SDTL[3]   = CPU0 IST SSDT Loaded
+  // SDTL[4]   = AP IST SSDT Loaded
+  // SDTL[5]   = AP CST SSDT Loaded
+  // SDTL[6]   = Cpu0Hwp SSDT Loaded
+  // SDTL[7]   = Ap0Hwp SSDT Loaded
+}
+
+Scope(\_PR)
+{
+  //
+  // Define a Processor scope ACPI PPM GlobalNvs NVS Region
+  //
+  OperationRegion(PNVS,SystemMemory,0xFFFF0000,0xAA55)
+  Field(PNVS,AnyAcc,Lock,Preserve)
+  {
+    PGRV,       8,      // (0) CPU GlobalNvs Revision
+    //
+    // PPM Flags Values
+    //
+    CFGD,    32,       // CFGD - PpmFlags
+    //
+    // Number of Logical Processors Values
+    //
+    NLPC,    8,        // (5) Number of Logical Processors
+    //
+    // Thermal Configuration Values
+    //
+    ACRT,    8,        // (6) Auto Critical Trip Point
+    APSV,    8,        // (7) Auto Passive Trip Point
+    AAC0,    8,        // (8) Auto Active Trip Point
+    CPID,    32,       // (9-12) CPUID
+                       //
+                       // (13-40) Reserved
+                       //
+    Offset(41),
+    //
+    // Mwait Hints and Latency values for C3/C6/C7/C7S
+    //
+    C3MW,    8,        // (41) Mwait Hint value for C3
+    C6MW,    8,        // (42) Mwait Hint value for C6
+    C7MW,    8,        // (43) Mwait Hint value for C7/C7s
+    CDMW,    8,        // (44) Mwait Hint value for C8/C9/C10
+    C3LT,   16,        // (45-46) Latency value for C3
+    C6LT,   16,        // (47-48) Latency Value for C6
+    C7LT,   16,        // (49-50) Latency Value for C7/C7S
+    CDLT,   16,        // (51-52) Latency Value for C8/C9/C10
+    CDLV,   16,        // (53-54) IO LVL value for C8/C9/C10
+    CDPW,   16,        // (55-56) Power value for C8/C9/C10
+    MPMF,   8,         // (57) MiscPowerManagementFlags
+    //
+    // DTS
+    //
+    DTSE,   8,         // (58) Digital Thermal Sensor Enable
+    DTS1,   8,         // (59) Digital Thermal Sensor 1 Reading
+    DTS2,   8,         // (60) Digital Thermal Sensor 2 Reading
+    DTSF,   8,         // (61) DTS SMI Function Call
+    PDTS,   8,         // (62) Package Temperature
+    PKGA,   8,         // (63) Package Temperature MSR available
+    DTS3,   8,         // (64) Digital Thermal Sensor 3 Reading
+    DTS4,   8,         // (65) Digital Thermal Sensor 4 Reading
+                       //
+                       // (66-82) Reserved
+                       //
+    Offset(83),
+    //
+    // SGX
+    //
+    EPCS, 8,           // (83) SGX Status
+    EMNA, 64,          // (84-91) EPC Base Address
+    ELNG, 64,          // (92-99) EPC Length
+    //
+    // HWP
+    //
+    HWPV, 8,           // (100) HWP Version
+    HWPA, 16,          // (101-102) IoTrap Address for HWP
+    HWPL, 16,          // (103-104) IoTrap Length for HWP
+    POWS, 8,           // (105) Power State
+    HDCE, 8,           // (106) Hardware Duty Cycling Policy
+    HWPI, 8,           // (107) HWP Interrupt Status
+    MWEN, 8            // (108) Mwait Enable
+  }
+}
+
+Scope(\_PR.CPU0)
+{
+  //
+  // Define handles for opregions (used by load.)
+  //
+  Name(HI0,0)    // Handle to CPU0IST
+  Name(HC0,0)    // Handle to CPU0CST
+
+  Method(_PDC,1)
+  {
+    //
+    // Check and extract the _PDC information.
+    //
+    Store(CPDC(Arg0), Local0)
+    //
+    // Save the capability information and load tables as needed.
+    //
+    GCAP(Local0)
+  }
+
+  Method(_OSC, 4)
+  {
+    //
+    // Check and extract the _OSC information.
+    //
+    Store(COSC(Arg0, Arg1, Arg2, Arg3), Local0)
+    //
+    // Save the capability information and load tables as needed.
+    //
+    GCAP(Local0)
+    //
+    // Return status.
+    //
+    Return (Local0)
+  }
+
+  //
+  // Implement a generic Method to check _PDC information which may be called
+  // by any of the processor scopes.  (The use of _PDC is deprecated in ACPI 3.
+  // in favor of _OSC. However, for backwards compatibility, _PDC may be
+  // implemented using _OSC as follows:)
+  //
+  Method(CPDC,1, Serialized)
+  {
+    CreateDwordField (Arg0, 0, REVS)
+    CreateDwordField (Arg0, 4, SIZE)
+
+    //
+    // Local0 = Number of bytes for Arg0
+    //
+    Store (SizeOf (Arg0), Local0)
+
+    //
+    // Local1 = Number of Capabilities bytes in Arg0
+    //
+    Store (Subtract (Local0, 8), Local1)
+
+    //
+    // TEMP = Temporary field holding Capability DWORDs
+    //
+    CreateField (Arg0, 64, Multiply (Local1, 8), TEMP)
+
+    //
+    // Create the Status (STAT) buffer with the first DWORD = 0
+    // This is required as per ACPI 3.0 Spec which says the
+    // first DWORD is used to return errors defined by _OSC.
+    //
+    Name (STS0, Buffer () {0x00, 0x00, 0x00, 0x00})
+
+    //
+    // Concatenate the _PDC capabilities bytes to the STS0 Buffer
+    // and store them in a local variable for calling OSC
+    //
+    Concatenate (STS0, TEMP, Local2)
+
+    Return(COSC (ToUUID("4077A616-290C-47BE-9EBD-D87058713953"), REVS, SIZE, Local2))
+  }
+
+  //
+  // Implement a generic Method to check _OSC information which may be called by any of the processor scopes.
+  //
+  // Arguments: (4)
+  //   Arg0 - A Buffer containing a UUID
+  //   Arg1 - An Integer containing a Revision ID of the buffer format
+  //   Arg2 - An Integer containing a count of entries in Arg3
+  //   Arg3 - A Buffer containing a list of DWORD capabilities
+  // Return Value:
+  //   A Buffer containing a list of capabilities
+  //
+  Method(COSC, 4,Serialized,,BuffObj,{BuffObj,IntObj,IntObj,BuffObj})
+  {
+    //
+    // Point to Status DWORD in the Arg3 buffer (STATUS)
+    //
+    If (LGreater(Arg2,0)) {
+      CreateDWordField(Arg3, 0, STS0)
+    }
+
+    //
+    // _OSC needs to validate the UUID and Revision.
+    //
+    // IF Unrecognized UUID
+    //  Return Unrecognized UUID _OSC Failure
+    // IF Unsupported Revision
+    //  Return Unsupported Revision _OSC Failure
+    //
+    //    STS0[0] = Reserved
+    //    STS0[1] = _OSC Failure
+    //    STS0[2] = Unrecognized UUID
+    //    STS0[3] = Unsupported Revision
+    //    STS0[4] = Capabilities masked
+    //
+    // Note:  The comparison method used is necessary due to
+    // limitations of certain OSes which cannot perform direct
+    // buffer comparisons.
+    //
+    // Create a set of "Input" UUID fields.
+    //
+    CreateDwordField(Arg0, 0x0, IID0)
+    CreateDwordField(Arg0, 0x4, IID1)
+    CreateDwordField(Arg0, 0x8, IID2)
+    CreateDwordField(Arg0, 0xC, IID3)
+    //
+    // Create a set of "Expected" UUID fields.
+    //
+    Name(UID0, ToUUID("4077A616-290C-47BE-9EBD-D87058713953"))
+    CreateDwordField(UID0, 0x0, EID0)
+    CreateDwordField(UID0, 0x4, EID1)
+    CreateDwordField(UID0, 0x8, EID2)
+    CreateDwordField(UID0, 0xC, EID3)
+    //
+    // Verify the input UUID matches the expected UUID.
+    //
+    If (LNot(LAnd(LAnd(LEqual(IID0, EID0),LEqual(IID1, EID1)),LAnd(LEqual(IID2, EID2),LEqual(IID3, EID3))))) {
+      //
+      // Return Unrecognized UUID _OSC Failure
+      //
+      Store (0x6, STS0)
+      Return (Arg3)
+    }
+
+    If (LNot(LEqual(Arg1,1))) {
+      //
+      // Return Unsupported Revision _OSC Failure
+      //
+      Store (0xA, STS0)
+      Return (Arg3)
+    }
+
+    Return (Arg3)
+  }
+
+  //
+  // Get the capability information and load appropriate tables as needed.
+  //
+  Method(GCAP, 1, Serialized)
+  {
+    //Name(HI0,0)    // Handle to Cpu0IST
+
+    //
+    // Point to Status DWORD in the Arg0 buffer (STATUS)
+    //
+    CreateDWordField(Arg0, 0, STS0)
+    //
+    // Point to Caps DWORDs of the Arg0 buffer (CAPABILITIES)
+    //
+    CreateDwordField(Arg0, 4, CAP0)
+
+    //
+    // If the UUID was unrecognized or the _OSC revision was unsupported,
+    // return without updating capabilities.
+    //
+    If (LOr(LEqual(STS0,0x6),LEqual(STS0,0xA))) {
+      Return()
+    }
+
+    //
+    // Check if this is a query (BIT0 of Status = 1).
+    // If so, mask off the bits we support and return.
+    //
+    if (And(STS0, 1)) {
+      And(CAP0, 0xBFF, CAP0)
+      Return()
+    }
+
+    //
+    // Store result of PDC. (We clear out the MSB, which was just
+    // used as a placeholder for the compiler; and then "OR" the
+    // value in case we get multiple calls, each of which only
+    // reports partial support.)
+    //
+    Or(And(PDC0, 0x7FFFFFFF), CAP0, PDC0)
+
+    //
+    // Check IF the CST SSDTs should be loaded.
+    //   CFGD[5:1] = C7, C6, C3, C1E, C1 Capable/Enabled
+    If (And(CFGD, 0x02)) {
+      //
+      // Load the CST SSDTs if:
+      //   (1) CMP capable/enabled
+      //   (2) Driver supports multi-processor configurations
+      //   (3) CPU0 CST ISDT is not already loaded
+      //
+      //   CFGD[9] = Two or more cores enabled
+      //   PDCx[3]  = OS supports C1 and P-states in MP systems
+      //   PDCx[4]  = OS supports ind. C2/C3 in MP systems
+      //   SDTL[1]  = CPU0 CST SSDT Loaded
+      //
+      If (LAnd(LAnd(And(CFGD, 0x02),And(PDC0,0x0018)),LNot(And(SDTL,0x02)))) {
+        //
+        // Flag the CST SSDT as loaded for CPU0
+        //
+        Or(SDTL, 0x02, SDTL)
+
+        OperationRegion(CST0,SystemMemory,DeRefOf(Index(SSDT,7)),DeRefOf(Index(SSDT,8)))
+        Load(CST0, HC0)  // Dynamically load the CPU0CST SSDT
+      }
+    }
+
+    // Load the IST SSDTs if:
+    //   (1) CMP capable/enabled
+    //   (2) HWP not capable or enabled
+    //   (3) Driver supports multi-processor configurations
+    //   (4) CPU0 IST SSDT is not already loaded
+    //
+    //   CFGD[0]  = EIST Capable/Enabled
+    //   CFGD[22] = HWP not capable or enabled
+    //   SDTL[3]  = CPU0 IST SSDT Loaded
+    //
+    If (LAnd(LNot(And(CFGD, 0x01)),LAnd(And(CFGD,0x01),LNot(And(SDTL,0x08))))) {
+      //
+      // Flag the IST SSDT as loaded for CPU0
+      //
+      Or(SDTL, 0x08, SDTL)
+
+      OperationRegion(IST0,SystemMemory,DeRefOf(Index(SSDT,1)),DeRefOf(Index(SSDT,2)))
+      Load(IST0, HI0)  // Dynamically load the CPU1IST SSDT
+    }
+
+    Return ()
+  }
+}
+
+
+Scope(\_PR.CPU1)
+{
+  //
+  // Define handles for opregions (used by load.)
+  //
+  Name(HI1,0)    // Handle to APIST
+  Name(HC1,0)    // Handle to APCST
+  Name(HW1,0)    // Handle to APHWP
+
+  Method(_PDC,1)
+  {
+    //
+    // Refer to \_PR.CPU0._PDC for description.
+    //
+    Store(\_PR.CPU0.CPDC(Arg0), Local0)
+    GCAP(Local0)
+  }
+
+  Method(_OSC, 4)
+  {
+    //
+    // Refer to \_PR.CPU0._OSC for description.
+    //
+    Store(\_PR.CPU0.COSC(Arg0, Arg1, Arg2, Arg3), Local0)
+    GCAP(Local0)
+    Return (Local0)
+  }
+
+  //
+  // Get the capability information and load appropriate tables as needed.
+  //
+  Method(GCAP, 1)
+  {
+    //
+    // Point to Status DWORD in the Arg0 buffer (STATUS)
+    //
+    CreateDWordField(Arg0, 0, STS1)
+    //
+    // Point to Caps DWORDs of the Arg0 buffer (CAPABILITIES)
+    //
+    CreateDwordField(Arg0, 4, CAP1)
+    //
+    // If the UUID was unrecognized or the _OSC revision was unsupported,
+    // return without updating capabilities.
+    //
+    If (LOr(LEqual(STS1,0x6),LEqual(STS1,0xA))) {
+      Return()
+    }
+
+    //
+    // Check if this is a query (BIT0 of Status = 1).
+    // If so, mask off the bits we support and return.
+    //
+    if (And(STS1, 1)) {
+      And(CAP1, 0xBFF, CAP1)
+      Return()
+    }
+
+    //
+    // Store result of PDC. (We clear out the MSB, which was just
+    // used as a placeholder for the compiler; and then "OR" the
+    // value in case we get multiple calls, each of which only
+    // reports partial support.)
+    //
+    Or(And(PDC1, 0x7FFFFFFF), CAP1, PDC1)
+
+    //
+    // Attempt to dynamically load the IST SSDTs if:
+    //   (1) Driver supports P-States in MP configurations
+    //   (2) Driver supports direct HW P-State control
+    //
+    //   PDCx[3]  = OS supports C1 and P-states in MP systems
+    //   PDCx[0]  = OS supports direct access of the perf MSR
+    //
+    If (LEqual(And(PDC1, 0x0009), 0x0009)) {
+      APPT()
+    }
+
+    //
+    // Load Ap0Hwp SSDT
+    // PDCx[5]   = OS supports CPPC from OSPM
+    //
+    // if(And(PDC1,0x0020)) {
+    //    HWPT()
+    //  }
+    //
+    // Load the CST SSDTs if:
+    //   (1) Driver supports multi-processor configurations
+    //
+    //   PDCx[3]  = OS supports C1 and P-states in MP systems
+    //   PDCx[4]  = OS supports ind. C2/C3 in MP systems
+    //
+    If (And(PDC1,0x0018)) {
+      APCT()
+    }
+
+    Store (PDC1, PDC0)
+
+    Return()
+  }
+
+  //
+  // Dynamically load the CST SSDTs if:
+  //   (1) C-States are enabled
+  //   (2) SSDT is not already loaded
+  //
+  //   CFGD[5:1] = Basic C-States supported (C1, C1E, C3, C6, C7)
+  //   SDTL[5]   = AP CST SSDT Loaded
+  //
+  Method(APCT,0, Serialized)
+  {
+    If (LAnd(And(CFGD,0x02),LNot(And(SDTL,0x20)))) {
+      //
+      // Flag the CST SSDT as loaded for the AP's
+      //
+      Or(SDTL, 0x20, SDTL)
+      //
+      // Dynamically load the APCST SSDT
+      //
+      OperationRegion(CST1,SystemMemory,DeRefOf(Index(SSDT,10)),DeRefOf(Index(SSDT,11)))
+      Load(CST1, HC1)
+    }
+  }
+
+  //
+  // Dynamically load the IST SSDTs if:
+  //   (1) If EIST capable and enabled
+  //   (2) SSDT is not already loaded
+  //
+  //   CFGD[0] = EIST Capable/Enabled
+  //   SDTL[4] = AP IST SSDT Loaded
+  //
+  Method(APPT,0, Serialized)
+  {
+    If (LAnd(And(CFGD,0x01),LNot(And(SDTL,0x10)))) {
+      //
+      // Flag the IST SSDT as loaded for CPU0
+      //
+      Or(SDTL, 0x10, SDTL)
+
+      OperationRegion(IST1,SystemMemory,DeRefOf(Index(SSDT,4)),DeRefOf(Index(SSDT,5)))
+      Load(IST1, HI1)  // Dynamically load the CPU1IST SSDT
+    }
+  }
+}  // End CPU1
+
+
+Scope(\_PR.CPU2)
+{
+  Method(_PDC,1)
+  {
+    //
+    // Call the _PDC for CPU1.
+    //
+    Store(\_PR.CPU0.CPDC(Arg0), Local0)
+    GCAP(Local0)
+  }
+
+  Method(_OSC, 4)
+  {
+    //
+    // Call the _OSC for CPU1.
+    //
+    Store(\_PR.CPU0.COSC(Arg0, Arg1, Arg2, Arg3), Local0)
+    GCAP(Local0)
+    Return (Local0)
+  }
+
+  Method(GCAP,1)
+  {
+    // Point to Status DWORD in the Arg0 buffer (STATUS)
+    CreateDWordField(Arg0, 0, STS2)
+
+    // Point to Caps DWORDs of the Arg0 buffer (CAPABILITIES)
+    CreateDwordField(Arg0, 4, CAP2)
+
+    //
+    // If the UUID was unrecognized or the _OSC revision was unsupported,
+    // return without updating capabilities.
+    //
+    If (LOr(LEqual(STS2,0x6),LEqual(STS2,0xA))) {
+      Return()
+    }
+
+    //
+    // Check if this is a query (BIT0 of Status = 1).
+    // If so, mask off the bits we support and return.
+    //
+    if (And(STS2, 1)) {
+      And(CAP2, 0xBFF, CAP2)
+      Return()
+    }
+
+    //
+    // Store result of PDC. (We clear out the MSB, which was just
+    // used as a placeholder for the compiler; and then "OR" the
+    // value in case we get multiple calls, each of which only
+    // reports partial support.)
+    //
+    Or(And(PDC2, 0x7FFFFFFF), CAP2, PDC2)
+    //
+    // Attempt to dynamically load the IST SSDTs if:
+    //   (1) Driver supports P-States in MP configurations
+    //   (2) Driver supports direct HW P-State control
+    //
+    //   PDCx[3]  = OS supports C1 and P-states in MP systems
+    //   PDCx[0]  = OS supports direct access of the perf MSR
+    //
+    If (LEqual(And(PDC2, 0x0009), 0x0009)) {
+      \_PR.CPU1.APPT()
+    }
+
+    //
+    // Load the CST SSDTs if:
+    //   (1) Driver supports multi-processor configurations
+    //
+    //   PDCx[3]  = OS supports C1 and P-states in MP systems
+    //   PDCx[4]  = OS supports ind. C2/C3 in MP systems
+    //
+    If (And(PDC2,0x0018)) {
+      \_PR.CPU1.APCT()
+    }
+
+    Store (PDC2, PDC0)
+    Return()
+  }
+}  // End CPU2
+
+Scope(\_PR.CPU3)
+{
+  Method(_PDC,1)
+  {
+    //
+    // Call the _PDC for CPU1.
+    //
+    Store(\_PR.CPU0.CPDC(Arg0), Local0)
+    GCAP(Local0)
+  }
+
+  Method(_OSC, 4)
+  {
+    //
+    // Call the _OSC for CPU1.
+    //
+    Store(\_PR.CPU0.COSC(Arg0, Arg1, Arg2, Arg3), Local0)
+    GCAP(Local0)
+    Return (Local0)
+  }
+
+  Method(GCAP,1)
+  {
+    // Point to Status DWORD in the Arg0 buffer (STATUS)
+    CreateDWordField(Arg0, 0, STS3)
+
+    // Point to Caps DWORDs of the Arg0 buffer (CAPABILITIES)
+    CreateDwordField(Arg0, 4, CAP3)
+
+    //
+    // If the UUID was unrecognized or the _OSC revision was unsupported,
+    // return without updating capabilities.
+    //
+    If (LOr(LEqual(STS3,0x6),LEqual(STS3,0xA))) {
+      Return()
+    }
+
+    //
+    // Check if this is a query (BIT0 of Status = 1).
+    // If so, mask off the bits we support and return.
+    //
+    if (And(STS3, 1)) {
+      And(CAP3, 0xBFF, CAP3)
+      Return()
+    }
+
+    //
+    // Store result of PDC. (We clear out the MSB, which was just
+    // used as a placeholder for the compiler; and then "OR" the
+    // value in case we get multiple calls, each of which only
+    // reports partial support.)
+    //
+    Or(And(PDC3, 0x7FFFFFFF), CAP3, PDC3)
+    //
+    // Attempt to dynamically load the IST SSDTs if:
+    //   (1) Driver supports P-States in MP configurations
+    //   (2) Driver supports direct HW P-State control
+    //
+    //   PDCx[3]  = OS supports C1 and P-states in MP systems
+    //   PDCx[0]  = OS supports direct access of the perf MSR
+    //
+    If (LEqual(And(PDC3, 0x0009), 0x0009)) {
+      \_PR.CPU1.APPT()
+    }
+    //
+    // Load the CST SSDTs if:
+    //   (1) Driver supports multi-processor configurations
+    //
+    //   PDCx[3]  = OS supports C1 and P-states in MP systems
+    //   PDCx[4]  = OS supports ind. C2/C3 in MP systems
+    //
+    If (And(PDC3,0x0018)) {
+      \_PR.CPU1.APCT()
+    }
+
+    Store (PDC3, PDC0)
+    Return()
+  }
+} // End CPU3
+} // End of Definition Block
+
author	Guo Mang <mang.guo@intel.com>	2016-12-23 10:44:35 +0800
committer	Guo Mang <mang.guo@intel.com>	2016-12-26 19:15:03 +0800
commit	53c716058fdca56a2c82efdb4011a84f6eae5746 (patch)
tree	00cf5ee4bca0212943da1a4355a496111899b851
parent	a674eea1c47a6aa0170b2beb07d4f2bbefc798e0 (diff)
download	edk2-platforms-53c716058fdca56a2c82efdb4011a84f6eae5746.tar.xz