diff options
| author | Guo Mang <mang.guo@intel.com> | 2016-06-02 13:39:57 +0800 |
|---|---|---|
| committer | Hao Wu <hao.a.wu@intel.com> | 2016-06-07 09:55:27 +0800 |
| commit | 5fdd3788f450c8c03cb4794ad7835c8f10deeccc (patch) | |
| tree | 5411ca426de49980154724b4869d08408e79016b | |
| parent | dad0b0a63c85b47075b1b9c1054ca33f14bb85d0 (diff) | |
| download | edk2-platforms-5fdd3788f450c8c03cb4794ad7835c8f10deeccc.tar.xz | |
ChvRefCodePkg: Add NorthCluster Include files.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Guo Mang <mang.guo@intel.com>
20 files changed, 2667 insertions, 0 deletions
diff --git a/ChvRefCodePkg/CherryViewSoc/NorthCluster/Include/Cherryview.h b/ChvRefCodePkg/CherryViewSoc/NorthCluster/Include/Cherryview.h new file mode 100644 index 0000000000..75c288bf67 --- /dev/null +++ b/ChvRefCodePkg/CherryViewSoc/NorthCluster/Include/Cherryview.h @@ -0,0 +1,84 @@ +/** @file
+ This header file provides common definitions just for Cherryview-SOC using to avoid including extra module's file.
+
+ Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _MC_H_INCLUDED_
+#define _MC_H_INCLUDED_
+//
+// Extended Configuration Base Address
+//
+#define EC_BASE 0xE0000000
+
+//
+// DEVICE 0 (Memory Controller Hub)
+//
+#define MC_BUS 0x00
+#define MC_DEV 0x00
+#define MC_DEV2 0x02
+#define MC_FUN 0x00
+#define MC_VID 0x8086
+#define MC_DID_OFFSET 0x2 //Device Identification
+#define MC_GGC_OFFSET 0x50 //GMCH Graphics Control Register
+
+// Message Bus Register Definitions
+#define CHV_MBR_READ_CMD 0x10000000
+#define CHV_MBR_WRITE_CMD 0x11000000
+
+//Common for Gunit/DISPIO/DFXLAKSEMORE/DISPCONT units
+#define CHV_MBR_GDISPIOREAD_CMD 0x00000000
+#define CHV_MBR_GDISPIOWRITE_CMD 0x01000000
+
+//Common for Smbus units
+#define CHV_SMB_REGREAD_CMD 0x04000000
+#define CHV_SMB_REGWRITE_CMD 0x05000000
+
+//Common for Punit/DFX/GPIONC/DFXSOC/DFXNC/DFXVISA/CCU units
+#define CHV_MBR_PDFXGPIODDRIOREAD_CMD 0x06000000
+#define CHV_MBR_PDFXGPIODDRIOWRITE_CMD 0x07000000
+
+//Msg Bus Registers
+#define MC_MCR 0x000000D0 //Cunit Message Control Register
+#define MC_MDR 0x000000D4 //Cunit Message Data Register
+#define MC_MCRX 0x000000D8 //Cunit Message Control Register Extension
+#define MC_MCRXX 0x000000DC //cunit Message Controller Register Extension 2
+
+#define MC_DEVEN_OFFSET 0x54 //Device Enable
+#define B_DEVEN_D2F0EN BIT3 // Internal Graphics Engine F0 Enable
+
+//smBiosMemory.c use this
+//PunitDriver.c
+#define MC_TSEGMB_OFFSET 0xAC //TSEG Memory Base
+
+
+//
+// Device 2 Register Equates
+//
+#define IGD_BUS 0x00
+#define IGD_DEV 0x02
+#define IGD_FUN_0 0x00
+#define IGD_FUN_1 0x01
+#define IGD_DEV_FUN (IGD_DEV << 3)
+#define IGD_BUS_DEV_FUN (MC_BUS << 8) + IGD_DEV_FUN
+#define IGD_VID 0x8086
+#define IGD_DID 0x22B0
+#define IGD_DID_C0 0x22B1
+#define IGD_MGGC_OFFSET 0x0050 //GMCH Graphics Control Register 0x50
+#define IGD_BSM_OFFSET 0x005C //Base of Stolen Memory
+#define IGD_SWSCI_OFFSET 0x00E0 //Software SCI 0xE0 2
+#define IGD_ASLE_OFFSET 0x00E4 //System Display Event Register 0xE4 4
+#define IGD_ASLS_OFFSET 0x00FC // ASL Storage
+#define IGD_DID_QS 0x0BE2 //RCOverride -a: Fix the DID error
+
+
+#endif
diff --git a/ChvRefCodePkg/CherryViewSoc/NorthCluster/Include/ChvAccess.h b/ChvRefCodePkg/CherryViewSoc/NorthCluster/Include/ChvAccess.h new file mode 100644 index 0000000000..a728c93c2b --- /dev/null +++ b/ChvRefCodePkg/CherryViewSoc/NorthCluster/Include/ChvAccess.h @@ -0,0 +1,416 @@ +/** @file
+ Macros to simplify and abstract the interface to PCI configuration.
+
+ Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _ChvAccess_H_INCLUDED_
+#define _ChvAccess_H_INCLUDED_
+
+#include "Cherryview.h"
+#include "ChvCommonDefinitions.h"
+#include <Library/IoLib.h>
+
+//
+// Memory Mapped IO access macros used by MSG BUS LIBRARY
+//
+#define MmioAddress( BaseAddr, Register ) \
+ ( (UINTN)BaseAddr + \
+ (UINTN)(Register) \
+ )
+
+//
+// UINT32
+//
+
+#define Mmio32Ptr( BaseAddr, Register ) \
+ ( (volatile UINT32 *)MmioAddress( BaseAddr, Register ) )
+
+#define Mmio32( BaseAddr, Register ) \
+ *Mmio32Ptr( BaseAddr, Register )
+
+#define Mmio32Or( BaseAddr, Register, OrData ) \
+ Mmio32( BaseAddr, Register ) = \
+ (UINT32) ( \
+ Mmio32( BaseAddr, Register ) | \
+ (UINT32)(OrData) \
+ )
+
+#define Mmio32And( BaseAddr, Register, AndData ) \
+ Mmio32( BaseAddr, Register ) = \
+ (UINT32) ( \
+ Mmio32( BaseAddr, Register ) & \
+ (UINT32)(AndData) \
+ )
+
+#define Mmio32AndThenOr( BaseAddr, Register, AndData, OrData ) \
+ Mmio32( BaseAddr, Register ) = \
+ (UINT32) ( \
+ ( Mmio32( BaseAddr, Register ) & \
+ (UINT32)(AndData) \
+ ) | \
+ (UINT32)(OrData) \
+ )
+
+//
+// UINT16
+//
+
+#define Mmio16Ptr( BaseAddr, Register ) \
+ ( (volatile UINT16 *)MmioAddress( BaseAddr, Register ) )
+
+#define Mmio16( BaseAddr, Register ) \
+ *Mmio16Ptr( BaseAddr, Register )
+
+#define Mmio16Or( BaseAddr, Register, OrData ) \
+ Mmio16( BaseAddr, Register ) = \
+ (UINT16) ( \
+ Mmio16( BaseAddr, Register ) | \
+ (UINT16)(OrData) \
+ )
+
+#define Mmio16And( BaseAddr, Register, AndData ) \
+ Mmio16( BaseAddr, Register ) = \
+ (UINT16) ( \
+ Mmio16( BaseAddr, Register ) & \
+ (UINT16)(AndData) \
+ )
+
+#define Mmio16AndThenOr( BaseAddr, Register, AndData, OrData ) \
+ Mmio16( BaseAddr, Register ) = \
+ (UINT16) ( \
+ ( Mmio16( BaseAddr, Register ) & \
+ (UINT16)(AndData) \
+ ) | \
+ (UINT16)(OrData) \
+ )
+
+//
+// UINT8
+//
+
+#define Mmio8Ptr( BaseAddr, Register ) \
+ ( (volatile UINT8 *)MmioAddress( BaseAddr, Register ) )
+
+#define Mmio8( BaseAddr, Register ) \
+ *Mmio8Ptr( BaseAddr, Register )
+
+#define Mmio8Or( BaseAddr, Register, OrData ) \
+ Mmio8( BaseAddr, Register ) = \
+ (UINT8) ( \
+ Mmio8( BaseAddr, Register ) | \
+ (UINT8)(OrData) \
+ )
+
+#define Mmio8And( BaseAddr, Register, AndData ) \
+ Mmio8( BaseAddr, Register ) = \
+ (UINT8) ( \
+ Mmio8( BaseAddr, Register ) & \
+ (UINT8)(AndData) \
+ )
+
+#define Mmio8AndThenOr( BaseAddr, Register, AndData, OrData ) \
+ Mmio8( BaseAddr, Register ) = \
+ (UINT8) ( \
+ ( Mmio8( BaseAddr, Register ) & \
+ (UINT8)(AndData) \
+ ) | \
+ (UINT8)(OrData) \
+ )
+
+//
+// MSG BUS API
+//
+
+#define MSG_BUS_ENABLED 0x000000F0
+#define MSGBUS_MASKHI 0xFFFFFF00
+#define MSGBUS_MASKLO 0x000000FF
+
+#define MESSAGE_BYTE_EN BIT4
+#define MESSAGE_WORD_EN BIT4 | BIT5
+#define MESSAGE_DWORD_EN BIT4 | BIT5 | BIT6 | BIT7
+
+#define SIDEBAND_OPCODE 0x78
+#define MEMREAD_OPCODE 0x00000000
+#define MEMWRITE_OPCODE 0x01000000
+
+#define MsgBusReadCmd(PortId) ((PortId == 0x06 || PortId == 0x12 || PortId == 0x10)? CHV_MBR_GDISPIOREAD_CMD : \
+((PortId == 0x04 || PortId == 0x13 || PortId == 0xA9 \
+||PortId == 0x0C )? CHV_MBR_PDFXGPIODDRIOREAD_CMD : CHV_MBR_READ_CMD))
+
+#define MsgBusWriteCmd(PortId) ((PortId == 0x06 || PortId == 0x12 || PortId == 0x10)? CHV_MBR_GDISPIOWRITE_CMD : \
+((PortId == 0x04 || PortId == 0x13 || PortId == 0xA9 \
+||PortId == 0x0C )? CHV_MBR_PDFXGPIODDRIOWRITE_CMD : CHV_MBR_WRITE_CMD))
+
+#define MsgBusCmd(PortId) \
+{ \
+ Mmio32( EC_BASE, MC_MCR ) = (UINT32)( (SIDEBAND_OPCODE << 24) | (PortId <<16)) ; \
+}
+
+#define MsgBusCmdWrite(PortId,Dbuff) \
+{ \
+ Mmio32( EC_BASE, MC_MDR ) = Dbuff; \
+ Mmio32( EC_BASE, MC_MCR ) = (UINT32)( (SIDEBAND_OPCODE << 24) | (PortId <<16)) ; \
+}
+//
+// UINT32
+//
+
+#define MsgBus32Read(PortId, Register, Dbuff) \
+{ \
+ Mmio32( EC_BASE, MC_MCRX) = ( (Register & MSGBUS_MASKHI)); \
+ Mmio32( EC_BASE, MC_MCR ) = (UINT32)( MsgBusReadCmd(PortId) | ((PortId) <<16) | ((Register & MSGBUS_MASKLO)<<8) | MESSAGE_DWORD_EN); \
+ (Dbuff) = (UINT32)Mmio32( EC_BASE, MC_MDR ); \
+}
+
+#define MsgBus32Write(PortId, Register,Dbuff) \
+{ \
+ Mmio32( EC_BASE, MC_MCRX) = ( (Register & MSGBUS_MASKHI)); \
+ Mmio32( EC_BASE, MC_MDR ) = Dbuff; \
+ Mmio32( EC_BASE, MC_MCR ) = (UINT32)( MsgBusWriteCmd(PortId) | ((PortId) <<16) | ((Register & MSGBUS_MASKLO)<<8) | MESSAGE_DWORD_EN); \
+}
+
+#define MsgBus32ReadEx( OPCODE, PORTID, Register, Dbuff, Bar, Dev, Func) \
+{ \
+ UINT8 Fid = ((Dev <<3) | (Func)) & 0xFF; \
+ UINT32 Temp32 = 0; \
+ Temp32 = (((Bar&0x7)<<8)|(Fid&0xff)); \
+ Mmio32( EC_BASE, MC_MCRXX) = Temp32; \
+ Mmio32( EC_BASE, MC_MCRX) = ( (Register & MSGBUS_MASKHI)); \
+ Mmio32( EC_BASE, MC_MCR ) = (UINT32)( (OPCODE << 24) | (PORTID << 16) | ((Register & MSGBUS_MASKLO) << 8) | MESSAGE_DWORD_EN); \
+ (Dbuff) = (UINT32)Mmio32( EC_BASE, MC_MDR ); \
+}
+
+#define MsgBus32WriteEx(OPCODE, PORTID, Register, Dbuff, Bar, Dev, Func) \
+{ \
+ UINT8 Fid = ((Dev <<3) | (Func)) & 0xFF; \
+ UINT32 Temp32 = 0; \
+ Temp32 = (((Bar&0x7)<<8)|(Fid&0xff)); \
+ Mmio32( EC_BASE, MC_MCRXX) = Temp32; \
+ Mmio32( EC_BASE, MC_MCRX) = ( (Register & MSGBUS_MASKHI)); \
+ Mmio32( EC_BASE, MC_MDR ) = Dbuff; \
+ Mmio32( EC_BASE, MC_MCR ) = (UINT32)( (OPCODE << 24) | (PORTID << 16) | ((Register & MSGBUS_MASKLO) << 8) | MESSAGE_DWORD_EN); \
+}
+
+#define GunitMsgBus32Read(PortId, Register, Dbuff) \
+{ \
+ Mmio32( EC_BASE + (2<<15), GUNIT_MCRX) = ( (Register & MSGBUS_MASKHI)); \
+ Mmio32( EC_BASE + (2<<15), GUNIT_MCR ) = (UINT32)( MsgBusReadCmd(PortId) | ((PortId) <<16) | ((Register & MSGBUS_MASKLO)<<8) | MESSAGE_DWORD_EN); \
+ (Dbuff) = (UINT32)Mmio32( EC_BASE + (2<<15), GUNIT_MDR ); \
+}
+
+#define GunitMsgBus32Write(PortId, Register,Dbuff) \
+{ \
+ Mmio32( EC_BASE + (2<<15), GUNIT_MCRX) = ( (Register & MSGBUS_MASKHI)); \
+ Mmio32( EC_BASE + (2<<15), GUNIT_MDR ) = Dbuff; \
+ Mmio32( EC_BASE + (2<<15), GUNIT_MCR ) = (UINT32)( MsgBusWriteCmd(PortId) | ((PortId) <<16) | ((Register & MSGBUS_MASKLO)<<8) | MESSAGE_DWORD_EN); \
+}
+
+#define MsgBus32Or(PortId, Register, Dbuff, OrData ) \
+{ \
+ Mmio32( EC_BASE, MC_MCRX) = ( (Register & MSGBUS_MASKHI)); \
+ Mmio32( EC_BASE, MC_MCR ) = (UINT32)( MsgBusReadCmd(PortId) | ((PortId) <<16) | ((Register & MSGBUS_MASKLO)<<8) | MESSAGE_DWORD_EN); \
+ (Dbuff) = (UINT32)Mmio32( EC_BASE, MC_MDR ); \
+ Mmio32( EC_BASE, MC_MCRX) = ( (Register & MSGBUS_MASKHI)); \
+ Mmio32( EC_BASE, MC_MDR ) = (Dbuff | OrData); \
+ Mmio32( EC_BASE, MC_MCR ) = (UINT32)( MsgBusWriteCmd(PortId) | ((PortId) <<16) | ((Register & MSGBUS_MASKLO)<<8) | MESSAGE_DWORD_EN); \
+}
+
+#define MsgBus32And(PortId, Register, Dbuff, AndData ) \
+{ \
+ Mmio32( EC_BASE, MC_MCRX) = ( (Register & MSGBUS_MASKHI)); \
+ Mmio32( EC_BASE, MC_MCR ) = (UINT32)( MsgBusReadCmd(PortId) | ((PortId) <<16) | ((Register & MSGBUS_MASKLO)<<8) | MESSAGE_DWORD_EN); \
+ (Dbuff) = (UINT32)Mmio32( EC_BASE, MC_MDR ); \
+ Mmio32( EC_BASE, MC_MCRX) = ( (Register & MSGBUS_MASKHI)); \
+ Mmio32( EC_BASE, MC_MDR ) = (Dbuff & AndData); \
+ Mmio32( EC_BASE, MC_MCR ) = (UINT32)( MsgBusWriteCmd(PortId) | ((PortId) <<16) | ((Register & MSGBUS_MASKLO)<<8) | MESSAGE_DWORD_EN); \
+}
+
+#define MsgBus32AndThenOr( PortId, Register, Dbuff, AndData, OrData ) \
+{ \
+ Mmio32( EC_BASE, MC_MCRX) = ( (Register & MSGBUS_MASKHI)); \
+ Mmio32( EC_BASE, MC_MCR ) = (UINT32)( MsgBusReadCmd(PortId) | ((PortId) <<16) | ((Register & MSGBUS_MASKLO)<<8) | MESSAGE_DWORD_EN); \
+ (Dbuff) = (UINT32)Mmio32( EC_BASE, MC_MDR ); \
+ Mmio32( EC_BASE, MC_MCRX) = ( (Register & MSGBUS_MASKHI)); \
+ Mmio32( EC_BASE, MC_MDR ) = ((Dbuff & AndData) | OrData); \
+ Mmio32( EC_BASE, MC_MCR ) = (UINT32)( MsgBusWriteCmd(PortId) | ((PortId) <<16) | ((Register & MSGBUS_MASKLO)<<8) | MESSAGE_DWORD_EN); \
+}
+
+//
+// UINT16
+//
+
+#define MsgBus16Or(PortId, Register, Dbuff, OrData ) \
+{ \
+ Mmio32( EC_BASE, MC_MCRX) = ( (Register & MSGBUS_MASKHI)); \
+ Mmio32( EC_BASE, MC_MCR ) = (UINT32)( MsgBusReadCmd(PortId) | ((PortId) <<16) | ((Register & MSGBUS_MASKLO)<<8) | MESSAGE_WORD_EN); \
+ (Dbuff) = (UINT16)Mmio16( EC_BASE, MC_MDR ); \
+ Mmio32( EC_BASE, MC_MCRX) = ( (Register & MSGBUS_MASKHI)); \
+ Mmio16( EC_BASE, MC_MDR ) = (Dbuff | OrData); \
+ Mmio32( EC_BASE, MC_MCR ) = (UINT32)( MsgBusWriteCmd(PortId) | ((PortId) <<16) | ((Register & MSGBUS_MASKLO)<<8) | MESSAGE_WORD_EN); \
+}
+
+#define MsgBus16And(PortId, Register, Dbuff, AndData ) \
+{ \
+ Mmio32( EC_BASE, MC_MCRX) = ( (Register & MSGBUS_MASKHI)); \
+ Mmio32( EC_BASE, MC_MCR ) = (UINT32)( MsgBusReadCmd(PortId) | ((PortId) <<16) | ((Register & MSGBUS_MASKLO)<<8) | MESSAGE_WORD_EN); \
+ (Dbuff) = (UINT16)Mmio16( EC_BASE, MC_MDR ); \
+ Mmio32( EC_BASE, MC_MCRX) = ( (Register & MSGBUS_MASKHI)); \
+ Mmio16( EC_BASE, MC_MDR ) = (Dbuff & AndData); \
+ Mmio32( EC_BASE, MC_MCR ) = (UINT32)( MsgBusWriteCmd(PortId) | ((PortId) <<16) | ((Register & MSGBUS_MASKLO)<<8) | MESSAGE_WORD_EN); \
+}
+
+#define MsgBus16AndThenOr( PortId, Register, Dbuff, AndData, OrData ) \
+{ \
+ Mmio32( EC_BASE, MC_MCRX) = ( (Register & MSGBUS_MASKHI)); \
+ Mmio32( EC_BASE, MC_MCR ) = (UINT32)( MsgBusReadCmd(PortId) | ((PortId) <<16) | ((Register & MSGBUS_MASKLO)<<8) | MESSAGE_WORD_EN); \
+ (Dbuff) = (UINT16)Mmio16( EC_BASE, MC_MDR ); \
+ Mmio32( EC_BASE, MC_MCRX) = ( (Register & MSGBUS_MASKHI)); \
+ Mmio16( EC_BASE, MC_MDR ) = ((Dbuff & AndData) | OrData); \
+ Mmio32( EC_BASE, MC_MCR ) = (UINT32)( MsgBusWriteCmd(PortId) | ((PortId) <<16) | ((Register & MSGBUS_MASKLO)<<8) | MESSAGE_WORD_EN); \
+}
+
+//
+// UINT8
+//
+
+#define MsgBus8Or( PortId, Register, Dbuff, OrData ) \
+{ \
+ Mmio32( EC_BASE, MC_MCRX) = ( (Register & MSGBUS_MASKHI)); \
+ Mmio32( EC_BASE, MC_MCR ) = (UINT32)( MsgBusReadCmd(PortId) | ((PortId) <<16) | ((Register & MSGBUS_MASKLO)<<8) | MESSAGE_BYTE_EN); \
+ (Dbuff) = (UINT8)Mmio8( EC_BASE, MC_MDR ); \
+ Mmio32( EC_BASE, MC_MCRX) = ( (Register & MSGBUS_MASKHI)); \
+ Mmio8( EC_BASE, MC_MDR ) = (Dbuff | OrData); \
+ Mmio32( EC_BASE, MC_MCR ) = (UINT32)( MsgBusWriteCmd(PortId) | ((PortId) <<16) | ((Register & MSGBUS_MASKLO)<<8) | MESSAGE_BYTE_EN); \
+}
+
+#define MsgBus8And( PortId, Register, Dbuff, AndData ) \
+{ \
+ Mmio32( EC_BASE, MC_MCRX) = ( (Register & MSGBUS_MASKHI)); \
+ Mmio32( EC_BASE, MC_MCR ) = (UINT32)( MsgBusReadCmd(PortId) | ((PortId) <<16) | ((Register & MSGBUS_MASKLO)<<8) | MESSAGE_BYTE_EN); \
+ (Dbuff) = (UINT8)Mmio8( EC_BASE, MC_MDR ); \
+ Mmio32( EC_BASE, MC_MCRX) = ( (Register & MSGBUS_MASKHI)); \
+ Mmio8( EC_BASE, MC_MDR ) = (Dbuff & AndData); \
+ Mmio32( EC_BASE, MC_MCR ) = (UINT32)( MsgBusWriteCmd(PortId) | ((PortId) <<16) | ((Register & MSGBUS_MASKLO)<<8) | MESSAGE_BYTE_EN); \
+}
+
+#define MsgBus8AndThenOr( PortId, Register, Dbuff, AndData, OrData ) \
+{ \
+ Mmio32( EC_BASE, MC_MCRX) = ( (Register & MSGBUS_MASKHI)); \
+ Mmio32( EC_BASE, MC_MCR ) = (UINT32)( MsgBusReadCmd(PortId) | ((PortId) <<16) | ((Register & MSGBUS_MASKLO)<<8) | MESSAGE_BYTE_EN); \
+ (Dbuff) = (UINT8)Mmio8( EC_BASE, MC_MDR ); \
+ Mmio32( EC_BASE, MC_MCRX) = ( (Register & MSGBUS_MASKHI)); \
+ Mmio8( EC_BASE, MC_MDR ) = ((Dbuff & AndData) | OrData); \
+ Mmio32( EC_BASE, MC_MCR ) = (UINT32)( MsgBusWriteCmd(PortId) | ((PortId) <<16) | ((Register & MSGBUS_MASKLO)<<8) | MESSAGE_BYTE_EN); \
+}
+
+/***************************/
+//
+// Memory mapped PCI IO
+//
+
+#define PciCfgPtr(Bus, Device, Function, Register )\
+ (UINTN)(Bus << 20) + \
+ (UINTN)(Device << 15) + \
+ (UINTN)(Function << 12) + \
+ (UINTN)(Register)
+
+#define PciCfg32Read_CF8CFC(B,D,F,R) \
+ (UINT32)(IoOut32(0xCF8,(0x80000000|(B<<16)|(D<<11)|(F<<8)|(R))),IoIn32(0xCFC))
+
+#define PciCfg32Write_CF8CFC(B,D,F,R,Data) \
+ (IoOut32(0xCF8,(0x80000000|(B<<16)|(D<<11)|(F<<8)|(R))),IoOut32(0xCFC,Data))
+
+#define PciCfg32Or_CF8CFC(B,D,F,R,O) \
+ PciCfg32Write_CF8CFC(B,D,F,R, \
+ (PciCfg32Read_CF8CFC(B,D,F,R) | (O)))
+
+#define PciCfg32And_CF8CFC(B,D,F,R,A) \
+ PciCfg32Write_CF8CFC(B,D,F,R, \
+ (PciCfg32Read_CF8CFC(B,D,F,R) & (A)))
+
+#define PciCfg32AndThenOr_CF8CFC(B,D,F,R,A,O) \
+ PciCfg32Write_CF8CFC(B,D,F,R, \
+ (PciCfg32Read_CF8CFC(B,D,F,R) & (A)) | (O))
+
+//
+// Device 0, Function 0
+//
+#define McD0PciCfg64(Register) MmPci64 (0, MC_BUS, 0, 0, Register)
+#define McD0PciCfg64Or(Register, OrData) MmPci64Or (0, MC_BUS, 0, 0, Register, OrData)
+#define McD0PciCfg64And(Register, AndData) MmPci64And (0, MC_BUS, 0, 0, Register, AndData)
+#define McD0PciCfg64AndThenOr(Register, AndData, OrData) MmPci64AndThenOr (0, MC_BUS, 0, 0, Register, AndData, OrData)
+
+#define McD0PciCfg32(Register) MmPci32 (0, MC_BUS, 0, 0, Register)
+#define McD0PciCfg32Or(Register, OrData) MmPci32Or (0, MC_BUS, 0, 0, Register, OrData)
+#define McD0PciCfg32And(Register, AndData) MmPci32And (0, MC_BUS, 0, 0, Register, AndData)
+#define McD0PciCfg32AndThenOr(Register, AndData, OrData) MmPci32AndThenOr (0, MC_BUS, 0, 0, Register, AndData, OrData)
+
+#define McD0PciCfg16(Register) MmPci16 (0, MC_BUS, 0, 0, Register)
+#define McD0PciCfg16Or(Register, OrData) MmPci16Or (0, MC_BUS, 0, 0, Register, OrData)
+#define McD0PciCfg16And(Register, AndData) MmPci16And (0, MC_BUS, 0, 0, Register, AndData)
+#define McD0PciCfg16AndThenOr(Register, AndData, OrData) MmPci16AndThenOr (0, MC_BUS, 0, 0, Register, AndData, OrData)
+
+#define McD0PciCfg8(Register) MmPci8 (0, MC_BUS, 0, 0, Register)
+#define McD0PciCfg8Or(Register, OrData) MmPci8Or (0, MC_BUS, 0, 0, Register, OrData)
+#define McD0PciCfg8And(Register, AndData) MmPci8And (0, MC_BUS, 0, 0, Register, AndData)
+#define McD0PciCfg8AndThenOr( Register, AndData, OrData ) MmPci8AndThenOr (0, MC_BUS, 0, 0, Register, AndData, OrData)
+
+//
+// Device 2, Function 0
+//
+#define McD2PciCfg64(Register) MmPci64 (0, MC_BUS, 2, 0, Register)
+#define McD2PciCfg64Or(Register, OrData) MmPci64Or (0, MC_BUS, 2, 0, Register, OrData)
+#define McD2PciCfg64And(Register, AndData) MmPci64And (0, MC_BUS, 2, 0, Register, AndData)
+#define McD2PciCfg64AndThenOr(Register, AndData, OrData) MmPci64AndThenOr (0, MC_BUS, 2, 0, Register, AndData, OrData)
+
+#define McD2PciCfg32(Register) MmPci32 (0, MC_BUS, 2, 0, Register)
+#define McD2PciCfg32Or(Register, OrData) MmPci32Or (0, MC_BUS, 2, 0, Register, OrData)
+#define McD2PciCfg32And(Register, AndData) MmPci32And (0, MC_BUS, 2, 0, Register, AndData)
+#define McD2PciCfg32AndThenOr(Register, AndData, OrData) MmPci32AndThenOr (0, MC_BUS, 2, 0, Register, AndData, OrData)
+
+#define McD2PciCfg16(Register) MmPci16 (0, MC_BUS, 2, 0, Register)
+#define McD2PciCfg16Or(Register, OrData) MmPci16Or (0, MC_BUS, 2, 0, Register, OrData)
+#define McD2PciCfg16And(Register, AndData) MmPci16And (0, MC_BUS, 2, 0, Register, AndData)
+#define McD2PciCfg16AndThenOr(Register, AndData, OrData) MmPci16AndThenOr (0, MC_BUS, 2, 0, Register, AndData, OrData)
+
+#define McD2PciCfg8(Register) MmPci8 (0, MC_BUS, 2, 0, Register)
+#define McD2PciCfg8Or(Register, OrData) MmPci8Or (0, MC_BUS, 2, 0, Register, OrData)
+#define McD2PciCfg8And(Register, AndData) MmPci8And (0, MC_BUS, 2, 0, Register, AndData)
+
+//
+// IO
+//
+
+#ifndef IoIn8
+
+#define IoIn8(Port) \
+ IoRead8(Port)
+
+#define IoIn16(Port) \
+ IoRead16(Port)
+
+#define IoIn32(Port) \
+ IoRead32(Port)
+
+#define IoOut8(Port, Data) \
+ IoWrite8(Port, Data)
+
+#define IoOut16(Port, Data) \
+ IoWrite16(Port, Data)
+
+#define IoOut32(Port, Data) \
+ IoWrite32(Port, Data)
+
+#endif
+
+#endif
diff --git a/ChvRefCodePkg/CherryViewSoc/NorthCluster/Include/ChvCommonDefinitions.h b/ChvRefCodePkg/CherryViewSoc/NorthCluster/Include/ChvCommonDefinitions.h new file mode 100644 index 0000000000..60f67fc891 --- /dev/null +++ b/ChvRefCodePkg/CherryViewSoc/NorthCluster/Include/ChvCommonDefinitions.h @@ -0,0 +1,248 @@ +/** @file
+ Macros to simplify and abstract the interface to PCI configuration.
+
+ Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+///
+/// PCI CONFIGURATION MAP REGISTER OFFSETS
+///
+#ifndef PCI_VID
+#define PCI_VID 0x0000 ///< Vendor ID Register
+#define PCI_DID 0x0002 ///< Device ID Register
+#define PCI_CMD 0x0004 ///< PCI Command Register
+#define PCI_STS 0x0006 ///< PCI Status Register
+#define PCI_RID 0x0008 ///< Revision ID Register
+#define PCI_IFT 0x0009 ///< Interface Type
+#define PCI_SCC 0x000A ///< Sub Class Code Register
+#define PCI_BCC 0x000B ///< Base Class Code Register
+#define PCI_CLS 0x000C ///< Cache Line Size
+#define PCI_PMLT 0x000D ///< Primary Master Latency Timer
+#define PCI_HDR 0x000E ///< Header Type Register
+#define PCI_BIST 0x000F ///< Built in Self Test Register
+#define PCI_BAR0 0x0010 ///< Base Address Register 0
+#define PCI_BAR1 0x0014 ///< Base Address Register 1
+#define PCI_BAR2 0x0018 ///< Base Address Register 2
+#define PCI_PBUS 0x0018 ///< Primary Bus Number Register
+#define PCI_SBUS 0x0019 ///< Secondary Bus Number Register
+#define PCI_SUBUS 0x001A ///< Subordinate Bus Number Register
+#define PCI_SMLT 0x001B ///< Secondary Master Latency Timer
+#define PCI_BAR3 0x001C ///< Base Address Register 3
+#define PCI_IOBASE 0x001C ///< I/O base Register
+#define PCI_IOLIMIT 0x001D ///< I/O Limit Register
+#define PCI_SECSTATUS 0x001E ///< Secondary Status Register
+#define PCI_BAR4 0x0020 ///< Base Address Register 4
+#define PCI_MEMBASE 0x0020 ///< Memory Base Register
+#define PCI_MEMLIMIT 0x0022 ///< Memory Limit Register
+#define PCI_BAR5 0x0024 ///< Base Address Register 5
+#define PCI_PRE_MEMBASE 0x0024 ///< Prefetchable memory Base register
+#define PCI_PRE_MEMLIMIT 0x0026 ///< Prefetchable memory Limit register
+#define PCI_PRE_MEMBASE_U 0x0028 ///< Prefetchable memory base upper 32 bits
+#define PCI_PRE_MEMLIMIT_U 0x002C ///< Prefetchable memory limit upper 32 bits
+#define PCI_SVID 0x002C ///< Subsystem Vendor ID
+#define PCI_SID 0x002E ///< Subsystem ID
+#define PCI_IOBASE_U 0x0030 ///< I/O base Upper Register
+#define PCI_IOLIMIT_U 0x0032 ///< I/O Limit Upper Register
+#define PCI_CAPP 0x0034 ///< Capabilities Pointer
+#define PCI_EROM 0x0038 ///< Expansion ROM Base Address
+#define PCI_INTLINE 0x003C ///< Interrupt Line Register
+#define PCI_INTPIN 0x003D ///< Interrupt Pin Register
+#define PCI_MAXGNT 0x003E ///< Max Grant Register
+#define PCI_BRIDGE_CNTL 0x003E ///< Bridge Control Register
+#define PCI_MAXLAT 0x003F ///< Max Latency Register
+#endif
+//
+// Bit Difinitions
+//
+#ifndef BIT0
+#define BIT0 0x0001
+#define BIT1 0x0002
+#define BIT2 0x0004
+#define BIT3 0x0008
+#define BIT4 0x0010
+#define BIT5 0x0020
+#define BIT6 0x0040
+#define BIT7 0x0080
+#define BIT8 0x0100
+#define BIT9 0x0200
+#define BIT10 0x0400
+#define BIT11 0x0800
+#define BIT12 0x1000
+#define BIT13 0x2000
+#define BIT14 0x4000
+#define BIT15 0x8000
+#define BIT16 0x00010000
+#define BIT17 0x00020000
+#define BIT18 0x00040000
+#define BIT19 0x00080000
+#define BIT20 0x00100000
+#define BIT21 0x00200000
+#define BIT22 0x00400000
+#define BIT23 0x00800000
+#define BIT24 0x01000000
+#define BIT25 0x02000000
+#define BIT26 0x04000000
+#define BIT27 0x08000000
+#define BIT28 0x10000000
+#define BIT29 0x20000000
+#define BIT30 0x40000000
+#define BIT31 0x80000000
+#endif
+
+#ifndef _PCIACCESS_H_INCLUDED_
+#define _PCIACCESS_H_INCLUDED_
+#ifndef PCI_EXPRESS_BASE_ADDRESS
+ #define PCI_EXPRESS_BASE_ADDRESS 0xE0000000
+#endif
+
+#ifndef MmPciAddress
+#define MmPciAddress( Segment, Bus, Device, Function, Register ) \
+ ( (UINTN)PCI_EXPRESS_BASE_ADDRESS + \
+ (UINTN)(Bus << 20) + \
+ (UINTN)(Device << 15) + \
+ (UINTN)(Function << 12) + \
+ (UINTN)(Register) \
+ )
+#endif
+
+//
+// UINT64
+//
+#define MmPci64Ptr( Segment, Bus, Device, Function, Register ) \
+ ( (volatile UINT64 *)MmPciAddress( Segment, Bus, Device, Function, Register ) )
+
+#define MmPci64( Segment, Bus, Device, Function, Register ) \
+ *MmPci64Ptr( Segment, Bus, Device, Function, Register )
+
+#define MmPci64Or( Segment, Bus, Device, Function, Register, OrData ) \
+ MmPci64( Segment, Bus, Device, Function, Register ) = \
+ (UINT64) ( \
+ MmPci64( Segment, Bus, Device, Function, Register ) | \
+ (UINT64)(OrData) \
+ )
+
+#define MmPci64And( Segment, Bus, Device, Function, Register, AndData ) \
+ MmPci64( Segment, Bus, Device, Function, Register ) = \
+ (UINT64) ( \
+ MmPci64( Segment, Bus, Device, Function, Register ) & \
+ (UINT64)(AndData) \
+ )
+
+#define MmPci64AndThenOr( Segment, Bus, Device, Function, Register, AndData, OrData ) \
+ MmPci64( Segment, Bus, Device, Function, Register ) = \
+ (UINT64) ( \
+ ( MmPci64( Segment, Bus, Device, Function, Register ) & \
+ (UINT64)(AndData) \
+ ) | \
+ (UINT64)(OrData) \
+ )
+
+//
+// UINT32
+//
+
+#define MmPci32Ptr( Segment, Bus, Device, Function, Register ) \
+ ( (volatile UINT32 *) MmPciAddress( Segment, Bus, Device, Function, Register ) )
+
+#define MmPci32( Segment, Bus, Device, Function, Register ) \
+ *MmPci32Ptr( Segment, Bus, Device, Function, Register )
+
+#define MmPci32Or( Segment, Bus, Device, Function, Register, OrData ) \
+ MmPci32( Segment, Bus, Device, Function, Register ) = \
+ (UINT32) ( \
+ MmPci32( Segment, Bus, Device, Function, Register ) | \
+ (UINT32)(OrData) \
+ )
+
+#define MmPci32And( Segment, Bus, Device, Function, Register, AndData ) \
+ MmPci32( Segment, Bus, Device, Function, Register ) = \
+ (UINT32) ( \
+ MmPci32( Segment, Bus, Device, Function, Register ) & \
+ (UINT32)(AndData) \
+ )
+
+#define MmPci32AndThenOr( Segment, Bus, Device, Function, Register, AndData, OrData ) \
+ MmPci32( Segment, Bus, Device, Function, Register ) = \
+ (UINT32) ( \
+ ( MmPci32( Segment, Bus, Device, Function, Register ) & \
+ (UINT32)(AndData) \
+ ) | \
+ (UINT32)(OrData) \
+ )
+
+//
+// UINT16
+//
+
+#define MmPci16Ptr( Segment, Bus, Device, Function, Register ) \
+ ( (volatile UINT16 *)MmPciAddress( Segment, Bus, Device, Function, Register ) )
+
+#define MmPci16( Segment, Bus, Device, Function, Register ) \
+ *MmPci16Ptr( Segment, Bus, Device, Function, Register )
+
+#define MmPci16Or( Segment, Bus, Device, Function, Register, OrData ) \
+ MmPci16( Segment, Bus, Device, Function, Register ) = \
+ (UINT16) ( \
+ MmPci16( Segment, Bus, Device, Function, Register ) | \
+ (UINT16)(OrData) \
+ )
+
+#define MmPci16And( Segment, Bus, Device, Function, Register, AndData ) \
+ MmPci16( Segment, Bus, Device, Function, Register ) = \
+ (UINT16) ( \
+ MmPci16( Segment, Bus, Device, Function, Register ) & \
+ (UINT16)(AndData) \
+ )
+
+#define MmPci16AndThenOr( Segment, Bus, Device, Function, Register, AndData, OrData ) \
+ MmPci16( Segment, Bus, Device, Function, Register ) = \
+ (UINT16) ( \
+ ( MmPci16( Segment, Bus, Device, Function, Register ) & \
+ (UINT16)(AndData) \
+ ) | \
+ (UINT16)(OrData) \
+ )
+
+//
+// UINT8
+//
+
+#define MmPci8Ptr( Segment, Bus, Device, Function, Register ) \
+ ( (volatile UINT8 *)MmPciAddress( Segment, Bus, Device, Function, Register ) )
+
+#define MmPci8( Segment, Bus, Device, Function, Register ) \
+ *MmPci8Ptr( Segment, Bus, Device, Function, Register )
+
+#define MmPci8Or( Segment, Bus, Device, Function, Register, OrData ) \
+ MmPci8( Segment, Bus, Device, Function, Register ) = \
+ (UINT8) ( \
+ MmPci8( Segment, Bus, Device, Function, Register ) | \
+ (UINT8)(OrData) \
+ )
+
+#define MmPci8And( Segment, Bus, Device, Function, Register, AndData ) \
+ MmPci8( Segment, Bus, Device, Function, Register ) = \
+ (UINT8) ( \
+ MmPci8( Segment, Bus, Device, Function, Register ) & \
+ (UINT8)(AndData) \
+ )
+
+#define MmPci8AndThenOr( Segment, Bus, Device, Function, Register, AndData, OrData ) \
+ MmPci8( Segment, Bus, Device, Function, Register ) = \
+ (UINT8) ( \
+ ( MmPci8( Segment, Bus, Device, Function, Register ) & \
+ (UINT8)(AndData) \
+ ) | \
+ (UINT8)(OrData) \
+ )
+
+#endif
diff --git a/ChvRefCodePkg/CherryViewSoc/NorthCluster/Include/ChvDataHob.h b/ChvRefCodePkg/CherryViewSoc/NorthCluster/Include/ChvDataHob.h new file mode 100644 index 0000000000..43e8569418 --- /dev/null +++ b/ChvRefCodePkg/CherryViewSoc/NorthCluster/Include/ChvDataHob.h @@ -0,0 +1,69 @@ +/** @file
+ The GUID definition for SaDataHob
+
+ Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _CHV_DATA_HOB_H_
+#define _CHV_DATA_HOB_H_
+
+#include <Base.h>
+
+extern EFI_GUID gChvDataHobGuid;
+
+#define GP_ENABLE 1
+#define GP_DISABLE 0
+
+#pragma pack(1)
+//
+// HgMode settings
+//
+typedef enum {
+ HgModeDisabled = 0,
+ HgModeReserved,
+ HgModeMuxless,
+ HgModeDgpu,
+ HgModeMax
+} HG_MODE;
+
+//
+// HG GPIO Data Structure
+//
+typedef struct {
+ UINT32 CommunityOffset; //< GPIO Community
+ UINT32 PinOffset; //< GPIO Pin
+ BOOLEAN Active; //< 0=Active Low; 1=Active High
+} HG_GPIO;
+
+//
+// HG Info HOB
+//
+typedef struct _HG_INFO_HOB {
+ EFI_HOB_GUID_TYPE EfiHobGuidType;
+ UINT8 RevisionId; //< Revision ID
+ HG_MODE HgMode;
+ BOOLEAN HgGpioSupport; //< 0=Not Supported; 1=Supported.
+ HG_GPIO HgDgpuHoldRst;
+ HG_GPIO HgDgpuPwrEnable;
+ UINT16 HgDelayAfterPwrEn;
+ UINT16 HgDelayAfterHoldReset;
+} HG_INFO_HOB;
+
+//
+// CherryView Data Hob
+//
+typedef struct {
+ EFI_HOB_GUID_TYPE EfiHobGuidType; //< GUID Hob type structure
+ HG_INFO_HOB HgInfo; //< HG Info HOB
+} CHV_DATA_HOB;
+#pragma pack()
+#endif
diff --git a/ChvRefCodePkg/CherryViewSoc/NorthCluster/Include/Guid/AcpiVariable.h b/ChvRefCodePkg/CherryViewSoc/NorthCluster/Include/Guid/AcpiVariable.h new file mode 100644 index 0000000000..b82b51ca72 --- /dev/null +++ b/ChvRefCodePkg/CherryViewSoc/NorthCluster/Include/Guid/AcpiVariable.h @@ -0,0 +1,64 @@ +/** @file
+ GUIDs used for ACPI variables.
+
+ Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _ACPI_VARIABLE_H_
+#define _ACPI_VARIABLE_H_
+
+#define ACPI_GLOBAL_VARIABLE L"AcpiGlobalVariable"
+
+//
+// The following structure combine all ACPI related variables into one in order
+// to boost performance
+//
+#pragma pack (1)
+typedef struct {
+ UINT16 Limit;
+ UINTN Base;
+} PSEUDO_DESCRIPTOR;
+#pragma pack()
+
+typedef struct {
+ BOOLEAN APState;
+ BOOLEAN S3BootPath;
+ EFI_PHYSICAL_ADDRESS WakeUpBuffer;
+ EFI_PHYSICAL_ADDRESS GdtrProfile;
+ EFI_PHYSICAL_ADDRESS IdtrProfile;
+ EFI_PHYSICAL_ADDRESS CpuPrivateData;
+ EFI_PHYSICAL_ADDRESS StackAddress;
+ EFI_PHYSICAL_ADDRESS MicrocodePointerBuffer;
+ EFI_PHYSICAL_ADDRESS SmramBase;
+ EFI_PHYSICAL_ADDRESS SmmStartImageBase;
+ UINT32 SmmStartImageSize;
+ UINT32 NumberOfCpus;
+ UINT32 ApInitDone;
+} ACPI_CPU_DATA;
+
+typedef struct {
+ //
+ // Acpi Related variables
+ //
+ EFI_PHYSICAL_ADDRESS AcpiReservedMemoryBase;
+ UINT32 AcpiReservedMemorySize;
+ EFI_PHYSICAL_ADDRESS S3ReservedLowMemoryBase;
+ EFI_PHYSICAL_ADDRESS AcpiBootScriptTable;
+ EFI_PHYSICAL_ADDRESS RuntimeScriptTableBase;
+ EFI_PHYSICAL_ADDRESS AcpiFacsTable;
+ UINT64 SystemMemoryLength;
+ ACPI_CPU_DATA AcpiCpuData;
+} ACPI_VARIABLE_SET;
+
+extern EFI_GUID gEfiAcpiVariableGuid;
+
+#endif
diff --git a/ChvRefCodePkg/CherryViewSoc/NorthCluster/Include/Guid/HgAcpiTableStorage.h b/ChvRefCodePkg/CherryViewSoc/NorthCluster/Include/Guid/HgAcpiTableStorage.h new file mode 100644 index 0000000000..6ff2cad67a --- /dev/null +++ b/ChvRefCodePkg/CherryViewSoc/NorthCluster/Include/Guid/HgAcpiTableStorage.h @@ -0,0 +1,21 @@ +/** @file
+ GUID definition for the HG ACPI table storage file name
+
+ Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _HG_ACPI_TABLE_STORAGE_H_
+#define _HG_ACPI_TABLE_STORAGE_H_
+
+extern EFI_GUID gHgAcpiTableStorageGuid;
+
+#endif
diff --git a/ChvRefCodePkg/CherryViewSoc/NorthCluster/Include/Guid/MemoryConfigData.h b/ChvRefCodePkg/CherryViewSoc/NorthCluster/Include/Guid/MemoryConfigData.h new file mode 100644 index 0000000000..dc79d81a4b --- /dev/null +++ b/ChvRefCodePkg/CherryViewSoc/NorthCluster/Include/Guid/MemoryConfigData.h @@ -0,0 +1,23 @@ +/** @file
+ GUID used for Memory Configuration Data entries in the HOB list.
+
+ Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _MEMORY_CONFIG_DATA_GUID_H_
+#define _MEMORY_CONFIG_DATA_GUID_H_
+
+#define EFI_MEMORY_CONFIG_VARIABLE_NAME L"MemoryConfig"
+extern EFI_GUID gEfiMemoryConfigDataGuid;
+extern CHAR16 EfiMemoryConfigVariable[];
+
+#endif
diff --git a/ChvRefCodePkg/CherryViewSoc/NorthCluster/Include/McAccess.h b/ChvRefCodePkg/CherryViewSoc/NorthCluster/Include/McAccess.h new file mode 100644 index 0000000000..6d922fa3a6 --- /dev/null +++ b/ChvRefCodePkg/CherryViewSoc/NorthCluster/Include/McAccess.h @@ -0,0 +1,157 @@ +/** @file
+ Macros to simplify and abstract the interface to PCI configuration.
+
+ Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _MCACCESS_H_INCLUDED_
+#define _MCACCESS_H_INCLUDED_
+
+#include "Cherryview.h"
+#include "ChvCommonDefinitions.h"
+
+//
+// Memory Controller PCI access macros
+//
+
+#define MCH_BASE_ADDRESS 0xfed14000
+
+// Device 0, Function 0
+
+#define McD0PciCfg32(Register) MmPci32 (0, MC_BUS, 0, 0, Register)
+
+#define McD0PciCfg32Or(Register, OrData) MmPci32Or (0, MC_BUS, 0, 0, Register, OrData)
+
+#define McD0PciCfg32And(Register, AndData) MmPci32And (0, MC_BUS, 0, 0, Register, AndData)
+
+#define McD0PciCfg32AndThenOr(Register, AndData, OrData) \
+ MmPci32AndThenOr (0, MC_BUS, 0, 0, Register, AndData, OrData)
+
+#define McD0PciCfg16(Register) MmPci16 (0, MC_BUS, 0, 0, Register)
+
+#define McD0PciCfg16Or(Register, OrData) MmPci16Or (0, MC_BUS, 0, 0, Register, OrData)
+
+#define McD0PciCfg16And(Register, AndData) MmPci16And (0, MC_BUS, 0, 0, Register, AndData)
+
+#define McD0PciCfg16AndThenOr(Register, AndData, OrData) \
+ MmPci16AndThenOr (0, MC_BUS, 0, 0, Register, AndData, OrData)
+
+#define McD0PciCfg8(Register) MmPci8 (0, MC_BUS, 0, 0, Register)
+
+#define McD0PciCfg8Or(Register, OrData) MmPci8Or (0, MC_BUS, 0, 0, Register, OrData)
+
+#define McD0PciCfg8And(Register, AndData) MmPci8And (0, MC_BUS, 0, 0, Register, AndData)
+
+#define McD0PciCfg8AndThenOr( Register, AndData, OrData ) \
+ MmPci8AndThenOr (0, MC_BUS, 0, 0, Register, AndData, OrData)
+
+
+// Device 1, Function 0
+
+#define McD1PciCfg32(Register) MmPci32 (0, MC_BUS, 1, 0, Register)
+
+#define McD1PciCfg32Or(Register, OrData) MmPci32Or (0, MC_BUS, 1, 0, Register, OrData)
+
+#define McD1PciCfg32And(Register, AndData) MmPci32And (0, MC_BUS, 1, 0, Register, AndData)
+
+#define McD1PciCfg32AndThenOr(Register, AndData, OrData) \
+ MmPci32AndThenOr (0, MC_BUS, 1, 0, Register, AndData, OrData)
+
+#define McD1PciCfg16(Register) MmPci16 (0, MC_BUS, 1, 0, Register)
+
+#define McD1PciCfg16Or(Register, OrData) MmPci16Or (0, MC_BUS, 1, 0, Register, OrData)
+
+#define McD1PciCfg16And(Register, AndData) MmPci16And (0, MC_BUS, 1, 0, Register, AndData)
+
+#define McD1PciCfg16AndThenOr(Register, AndData, OrData) \
+ MmPci16AndThenOr (0, MC_BUS, 1, 0, Register, AndData, OrData)
+
+#define McD1PciCfg8(Register) MmPci8 (0, MC_BUS, 1, 0, Register)
+
+#define McD1PciCfg8Or(Register, OrData) MmPci8Or (0, MC_BUS, 1, 0, Register, OrData)
+
+#define McD1PciCfg8And(Register, AndData) MmPci8And (0, MC_BUS, 1, 0, Register, AndData)
+
+#define McD1PciCfg8AndThenOr(Register, AndData, OrData) \
+ MmPci8AndThenOr (0, MC_BUS, 1, 0, Register, AndData, OrData)
+
+
+// Device 2, Function 0
+
+#define McD2PciCfg32(Register) MmPci32 (0, MC_BUS, 2, 0, Register)
+
+#define McD2PciCfg32Or(Register, OrData) MmPci32Or (0, MC_BUS, 2, 0, Register, OrData)
+
+#define McD2PciCfg32And(Register, AndData) MmPci32And (0, MC_BUS, 2, 0, Register, AndData)
+
+#define McD2PciCfg32AndThenOr(Register, AndData, OrData) \
+ MmPci32AndThenOr (0, MC_BUS, 2, 0, Register, AndData, OrData)
+
+#define McD2PciCfg16(Register) MmPci16 (0, MC_BUS, 2, 0, Register)
+
+#define McD2PciCfg16Or(Register, OrData) MmPci16Or (0, MC_BUS, 2, 0, Register, OrData)
+
+#define McD2PciCfg16And(Register, AndData) MmPci16And (0, MC_BUS, 2, 0, Register, AndData)
+
+#define McD2PciCfg16AndThenOr(Register, AndData, OrData) \
+ MmPci16AndThenOr (0, MC_BUS, 2, 0, Register, AndData, OrData)
+
+#define McD2PciCfg8(Register) MmPci8 (0, MC_BUS, 2, 0, Register)
+
+#define McD2PciCfg8Or(Register, OrData) MmPci8Or (0, MC_BUS, 2, 0, Register, OrData)
+
+#define McD2PciCfg8And(Register, AndData) MmPci8And (0, MC_BUS, 2, 0, Register, AndData)
+
+#define McD2PciCfg8AndThenOr(Register, AndData, OrData) \
+ MmPci8AndThenOr (0, MC_BUS, 2, 0, Register, AndData, OrData)
+
+//
+// Memory Controller Hub Memory Mapped IO register accesse
+//
+
+#define McMmioAddress(Register) ((UINTN)MCH_BASE_ADDRESS + (UINTN)(Register))
+
+#define McMmio32Ptr(Register) ((volatile UINT32 *)McMmioAddress (Register))
+
+#define McMmio32(Register) *McMmio32Ptr( Register )
+
+#define McMmio32Or(Register, OrData) (McMmio32 (Register) |= (UINT32)(OrData))
+
+#define McMmio32And(Register, AndData) (McMmio32 (Register) &= (UINT32)(AndData))
+
+#define McMmio32AndThenOr(Register, AndData, OrData) \
+ (McMmio32 ( Register ) = (McMmio32( Register ) & (UINT32)(AndData)) | (UINT32)(OrData))
+
+#define McMmio16Ptr(Register) ((volatile UINT16 *)McMmioAddress (Register))
+
+#define McMmio16(Register) *McMmio16Ptr (Register)
+
+#define McMmio16Or(Register, OrData) (McMmio16 (Register) |= (UINT16)(OrData))
+
+#define McMmio16And( Register, AndData ) (McMmio16 (Register) &= (UINT16)(AndData))
+
+#define McMmio16AndThenOr(Register, AndData, OrData) \
+ (McMmio16 (Register) = (McMmio16 (Register) & (UINT16)(AndData)) | (UINT16)(OrData))
+
+#define McMmio8Ptr(Register) ((volatile UINT8 *)McMmioAddress (Register))
+
+#define McMmio8(Register) *McMmio8Ptr (Register)
+
+#define McMmio8Or(Register, OrData) (McMmio8 (Register) |= (UINT8)(OrData))
+
+#define McMmio8And(Register, AndData) (McMmio8 (Register) &= (UINT8)(AndData))
+
+#define McMmio8AndThenOr(Register, AndData, OrData) \
+ (McMmio8 (Register) = (McMmio8 (Register) & (UINT8)(AndData)) | (UINT8)(OrData))
+
+#endif
+
diff --git a/ChvRefCodePkg/CherryViewSoc/NorthCluster/Include/PlatformBaseAddresses.h b/ChvRefCodePkg/CherryViewSoc/NorthCluster/Include/PlatformBaseAddresses.h new file mode 100644 index 0000000000..8960966454 --- /dev/null +++ b/ChvRefCodePkg/CherryViewSoc/NorthCluster/Include/PlatformBaseAddresses.h @@ -0,0 +1,81 @@ +/** @file
+ The definition of Platform Base Address.
+
+ Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _PLATFORM_BASE_ADDRESSES_H
+#define _PLATFORM_BASE_ADDRESSES_H
+
+//
+// Define some fixed platform device location information
+//
+
+//
+// Define platform base
+//
+
+//
+// SIO
+//
+#define SIO_BASE_ADDRESS 0x0680
+#define SIO_MONITORING_BASE_ADDRESS 0x0290
+#define SIO_BASE_MASK 0xFFF0
+#define WINDBOND_ECIR_BASE_ADDRESS 0x0810
+#define SIO_MAILBOX_BASE_ADDRESS 0x0360 // Used by EC controller
+#define SIO_EC_CHANNEL2 0x62 // Used by EC controller for offset 0x62 and 0x66
+
+//
+// South Cluster
+//
+#define ACPI_BASE_ADDRESS 0x0400
+#define SMBUS_BUS_DEV_FUNC 0x1F0300
+#define SMBUS_BASE_ADDRESS 0xEFA0 // SMBus IO Base Address
+#define SPI_BASE_ADDRESS 0xFED01000 // SPI Memory Base Address
+#define PMC_BASE_ADDRESS 0xFED03000 // PMC Memory Base Address
+#define IO_BASE_ADDRESS 0xFED80000 // IO Memory Base Address
+#define ILB_BASE_ADDRESS 0xFED08000 // ILB Memory Base Address
+#define RCBA_BASE_ADDRESS 0xFED1C000 // Root Complex Base Address
+#define MPHY_BASE_ADDRESS 0xFEA00000 // MPHY Memory Base Address
+#define PUNIT_BASE_ADDRESS 0xFED06000 // PUNIT Memory Base Address
+
+//
+// MCH/CPU
+//
+#define DMI_BASE_ADDRESS 0xFED18000 // 4K, similar to IIO_RCBA // modify from bearlake -- cchew10
+#define EP_BASE_ADDRESS 0xFED19000
+#define MC_MMIO_BASE 0xFED14000 // Base Address for MMIO registers
+
+//
+// TPM
+//
+#define TPM_BASE_ADDRESS 0xFED40000 // Base address for TPM
+
+//
+// Local and I/O APIC addresses.
+//
+#define IO_APIC_ADDRESS 0xFEC00000
+#define IIO_IOAPIC_ADDRESS 0xFEC90000
+#define LOCAL_APIC_ADDRESS 0xFEE00000
+
+//
+// PCIEX Base Address (ECAM)
+//
+#define PCIEX_BASE_ADDRESS 0xE0000000
+
+//
+// HPET
+//
+#define HPET_BASE_ADDRESS 0xFED00000 // HPET Base Address
+
+#endif
+
diff --git a/ChvRefCodePkg/CherryViewSoc/NorthCluster/Include/Ppi/ChvPeiInit.h b/ChvRefCodePkg/CherryViewSoc/NorthCluster/Include/Ppi/ChvPeiInit.h new file mode 100644 index 0000000000..339aee78ce --- /dev/null +++ b/ChvRefCodePkg/CherryViewSoc/NorthCluster/Include/Ppi/ChvPeiInit.h @@ -0,0 +1,24 @@ +/** @file
+ Interface definition between CherryView MRC and ChvInitPeim driver..
+
+ Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _CHV_PEI_INIT_H_
+#define _CHV_PEI_INIT_H_
+
+//
+// Extern the GUID for PPI users.
+//
+extern EFI_GUID gChvPeiInitPpiGuid;
+
+#endif
diff --git a/ChvRefCodePkg/CherryViewSoc/NorthCluster/Include/Ppi/ChvPlatformPolicyPpi.h b/ChvRefCodePkg/CherryViewSoc/NorthCluster/Include/Ppi/ChvPlatformPolicyPpi.h new file mode 100644 index 0000000000..3473db9268 --- /dev/null +++ b/ChvRefCodePkg/CherryViewSoc/NorthCluster/Include/Ppi/ChvPlatformPolicyPpi.h @@ -0,0 +1,230 @@ +/** @file
+ Interface definition details between CherryView MRC and platform drivers during PEI phase.
+
+ Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _CHV_PLATFORM_POLICY_PPI_H_
+#define _CHV_PLATFORM_POLICY_PPI_H_
+
+//
+// Extern the GUID for protocol users.
+//
+extern EFI_GUID gChvPolicyPpiGuid;
+
+//
+// PPI revision number
+// Any backwards compatible changes to this PPI will result in an update in the revision number
+// Major changes will require publication of a new PPI
+//
+#define MRC_PLATFORM_POLICY_PPI_REVISION 1
+
+#ifndef MAX_SOCKETS
+#define MAX_SOCKETS 4
+#endif
+
+#ifndef MAX_CHANNELS
+#define MAX_CHANNELS 2
+#endif
+
+#ifndef MAX_DIMMS
+#define MAX_DIMMS 2
+#endif
+
+#define MAX_OEM_SPD_ADDR 125
+#define SPD_TABLE_SIZE MAX_OEM_SPD_ADDR + 1
+
+#define S3_TIMING_DATA_LEN 9
+#define S3_READ_TRAINING_DATA_LEN 16
+#define S3_WRITE_TRAINING_DATA_LEN 12
+
+#ifndef S3_RESTORE_DATA_LEN
+#define S3_RESTORE_DATA_LEN (S3_TIMING_DATA_LEN + S3_READ_TRAINING_DATA_LEN + S3_WRITE_TRAINING_DATA_LEN)
+#endif // S3_RESTORE_DATA_LEN
+
+#define BSW_SVID_CONFIG0 0
+#define BSW_SVID_CONFIG1 1
+#define BSW_SVID_CONFIG3 3
+#define BSW_I2C_PMIC_CONFIG 8
+#pragma pack(1)
+//
+// MRC Platform Data Structure
+//
+typedef struct {
+ UINT8 SpdAddressTable[MAX_SOCKETS];
+ UINT8 TSonDimmSmbusAddress[MAX_SOCKETS];
+
+ UINT16 SmbusBar;
+ UINT32 IchRcba;
+ UINT32 WdbBaseAddress; // Write Data Buffer area (WC caching mode)
+ UINT32 WdbRegionSize;
+ UINT32 SmBusAddress;
+ UINT8 UserBd;
+ UINT8 PlatformType;
+ UINT8 FastBoot;
+ UINT8 DynSR;
+ UINT8 HgMode; ///< HgMode (0=Disabled, 1=SG Muxed, 2=SG Muxless, 3=PEG)
+ UINT16 HgSubSystemId; ///< Hybrid Graphics Subsystem ID
+ UINT16 HgDelayAfterPwrEn; ///< Dgpu Delay after Power enable using Setup option
+ UINT16 HgDelayAfterHoldReset; ///< Dgpu Delay after Hold Reset using Setup option
+} CHV_PLATFORM_DATA;
+
+typedef struct {
+ UINT16 MmioSize;
+ UINT16 GttSize;
+ UINT8 IgdDvmt50PreAlloc;
+ UINT8 PrimaryDisplay;
+ UINT8 ApertureSize;
+ UINT8 InternalGraphics;
+ UINT8 IgdTurboEn;
+ UINT64 GttMmAdr;
+ UINT32 GMAdr;
+} GT_CONFIGURATION;
+
+enum {
+ MRC_MOTHERBOARDDOWN = 0,
+ MRC_SODIMM = 1,
+ MRC_COPOP = 2
+};
+
+typedef enum {
+ MRC_DDR3L = 0,
+ MRC_LPDDR3 = 1,
+} CHV_POLICY_DDR_TYPE;
+
+typedef enum {
+ MRC_DDR800 = 0,
+ MRC_DDR1066 = 1,
+ MRC_DDR1600 = 2,
+ MRC_DDR800_SKU333 = 3,
+ MRC_DDR1000_SKU333 = 4,
+ MRC_DDR1333_SKU333 = 5,
+ MRC_DDR900_SKU360 = 6,
+ MRC_DDR1800_SKU360 = 7,
+ MRC_DDR933_SKU373 = 8,
+ MRC_DDR1866_SKU373 = 9,
+ MRC_DDR_MAX =10,
+} CHV_POLICY_DDR_FREQUENCY;
+
+typedef enum {
+ MRC_Width_x8 = 0,
+ MRC_Width_x16 = 1,
+ MRC_Width_x32 = 2,
+} CHV_POLICY_DRAM_WIDTH;
+
+typedef enum {
+ MRC_Density_1Gb = 0,
+ MRC_Density_2Gb = 1,
+ MRC_Density_4Gb = 2,
+ MRC_Density_8Gb = 3,
+ MRC_Density_16Gb = 4,
+ MRC_Density_6b = 5,
+} CHV_POLICY_DRAM_DENSITY;
+
+typedef enum {
+ DimmInstalled = 0, // Check Physical Spd Data thru the Smbus
+ SolderDownMemory, // Use OemSpdDataMemorySolderDown SPD data pointer
+ DimmDisabled // Dimm Slot Disabled
+} OEM_MEMORY_DIMM_TYPE;
+
+typedef UINT8 OEM_MEMORY_DIMM_CONFIGURATION;
+
+typedef struct {
+ UINT8 Enabled;
+ UINT8 CurrentConfiguration;
+} CHANNEL_CONFIGURATION;
+
+typedef struct {
+ UINT8 EccSupport;
+ UINT16 DdrFreqLimit;
+ UINT8 MaxTolud;
+ CHV_POLICY_DDR_TYPE DdrType;
+ UINT8 DvfsEnable;
+ CHV_POLICY_DDR_FREQUENCY DvfsFreqA;
+ CHV_POLICY_DDR_FREQUENCY DvfsFreqB;
+ UINT8 RmtEvMode;
+ UINT8 RmtCommandMode;
+ UINT8 DualRankDram;
+ UINT8 MrcDynamicSr;
+ UINT8 MrcChannelSel_3_0;
+ UINT8 MrcChannelSel_4;
+ UINT8 AutoDetectDram;
+ UINT8 MrcDebugMsgLevel;
+ UINT8 MrcPm5Enable;
+ UINT8 MrcBankAddressHashingEnable;
+ UINT8 MrcRankSelInterleave;
+ CHANNEL_CONFIGURATION Channel[MAX_CHANNELS];
+ UINT8 MrcConfigChanged;
+ UINT8 UseDimmSpd;
+ CHV_POLICY_DRAM_WIDTH DramWidth;
+ CHV_POLICY_DRAM_DENSITY DramDensity;
+ UINT8 MrcDdr2nMode;
+ UINT8 CaMirrorEn;
+ UINT8 TSEGSizeSel;
+ UINT8 (*OemSpdDataMemorySolderDown)[SPD_TABLE_SIZE];
+ OEM_MEMORY_DIMM_CONFIGURATION OemMemoryDimmConfiguration[MAX_CHANNELS][MAX_DIMMS];
+ UINT8 MrcRxPwrTrainingDisable;
+ UINT8 MrcTxPwrTrainingDisable;
+ UINT8 MrcScramblerDisable;
+ UINT8 MrcSpeedGrade;
+ UINT8 DrpLockDisable;
+ UINT8 ReutLockDisable;
+ UINT8 UseBiosProvidedDramTimings;
+ UINT8 RhPrevention;
+ UINT8 RemapEnable;
+ UINT8 Ddr3AutoSelfRefreshEnable;
+ UINT8 MrcSpdFrequencyOverrideEnable;
+} MEMORY_CONFIGURATION;
+
+///
+/// HG GPIO Data Structure
+///
+typedef struct {
+ UINT32 CommunityOffset; ///< GPIO Community
+ UINT32 PinOffset; ///< GPIO Pin
+ BOOLEAN Active; ///< 0=Active Low; 1=Active High
+} HG_GPIO_INFO;
+
+///
+/// Defines the Hybrid Graphics configuration parameters.
+///
+typedef struct {
+ BOOLEAN GpioSupport; ///< 1=Supported; 0=Not Supported
+ HG_GPIO_INFO HgDgpuHoldRst; ///< This field contain dGPU HLD RESET GPIO value and level information
+ HG_GPIO_INFO HgDgpuPwrEnable; ///< This field contain dGPU_PWR Enable GPIO value and level information
+} HG_GPIO_DATA;
+//
+// CHV Platform Policiy PPI
+//
+typedef struct _CHV_POLICY_PPI {
+ UINT8 Revision;
+ CHV_PLATFORM_DATA PlatformData;
+ GT_CONFIGURATION GtConfig;
+ MEMORY_CONFIGURATION MemConfig;
+ HG_GPIO_DATA HgGpioData;
+ UINT8 PMIC_I2CBus; // This field is NA when ChvSvidConfig is not BSW_I2C_PMIC_CONFIG
+ VOID *S3DataPtr; // was called MRC_PARAMS_SAVE_RESTORE
+ UINT8 ISPEn; //ISP (IUNIT) Device Enabled
+ UINT8 ISPPciDevConfig; //ISP (IUNIT) Device Config: 0->B0/D2/F0 for Window OS, 1->B0D3/F0 for Linux OS
+ BOOLEAN IEDEnabled;
+ UINT32 IEDRamSize;
+ UINT8 ChvSvidConfig;
+ UINT8 PunitPwrConfigDisable;
+#ifdef PRAM_SUPPORT
+ UINT32 PramSize;
+#endif
+ UINT8 PkgPwrLim1; // Power Limit Value (to be set in PUINT PKG_PWR_LIM1)
+} CHV_POLICY_PPI;
+
+#pragma pack()
+
+#endif // _CHV_POLICY_PPI_H_
diff --git a/ChvRefCodePkg/CherryViewSoc/NorthCluster/Include/Ppi/PlatformMemoryRange.h b/ChvRefCodePkg/CherryViewSoc/NorthCluster/Include/Ppi/PlatformMemoryRange.h new file mode 100644 index 0000000000..bb412f0756 --- /dev/null +++ b/ChvRefCodePkg/CherryViewSoc/NorthCluster/Include/Ppi/PlatformMemoryRange.h @@ -0,0 +1,135 @@ +/** @file
+ Platform Memory Range PPI as defined in EFI 2.0
+
+ PPI for reserving special purpose memory ranges.
+
+ Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _PEI_PLATFORM_MEMORY_RANGE_H_
+#define _PEI_PLATFORM_MEMORY_RANGE_H_
+
+typedef struct _PEI_PLATFORM_MEMORY_RANGE_PPI PEI_PLATFORM_MEMORY_RANGE_PPI ;
+
+#define PEI_MEMORY_RANGE_OPTION_ROM UINT32
+
+#define PEI_MR_OPTION_ROM_ALL 0xFFFFFFFF
+#define PEI_MR_OPTION_ROM_NONE 0x00000000
+#define PEI_MR_OPTION_ROM_C0000_16K 0x00000001
+#define PEI_MR_OPTION_ROM_C4000_16K 0x00000002
+#define PEI_MR_OPTION_ROM_C8000_16K 0x00000004
+#define PEI_MR_OPTION_ROM_CC000_16K 0x00000008
+#define PEI_MR_OPTION_ROM_D0000_16K 0x00000010
+#define PEI_MR_OPTION_ROM_D4000_16K 0x00000020
+#define PEI_MR_OPTION_ROM_D8000_16K 0x00000040
+#define PEI_MR_OPTION_ROM_DC000_16K 0x00000080
+#define PEI_MR_OPTION_ROM_E0000_16K 0x00000100
+#define PEI_MR_OPTION_ROM_E4000_16K 0x00000200
+#define PEI_MR_OPTION_ROM_E8000_16K 0x00000400
+#define PEI_MR_OPTION_ROM_EC000_16K 0x00000800
+#define PEI_MR_OPTION_ROM_F0000_16K 0x00001000
+#define PEI_MR_OPTION_ROM_F4000_16K 0x00002000
+#define PEI_MR_OPTION_ROM_F8000_16K 0x00004000
+#define PEI_MR_OPTION_ROM_FC000_16K 0x00008000
+
+//
+// SMRAM Memory Range
+//
+#define PEI_MEMORY_RANGE_SMRAM UINT32
+#define PEI_MR_SMRAM_ALL 0xFFFFFFFF
+#define PEI_MR_SMRAM_NONE 0x00000000
+#define PEI_MR_SMRAM_CACHEABLE_MASK 0x80000000
+#define PEI_MR_SMRAM_SEGTYPE_MASK 0x00FF0000
+#define PEI_MR_SMRAM_ABSEG_MASK 0x00010000
+#define PEI_MR_SMRAM_HSEG_MASK 0x00020000
+#define PEI_MR_SMRAM_TSEG_MASK 0x00040000
+//
+// If adding additional entries, SMRAM Size
+// is a multiple of 128KB.
+//
+#define PEI_MR_SMRAM_SIZE_MASK 0x0000FFFF
+#define PEI_MR_SMRAM_SIZE_128K_MASK 0x00000001
+#define PEI_MR_SMRAM_SIZE_256K_MASK 0x00000002
+#define PEI_MR_SMRAM_SIZE_512K_MASK 0x00000004
+#define PEI_MR_SMRAM_SIZE_1024K_MASK 0x00000008
+#define PEI_MR_SMRAM_SIZE_2048K_MASK 0x00000010
+#define PEI_MR_SMRAM_SIZE_4096K_MASK 0x00000020
+#define PEI_MR_SMRAM_SIZE_8192K_MASK 0x00000040
+
+#define PEI_MR_SMRAM_ABSEG_128K_NOCACHE 0x00010001
+#define PEI_MR_SMRAM_HSEG_128K_CACHE 0x80020001
+#define PEI_MR_SMRAM_HSEG_128K_NOCACHE 0x00020001
+#define PEI_MR_SMRAM_TSEG_128K_CACHE 0x80040001
+#define PEI_MR_SMRAM_TSEG_128K_NOCACHE 0x00040001
+#define PEI_MR_SMRAM_TSEG_256K_CACHE 0x80040002
+#define PEI_MR_SMRAM_TSEG_256K_NOCACHE 0x00040002
+#define PEI_MR_SMRAM_TSEG_512K_CACHE 0x80040004
+#define PEI_MR_SMRAM_TSEG_512K_NOCACHE 0x00040004
+#define PEI_MR_SMRAM_TSEG_1024K_CACHE 0x80040008
+#define PEI_MR_SMRAM_TSEG_1024K_NOCACHE 0x00040008
+
+//
+// Graphics Memory Range
+//
+#define PEI_MEMORY_RANGE_GRAPHICS_MEMORY UINT32
+#define PEI_MR_GRAPHICS_MEMORY_ALL 0xFFFFFFFF
+#define PEI_MR_GRAPHICS_MEMORY_NONE 0x00000000
+#define PEI_MR_GRAPHICS_MEMORY_CACHEABLE 0x80000000
+//
+// If adding additional entries, Graphics Memory Size
+// is a multiple of 512KB.
+//
+#define PEI_MR_GRAPHICS_MEMORY_SIZE_MASK 0x0000FFFF
+#define PEI_MR_GRAPHICS_MEMORY_512K_NOCACHE 0x00000001
+#define PEI_MR_GRAPHICS_MEMORY_512K_CACHE 0x80000001
+#define PEI_MR_GRAPHICS_MEMORY_1M_NOCACHE 0x00000002
+#define PEI_MR_GRAPHICS_MEMORY_1M_CACHE 0x80000002
+#define PEI_MR_GRAPHICS_MEMORY_4M_NOCACHE 0x00000008
+#define PEI_MR_GRAPHICS_MEMORY_4M_CACHE 0x80000008
+#define PEI_MR_GRAPHICS_MEMORY_8M_NOCACHE 0x00000010
+#define PEI_MR_GRAPHICS_MEMORY_8M_CACHE 0x80000010
+#define PEI_MR_GRAPHICS_MEMORY_16M_NOCACHE 0x00000020
+#define PEI_MR_GRAPHICS_MEMORY_16M_CACHE 0x80000020
+#define PEI_MR_GRAPHICS_MEMORY_32M_NOCACHE 0x00000040
+#define PEI_MR_GRAPHICS_MEMORY_32M_CACHE 0x80000040
+#define PEI_MR_GRAPHICS_MEMORY_48M_NOCACHE 0x00000060
+#define PEI_MR_GRAPHICS_MEMORY_48M_CACHE 0x80000060
+#define PEI_MR_GRAPHICS_MEMORY_64M_NOCACHE 0x00000080
+#define PEI_MR_GRAPHICS_MEMORY_64M_CACHE 0x80000080
+#define PEI_MR_GRAPHICS_MEMORY_128M_NOCACHE 0x00000100
+#define PEI_MR_GRAPHICS_MEMORY_128M_CACHE 0x80000100
+#define PEI_MR_GRAPHICS_MEMORY_256M_NOCACHE 0x00000200
+#define PEI_MR_GRAPHICS_MEMORY_256M_CACHE 0x80000200
+//
+// Pci Memory Hole
+//
+#define PEI_MEMORY_RANGE_PCI_MEMORY UINT32
+#define PEI_MR_PCI_MEMORY_SIZE_512M_MASK 0x00000001
+
+typedef
+EFI_STATUS
+(EFIAPI *PEI_CHOOSE_RANGES) (
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN PEI_PLATFORM_MEMORY_RANGE_PPI * This,
+ IN OUT PEI_MEMORY_RANGE_OPTION_ROM * OptionRomMask,
+ IN OUT PEI_MEMORY_RANGE_SMRAM * SmramMask,
+ IN OUT PEI_MEMORY_RANGE_GRAPHICS_MEMORY * GraphicsMemoryMask,
+ IN OUT PEI_MEMORY_RANGE_PCI_MEMORY * PciMemoryMask
+ );
+
+struct _PEI_PLATFORM_MEMORY_RANGE_PPI {
+ PEI_CHOOSE_RANGES ChooseRanges;
+};
+
+extern EFI_GUID gPeiPlatformMemoryRangePpiGuid;
+
+#endif
diff --git a/ChvRefCodePkg/CherryViewSoc/NorthCluster/Include/Ppi/PlatformMemorySize.h b/ChvRefCodePkg/CherryViewSoc/NorthCluster/Include/Ppi/PlatformMemorySize.h new file mode 100644 index 0000000000..72dd7dfdbe --- /dev/null +++ b/ChvRefCodePkg/CherryViewSoc/NorthCluster/Include/Ppi/PlatformMemorySize.h @@ -0,0 +1,37 @@ +/** @file
+ Platform Memory Size PPI as defined in Tiano.
+ PPI for describing the minimum platform memory size in order to successfully
+ pass control into DXE.
+
+ Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _PEI_PLATFORM_MEMORY_SIZE_H_
+#define _PEI_PLATFORM_MEMORY_SIZE_H_
+
+EFI_FORWARD_DECLARATION (PEI_PLATFORM_MEMORY_SIZE_PPI);
+
+typedef
+EFI_STATUS
+(EFIAPI *PEI_GET_MINIMUM_PLATFORM_MEMORY_SIZE) (
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN PEI_PLATFORM_MEMORY_SIZE_PPI * This,
+ IN OUT UINT64 *MemorySize
+ );
+
+typedef struct _PEI_PLATFORM_MEMORY_SIZE_PPI {
+ PEI_GET_MINIMUM_PLATFORM_MEMORY_SIZE GetPlatformMemorySize;
+} PEI_PLATFORM_MEMORY_SIZE_PPI;
+
+extern EFI_GUID gPeiPlatformMemorySizePpiGuid;
+
+#endif
diff --git a/ChvRefCodePkg/CherryViewSoc/NorthCluster/Include/Ppi/SmmAccess.h b/ChvRefCodePkg/CherryViewSoc/NorthCluster/Include/Ppi/SmmAccess.h new file mode 100644 index 0000000000..3fb9810b82 --- /dev/null +++ b/ChvRefCodePkg/CherryViewSoc/NorthCluster/Include/Ppi/SmmAccess.h @@ -0,0 +1,138 @@ +/** @file
+ SmmAccess PPI
+ This code abstracts the PEI core to provide SmmAccess services.
+
+ Copyright (c) 2009 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _PEI_SMM_ACCESS_PPI_H_
+#define _PEI_SMM_ACCESS_PPI_H_
+
+typedef struct _PEI_SMM_ACCESS_PPI PEI_SMM_ACCESS_PPI;
+
+/**
+ This routine accepts a request to "open" a region of SMRAM. The
+ region could be legacy ABSEG, HSEG, or TSEG near top of physical memory.
+ The use of "open" means that the memory is visible from all PEIM
+ and SMM agents.
+
+ @param[in]
+ PeiServices - General purpose services available to every PEIM.
+ This - Pointer to the SMM Access Interface.
+ DescriptorIndex - Region of SMRAM to Open.
+
+ @retval
+ EFI_SUCCESS - The region was successfully opened.
+ EFI_DEVICE_ERROR - The region could not be opened because locked by
+ chipset.
+ EFI_INVALID_PARAMETER - The descriptor index was out of bounds.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *PEI_SMM_OPEN) (
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN PEI_SMM_ACCESS_PPI *This,
+ IN UINTN DescriptorIndex
+ );
+
+/**
+ This routine accepts a request to "close" a region of SMRAM. The
+ region could be legacy AB or TSEG near top of physical memory.
+ The use of "close" means that the memory is only visible from SMM agents,
+ not from PEIM.
+
+ @param[in]
+ PeiServices - General purpose services available to every PEIM.
+ This - Pointer to the SMM Access Interface.
+ DescriptorIndex - Region of SMRAM to Close.
+
+ @retval
+ EFI_SUCCESS - The region was successfully closed.
+ EFI_DEVICE_ERROR - The region could not be closed because locked by
+ chipset.
+ EFI_INVALID_PARAMETER - The descriptor index was out of bounds.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *PEI_SMM_CLOSE) (
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN PEI_SMM_ACCESS_PPI *This,
+ IN UINTN DescriptorIndex
+ );
+
+/**
+ This routine accepts a request to "lock" SMRAM. The
+ region could be legacy AB or TSEG near top of physical memory.
+ The use of "lock" means that the memory can no longer be opened
+ to PEIM.
+
+ @param[in]
+ PeiServices - General purpose services available to every PEIM.
+ This - Pointer to the SMM Access Interface.
+ DescriptorIndex - Region of SMRAM to Lock.
+
+ @retval
+ EFI_SUCCESS - The region was successfully locked.
+ EFI_DEVICE_ERROR - The region could not be locked because at least
+ one range is still open.
+ EFI_INVALID_PARAMETER - The descriptor index was out of bounds.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *PEI_SMM_LOCK) (
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN PEI_SMM_ACCESS_PPI *This,
+ IN UINTN DescriptorIndex
+ );
+
+/**
+ This routine services a user request to discover the SMRAM
+ capabilities of this platform. This will report the possible
+ ranges that are possible for SMRAM access, based upon the
+ memory controller capabilities.
+
+ @param[in]
+ PeiServices - General purpose services available to every PEIM.
+ This - Pointer to the SMRAM Access Interface.
+ SmramMapSize - Pointer to the variable containing size of the
+ buffer to contain the description information.
+ SmramMap - Buffer containing the data describing the Smram
+ region descriptors.
+ @retval
+ EFI_BUFFER_TOO_SMALL - The user did not provide a sufficient buffer.
+ EFI_SUCCESS - The user provided a sufficiently-sized buffer.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *PEI_SMM_CAPABILITIES) (
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN PEI_SMM_ACCESS_PPI *This,
+ IN OUT UINTN *SmramMapSize,
+ IN OUT EFI_SMRAM_DESCRIPTOR *SmramMap
+ );
+
+struct _PEI_SMM_ACCESS_PPI {
+ PEI_SMM_OPEN Open;
+ PEI_SMM_CLOSE Close;
+ PEI_SMM_LOCK Lock;
+ PEI_SMM_CAPABILITIES GetCapabilities;
+ BOOLEAN LockState;
+ BOOLEAN OpenState;
+};
+
+extern EFI_GUID gPeiSmmAccessPpiGuid;
+
+#endif
diff --git a/ChvRefCodePkg/CherryViewSoc/NorthCluster/Include/Protocol/ChvPlatformPolicyProtocol.h b/ChvRefCodePkg/CherryViewSoc/NorthCluster/Include/Protocol/ChvPlatformPolicyProtocol.h new file mode 100644 index 0000000000..1576124c31 --- /dev/null +++ b/ChvRefCodePkg/CherryViewSoc/NorthCluster/Include/Protocol/ChvPlatformPolicyProtocol.h @@ -0,0 +1,69 @@ +/** @file
+ Interface definition details between MCH and platform drivers during DXE phase.
+
+ Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _CHV_PLATFORM_POLICY_PROTOCOL_H_
+#define _CHV_PLATFORM_POLICY_PROTOCOL_H_
+
+//
+// Extern the GUID for protocol users.
+//
+#ifndef FSP_FLAG
+extern EFI_GUID gDxeChvPlatformPolicyGuid;
+#endif
+
+//
+// Protocol revision number
+// Any backwards compatible changes to this protocol will result in an update in the revision number
+// Major changes will require publication of a new protocol
+//
+#define DXE_CHV_PLATFORM_POLICY_PROTOCOL_REVISION 0
+
+typedef struct {
+ UINT8 PFITStatus;
+ UINT8 IgdTheramlSupport;
+ UINT8 ALSEnabled;
+ UINT8 LidStatus;
+} IGD_PANEL_FEATURES;
+
+//
+// CHV DXE Platform Policiy ==================================================
+//
+
+#define NO_AUDIO 0
+#define HD_AUDIO 1
+#define LPE_AUDIO 2
+
+typedef struct _DXE_CHV_PLATFORM_POLICY_PROTOCOL {
+ UINT8 Revision;
+ IGD_PANEL_FEATURES IgdPanelFeatures;
+ UINT8 EnableRenderStandby;
+ UINT8 MaxInverterPWM;
+ UINT8 MinInverterPWM;
+ UINT8 ForceWake;
+ UINT8 EuControl;
+ UINT8 PmWeights;
+ UINT8 PavpMode;
+ UINT8 S0ixSupported;
+ UINT8 AudioTypeSupport;
+ UINT8 EnableIGDTurbo;
+ UINT8 PowerMeterLock;
+ UINT8 PunitPwrConfigDisable;
+ UINT8 Wopcmsz;
+ UINT32 PAVP_PR3_MemLength;
+ UINT8 RPMBLock;
+ UINT8 PavpAsmf;
+} DXE_CHV_PLATFORM_POLICY_PROTOCOL;
+
+#endif
diff --git a/ChvRefCodePkg/CherryViewSoc/NorthCluster/Include/Protocol/GlobalNvsArea.h b/ChvRefCodePkg/CherryViewSoc/NorthCluster/Include/Protocol/GlobalNvsArea.h new file mode 100644 index 0000000000..f5813d33f4 --- /dev/null +++ b/ChvRefCodePkg/CherryViewSoc/NorthCluster/Include/Protocol/GlobalNvsArea.h @@ -0,0 +1,449 @@ +/** @file
+ Definition of the global NVS area protocol. This protocol
+ publishes the address and format of a global ACPI NVS buffer used as a communications
+ buffer between SMM code and ASL code.
+ The format is derived from the ACPI reference code, version 0.95.
+
+ Note: Data structures defined in this protocol are not naturally aligned.
+
+ Copyright (c) 2012 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _GLOBAL_NVS_AREA_H_
+#define _GLOBAL_NVS_AREA_H_
+
+//
+// Includes
+//
+#define GLOBAL_NVS_DEVICE_ENABLE 1
+#define GLOBAL_NVS_DEVICE_DISABLE 0
+
+//
+// Forward reference for pure ANSI compatibility
+//
+
+//EFI_FORWARD_DECLARATION (EFI_GLOBAL_NVS_AREA_PROTOCOL);
+
+//
+// Global NVS Area Protocol GUID
+//
+#define EFI_GLOBAL_NVS_AREA_PROTOCOL_GUID \
+{ 0x74e1e48, 0x8132, 0x47a1, 0x8c, 0x2c, 0x3f, 0x14, 0xad, 0x9a, 0x66, 0xdc }
+//
+// Revision id - Added TPM related fields
+//
+#define GLOBAL_NVS_AREA_RIVISION_1 1
+//
+// Extern the GUID for protocol users.
+//
+extern EFI_GUID gEfiGlobalNvsAreaProtocolGuid;
+
+//
+// Global NVS Area definition
+//
+#pragma pack (1)
+typedef struct {
+ ///
+ /// Miscellaneous Dynamic Values, the definitions below need to be matched
+ /// GNVS definitions in Platform.ASL
+ ///
+ UINT16 OperatingSystem; // 00 Operating System
+ UINT8 SmiFunction; // 02 SMI function call via IO Trap
+ UINT32 Port80DebugValue; // 03 Port 80 Debug Port Value
+ UINT8 Revision; // 07 Revision of the structure EFI_GLOBAL_NVS_AREA
+ UINT8 OSImageId; // 08 OS identification.
+ UINT8 AcpiDevDis; // 09 Enable Or Disable Acpi Device Nodes
+ UINT8 BoardID; // 10 Board ID
+ UINT8 FabID; // 11 FAB ID
+ UINT8 ECSupport; // 12 EC Support
+ UINT8 FanSupport; // 13 Fan Support
+ UINT8 BatterySupport; // 14 Battery Support
+ UINT8 Reserved51[9]; // 15:23 Reserved for Platform Policies
+
+ ///
+ /// Processor Configuration Values
+ ///
+ UINT8 ApicEnable; // 24 APIC Enabled by SBIOS (APIC Enabled = 1)
+ UINT8 LogicalProcessorCount; // 25 Number of Logical Processors if MP Enabled != 0
+ UINT32 PpmFlags; // 26 PPM configuration flags, same as CFGD
+ UINT8 PowerState; // 30 Power State (AC Mode = 1)
+ UINT8 Reserved52[10]; // 31:40 Reserved for CPU Policies
+
+ ///
+ /// System Agent Policies
+ ///
+ /// Internal Graphics Device Values
+ ///
+ UINT8 IgdState; // 41 IGD State (Primary Display = 1)
+ UINT8 DisplayToggleList; // 42 Display Toggle List Selection
+ UINT8 CurrentDeviceList; // 43 Current Attached Device List
+ UINT8 PreviousDeviceList; // 44 Previous Attached Device List
+ UINT16 CurrentDisplayState; // 45 Current Display State
+ UINT16 NextDisplayState; // 47 Next Display State
+ UINT8 NumberOfValidDeviceId; // 49 Number of Valid Device IDs
+ UINT32 DeviceId1; // 50 Device ID 1
+ UINT32 DeviceId2; // 54 Device ID 2
+ UINT32 DeviceId3; // 58 Device ID 3
+ UINT32 DeviceId4; // 62 Device ID 4
+ UINT32 DeviceId5; // 66 Device ID 5
+ UINT32 DeviceId6; // 70 Device ID 6
+ UINT32 DeviceId7; // 74 Device ID 7
+ UINT32 DeviceId8; // 78 Device ID 8
+ UINT32 IgdOpRegionAddress; // 82 IGD OpRegion base Address
+ UINT8 IgdBootType; // 86 IGD Boot Display Device
+ UINT8 IgdPanelType; // 87 IGD Panel Type CMOs option
+ UINT8 IgdTvFormat; // 88 IGD TV Format CMOS option
+ UINT8 IgdTvMinor; // 89 IGD TV Minor Format CMOS option
+ UINT8 IgdPanelScaling; // 90 IGD Panel Scaling
+ UINT8 IgdBlcConfig; // 91 IGD BLC Configuration
+ UINT8 IgdBiaConfig; // 92 IGD BIA Configuration
+ UINT8 IgdSscConfig; // 93 IGD SSC Configuration
+ UINT8 IgdPowerConservation; // 94 IGD Power Conservation Feature Flag
+ UINT8 IgdDvmtMemSize; // 95 IGD DVMT Memory Size
+ UINT8 IgdFunc1Enable; // 96 IGD Function 1 Enable
+ UINT8 IgdSciSmiMode; // 97 GMCH SMI/SCI mode (0=SCI)
+ UINT8 IgdPAVP; // 98 IGD PAVP data
+ UINT8 PanelVendor; // 99 MIPI Display Panel Vendor
+
+ ///
+ /// Backlight Control Values
+ ///
+ UINT8 BacklightControlSupport; // 100 Backlight Control Support
+ UINT8 BrightnessPercentage; // 101 Brightness Level Percentage
+
+ ///
+ /// Ambient Light Sensor Values
+ ///
+ UINT8 AlsEnable; // 102 Ambient Light Sensor Enable
+ UINT8 AlsAdjustmentFactor; // 103 Ambient Light Adjustment Factor
+ UINT8 LuxLowValue; // 104 LUX Low Value
+ UINT8 LuxHighValue; // 105 LUX High Value
+
+ ///
+ /// Camera
+ ///
+ UINT32 ISPAddr; // 106 ISP Base address
+ UINT8 ISPDevSel; // 110 ISP device enabled selection 0: Disabled; 1: PCI Device 2; 2: PCI Device 3
+ UINT8 RvpCameraDevSel; // 111 Camera selection 0 - Cynthiana_A, 1 - Cynthiana_2B, 2 - Cynthiana_2B_CR
+ UINT8 EbCameraDevSel; // 112 COMBO AIC 0 - Disable, 1 - Enable
+
+ UINT32 NvIgOpRegionAddress; // 113 NVIG support
+ UINT32 NvHmOpRegionAddress; // 117 NVHM support
+ UINT32 ApXmOpRegionAddress; // 121 AMDA support
+
+ ///
+ /// Hybrid Graphics Support
+ ///
+ UINT8 HgMode; // 125 HG Mode (0=Disabled, 1=HG Muxed, 2=HG Muxless, 3=DGPU Only)
+ UINT32 GpioBaseAddress; // 126 GPIO Base Address
+ UINT32 XPcieCfgBaseAddress; // 130 Any Device's PCIe Config Space Base Address
+ UINT8 HgGpioSupport; // 134 HG GPIO Support
+ UINT16 HgDelayAfterPwrEn; // 135 Delay after Power Enable
+ UINT16 HgDelayAfterHoldReset; // 137 Delay after Hold Reset
+ UINT32 HgHoldRstCommOffset; // 139 dGPU HLD RST GPIO Community Offset
+ UINT32 HgHoldRstPinOffset; // 143 dGPU HLD RST GPIO Pin Offset
+ UINT8 HgHoldRstActiveInfo; // 147 dGPU HLD RST GPIO Active Information
+ UINT32 HgPwrEnableCommOffset; // 148 dGPU PWR Enable GPIO Community Offset
+ UINT32 HgPwrEnablePinOffset; // 152 dGPU PWR Enable GPIO Pin Offset
+ UINT8 HgPwrEnableActiveInfo; // 156 dGPU PWR Enable GPIO Active Information
+ UINT32 CapStrPresence; // 157 PEG Endpoint Capability Structure Presence
+ UINT8 EndpointPcieCapOffset; // 161 PEG Endpoint PCIe Capability Structure Offset
+ UINT16 EndpointVcCapOffset; // 162 PEG Endpoint Virtual Channel Capability Structure Offset
+ UINT32 RootPortBaseAddress; // 164 dGPU Root Port Base Address
+ UINT32 DeviceIdX; // 168 Device ID for eDP device
+ UINT8 EdpValid; // 172 Check for eDP display device
+
+ UINT8 Reserved53[9]; // 173: 181 Reserved for North Cluster policies
+
+ ///
+ /// Security Policies
+ ///
+ ///
+ /// TPM Registers
+ ///
+ UINT8 Reserved_182; // 182
+ UINT8 Reserved_183; // 183
+ UINT32 Reserved_184; // 184
+ UINT32 Reserved_188; // 188
+ UINT8 Reserved_192; // 192
+ UINT8 Reserved_193; // 193
+ UINT32 Reserved_194; // 194
+ UINT8 Reserved_198; // 198
+ UINT8 Reserved_199; // 199
+ UINT8 I2C0RuntimeD3Enabled; // 200 I2C 1 Runtime D3 Support
+ UINT8 I2C1RuntimeD3Enabled; // 201 I2C 2 Runtime D3 Support
+ UINT8 I2C2RuntimeD3Enabled; // 202 I2C 3 Runtime D3 Support
+ UINT8 I2C3RuntimeD3Enabled; // 203 I2C 4 Runtime D3 Support
+ UINT8 I2C4RuntimeD3Enabled; // 204 I2C 5 Runtime D3 Support
+ UINT8 I2C5RuntimeD3Enabled; // 205 I2C 6 Runtime D3 Support
+ UINT8 I2C6RuntimeD3Enabled; // 206 I2C 7 Runtime D3 Support
+ UINT8 Reserved54[3]; // 207: 209 Reserved for Security policies
+
+ ///
+ /// PCH policies
+ ///
+ UINT8 PchLpeEnabled; // 210 LPE Audio Enabled
+ UINT8 Reserved11[9]; // 211: 219
+ ///
+ /// USB Sideband Deferring Support
+ ///
+ UINT32 UsbOtgAddr; // 220 USB OTG BAR0
+ UINT32 UsbOtgAddr1; // 224 USB OTG BAR1
+ UINT8 OtgMode; // 228 OTG Mode 0- OTG disable 1- OTG PCI mode
+ UINT32 LPEBar0; // 229 LPE Bar0
+ UINT32 LPEBar1; // 233 LPE Bar1
+ UINT32 LPEBar2; // 237 LPE Bar2
+ UINT8 PlatformFlavor; // 241 Platform Flavor 0:unknown 1: Mobile; 2: desktop
+ UINT8 XhciMode; // 242 xHCI controller mode
+ UINT8 PmicEnable; // 243 PMIC enable/disable
+ UINT8 UartSelection; // 244 UART Interface Selection 0: Internal; 1: SIO
+ UINT8 BTHStatus; // 245 BTH Device Select
+ UINT8 emmcVersion; // 246 eMMC controller version 0 - 4.41 1 - 4.5
+ UINT8 GpioAcpiEnabled; // 247 GPIO ACPI Devices Enable
+ UINT32 LDMA1Addr; // 248 DMA1 BAR0
+ UINT32 LDMA1Len; // 252 DMA1 BAR0 Length
+ UINT32 LDMA11Addr; // 256 DMA1 BAR1
+ UINT32 LDMA11Len; // 260 DMA1 BAR1 Length
+ UINT32 PWM1Addr; // 264 PWM1 BAR0
+ UINT32 PWM1Len; // 268 PWM1 BAR0 Length
+ UINT32 PWM11Addr; // 272 PWM1 BAR1
+ UINT32 PWM11Len; // 276 PWM1 BAR1 Length
+ UINT32 PWM2Addr; // 280 PWM2 BAR0
+ UINT32 PWM2Len; // 284 PWM2 BAR0 Length
+ UINT32 PWM21Addr; // 288 PWM2 BAR1
+ UINT32 PWM21Len; // 292 PWM2 BAR1 Length
+ UINT32 UART1Addr; // 296 HSUART1 BAR0
+ UINT32 UART1Len; // 300 HSUART1 BAR0 Length
+ UINT32 UART11Addr; // 304 HSUART1 BAR1
+ UINT32 UART11Len; // 308 HSUART1 BAR1 Length
+ UINT32 UART2Addr; // 312 HSUART2 BAR0
+ UINT32 UART2Len; // 316 HSUART2 BAR0 Length
+ UINT32 UART21Addr; // 320 HSUART2 BAR1
+ UINT32 UART21Len; // 324 HSUART2 BAR1 Length
+ UINT32 SPIAddr; // 328 SPI BAR0
+ UINT32 SPILen; // 332 SPI BAR0 Length
+ UINT32 SPI1Addr; // 336 SPI BAR1
+ UINT32 SPI1Len; // 340 SPI BAR1 Length
+ UINT32 SPI2Addr; // 344 SPI2 BAR0
+ UINT32 SPI2Len; // 348 SPI2 BAR0 Length
+ UINT32 SPI21Addr; // 352 SPI2 BAR1
+ UINT32 SPI21Len; // 356 SPI2 BAR1 Length
+ UINT32 SPI3Addr; // 360 SPI3 BAR0
+ UINT32 SPI3Len; // 364 SPI3 BAR0 Length
+ UINT32 SPI31Addr; // 368 SPI3 BAR1
+ UINT32 SPI31Len; // 372 SPI3 BAR1 Length
+ UINT32 LDMA2Addr; // 376 DMA2 BAR0
+ UINT32 LDMA2Len; // 380 DMA2 BAR0 Length
+ UINT32 LDMA21Addr; // 384 DMA2 BAR1
+ UINT32 LDMA21Len; // 388 DMA2 BAR1 Length
+ UINT32 I2C1Addr; // 392 I2C1 BAR0
+ UINT32 I2C1Len; // 396 I2C1 BAR0 Length
+ UINT32 I2C11Addr; // 400 I2C1 BAR1
+ UINT32 I2C11Len; // 404 I2C1 BAR1 Length
+ UINT32 I2C2Addr; // 408 I2C2 BAR0
+ UINT32 I2C2Len; // 412 I2C2 BAR0 Length
+ UINT32 I2C21Addr; // 416 I2C2 BAR1
+ UINT32 I2C21Len; // 420 I2C2 BAR1 Length
+ UINT32 I2C3Addr; // 424 I2C3 BAR0
+ UINT32 I2C3Len; // 428 I2C3 BAR0 Length
+ UINT32 I2C31Addr; // 432 I2C3 BAR1
+ UINT32 I2C31Len; // 436 I2C3 BAR1 Length
+ UINT32 I2C4Addr; // 440 I2C4 BAR0
+ UINT32 I2C4Len; // 444 I2C4 BAR0 Length
+ UINT32 I2C41Addr; // 448 I2C4 BAR1
+ UINT32 I2C41Len; // 452 I2C4 BAR1 Length
+ UINT32 I2C5Addr; // 456 I2C5 BAR0
+ UINT32 I2C5Len; // 460 I2C5 BAR0 Length
+ UINT32 I2C51Addr; // 464 I2C5 BAR1
+ UINT32 I2C51Len; // 468 I2C5 BAR1 Length
+ UINT32 I2C6Addr; // 472 I2C6 BAR0
+ UINT32 I2C6Len; // 476 I2C6 BAR0 Length
+ UINT32 I2C61Addr; // 480 I2C6 BAR1
+ UINT32 I2C61Len; // 484 I2C6 BAR1 Length
+ UINT32 I2C7Addr; // 488 I2C7 BAR0
+ UINT32 I2C7Len; // 492 I2C7 BAR0 Length
+ UINT32 I2C71Addr; // 496 I2C7 BAR1
+ UINT32 I2C71Len; // 500 I2C7 BAR1 Length
+ UINT32 eMMCAddr; // 504 eMMC BAR0
+ UINT32 eMMCLen; // 508 eMMC BAR0 Length
+ UINT32 eMMC1Addr; // 512 eMMC BAR1
+ UINT32 eMMC1Len; // 516 eMMC BAR1 Length
+ UINT32 SDIOAddr; // 520 SDIO BAR0
+ UINT32 SDIOLen; // 524 SDIO BAR0 Length
+ UINT32 SDIO1Addr; // 528 SDIO BAR1
+ UINT32 SDIO1Len; // 532 SDIO BAR1 Length
+ UINT32 SDCardAddr; // 536 SDCard BAR0
+ UINT32 SDCardLen; // 540 SDCard BAR0 Length
+ UINT32 SDCard1Addr; // 544 SDCard BAR1
+ UINT32 SDCard1Len; // 548 SDSCard BAR1 Length
+ UINT32 IshAddr; // 552 ISH BAR0
+ UINT32 IshAddr1; // 556 ISH BAR1
+ UINT16 Sdcard1p8vSwitchingDelay;// 560 SD Card 1.8 Volt Switching Delay (ms)
+ UINT16 Sdcard3p3vDischargeDelay;// 562 SD Card 3.3 Volt Discharge Delay (ms)
+ UINT16 Reserved25[2]; // 564 : 567
+ UINT8 I2CTouchAddress; // 568 I2C touch address, 0x4B:RVP 0x4A:FFRD
+ UINT8 S0ix; // 569 S0ix status 0 - disabled 1 - enabled
+ UINT8 SDIOMode; // 570 SDIO Mode 3 - Default 2 - DDR50
+ UINT8 Ellensburg; // 571 Support EllensBurg
+ UINT8 AudioCodecSuppport; // 572 Support for Audio Codec
+ UINT8 BTModuleSelect; // 573 BT Module Select: BCRM or STP
+ UINT8 PmicType; // 574 PmicType
+ UINT8 PssdFix; // 575 Pre-Sillicon Work Arounds for ASL. 1-PSSD, 0-Normal
+ UINT8 Reserved55[9]; // 576 : 584 Reserved for PCH policies
+
+ ///
+ /// Platform policies
+ ///
+ UINT8 PcieOSCControl; // 585 PCIE OSC Control
+ UINT8 NativePCIESupport; // 586 Native PCI Express Support
+ UINT8 IoApicInterruptFlag; // 587 Global IOAPIC/8259 Interrupt Mode Flag
+ UINT8 L01Counter; // 588 Global L01 Counter
+ UINT8 AcpiModemSel; // 589
+ UINT8 VirtualButtonSupport; // 590 BSW Virtual Button Support
+ UINT8 PssDevice; // 591
+ UINT8 IsctCfg; // 592
+
+ ///
+ /// EC
+ ///
+ UINT8 LidState; // 593 Lid State (Lid Open = 1)
+ UINT8 DosEn; // 594 _DOS Display Support Flag.
+ UINT8 EcAvl; // 595 Embedded Controller Availability Flag.
+
+ ///
+ /// Thermal Policy Values
+ ///
+ UINT8 Reserved1; // 596 Active Trip Point 1
+ UINT8 Reserved2; // 597 Active Trip Point
+ UINT8 PassiveThermalTripPoint; // 598 Passive Trip Point
+ UINT8 PassiveTc1Value; // 599 Passive Trip Point TC1 Value
+ UINT8 PassiveTc2Value; // 600 Passive Trip Point TC2 Value
+ UINT8 PassiveTspValue; // 601 Passive Trip Point TSP Value
+ UINT8 CriticalThermalTripPoint; // 602 Critical Trip Point
+ UINT8 EnableDigitalThermalSensor; // 603 Digital Thermal Sensor Enable
+ UINT8 BspDigitalThermalSensorTemperature; // 604 Digital Thermal Sensor 1 Reading Temperature of BSP
+ UINT8 ApDigitalThermalSensorTemperature; // 605 Digital Thermal Sensor 2 Reading Temperature of AP
+ UINT8 DigitalThermalSensorSmiFunction; // 606 DTS SMI function call via DTS IO Trap
+ UINT8 CoolingType; // 607 Global Cooling Type Flag
+ UINT8 VirtualFan0Status; // 608 Virtual Fan 0 Status
+ UINT16 Str2TspValue; // 609 10 - Minimum 500 - Maximum
+
+ ///
+ /// Battery Support Values
+ ///
+ UINT8 NumberOfBatteries; // 611 Battery Number Present
+ UINT8 BatteryCapacity0; // 612 Battery 0 Stored Capacity
+ UINT8 BatteryCapacity1; // 613 Battery 1 Stored Capacity
+ UINT8 BatteryStatus0; // 614 Battery 0 Stored Status
+ UINT8 BatteryStatus1; // 615 Battery 1 Stored Status
+ UINT8 BatteryChargingSolution; // 616 Battery charging solution 0-CLV 1-ULPMC
+ UINT8 DisableBattery; // 617
+
+ ///
+ /// SIO Configuration Values
+ ///
+ UINT8 DockedSioPresent; // 618 Dock SIO Present
+ UINT8 OnboardCom; // 619 Onboard COM Port
+ UINT8 OnboardComCir; // 620 Onboard COM CIR Port
+ UINT8 WPCN381U; // 621
+
+ ///
+ /// DPTF
+ ///
+ UINT8 DptfEnable; // 622 DPTF Enable/Disable
+ UINT8 DptfSysThermal0; // 623 System Thermal Sensor 0
+ UINT8 DptfSysThermal1; // 624 System Thermal Sensor 1
+ UINT8 DptfSysThermal2; // 625 System Thermal Sensor 2
+ UINT8 DptfSysThermal3; // 626 System Thermal Sensor 3
+ UINT8 DptfSysThermal4; // 627 System Thermal Sensor 4
+ UINT8 DptfCharger; // 628 DPTF Changer Device
+ UINT8 DptfDisplayDevice; // 629 DPTF Display Device
+ UINT8 DptfSocDevice; // 630 DPTF SoC Device
+ UINT8 DptfProcessor; // 631 DPTF Processor Device
+ UINT32 DptfProcCriticalTemperature; // 632 DPTF Processor participant critical temperature
+ UINT32 DptfProcPassiveTemperature; // 636 DPTF Processor participant passive temperature
+ UINT32 DptfGenericCriticalTemperature0; // 640 DPTF Generic sensor0 participant critical temperature
+ UINT32 DptfGenericPassiveTemperature0; // 644 DPTF Generic sensor0 participant passive temperature
+ UINT32 DptfGenericCriticalTemperature1; // 648 DPTF Generic sensor1 participant critical temperature
+ UINT32 DptfGenericPassiveTemperature1; // 652 DPTF Generic sensor1 participant passive temperature
+ UINT32 DptfGenericCriticalTemperature2; // 656 DPTF Generic sensor2 participant critical temperature
+ UINT32 DptfGenericPassiveTemperature2; // 660 DPTF Generic sensor2 participant passive temperature
+ UINT32 DptfGenericCriticalTemperature3; // 664 DPTF Generic sensor3 participant critical temperature
+ UINT32 DptfGenericPassiveTemperature3; // 668 DPTF Generic sensor3 participant passive temperature
+ UINT32 DptfGenericCriticalTemperature4; // 672 DPTF Generic sensor4 participant critical temperature
+ UINT32 DptfGenericPassiveTemperature4; // 676 DPTF Generic sensor4 participant passive temperature
+ UINT8 CLpmSetting; // 680 DPTF current low power mode setting
+ UINT32 DptfCriticalThreshold0; // 681 DPTF Critical threshold0 for SCU
+ UINT32 DptfCriticalThreshold1; // 685 DPTF Critical threshold1 for SCU
+ UINT32 DptfCriticalThreshold2; // 689 DPTF Critical threshold2 for SCU
+ UINT32 DptfCriticalThreshold3; // 693 DPTF Critical threshold3 for SCU
+ UINT32 DptfCriticalThreshold4; // 697 DPTF Critical threshold4 for SCU
+ UINT8 DptfSuperDbg; // 701 DPTF Super Debug option. 0 - Disabled, 1 - Enabled
+ UINT32 LPOEnable; // 702 DPTF LPO Enable
+ UINT32 LPOStartPState; // 706 P-State start index
+ UINT32 LPOStepSize; // 710 Step size
+ UINT32 LPOPowerControlSetting; // 714 Power control setting
+ UINT32 LPOPerformanceControlSetting; // 718 Performance control setting
+ UINT8 DppmEnabled; // 722 DPTF: DPPM enable/disable
+ UINT8 DptfWwanDevice; // 723 DPTF WWAN
+ UINT32 DptfWwanCrt; // 724 DPTF WWAN critical temp
+ UINT32 DptfWwanPsv; // 728 DPTF WWAN Passive temp
+ UINT8 DptfMemDevice; // 732 DPTF Memory Participant
+ UINT8 AmbientConstantSign[6]; // 733:738 DPTF:Sign of Amb. Const
+ UINT8 AmbientTripPointChange; // 739 DPTF: Controls whether _ATI changes other participant's trip point(enabled/disabled)
+
+ UINT8 AmbientConstants[6]; // 740:745 DPTF: #IMP# Takes 6 bytes
+ UINT8 DisplayHighLimit; // 746
+ UINT8 DisplayLowLimit; // 747
+
+ UINT8 NfcConnection; // 748 NFC Connection 1:I2C7 2:SEC
+
+ UINT32 BmBound; // 749 BM Bound //USED
+ UINT8 FsaStatus; // 753 FSA Status 0 - Fsa is off, 1- Fsa is on
+
+ UINT8 WIFIModuleSelect; // 754 WIFI Module Select: BCRM or STP
+ UINT8 EnablePassivePolicy; // 755 DPTF: Passive Policy enable/disable
+ UINT8 EnableCriticalPolicy; // 756 DPTF: Critical Policy enable/disable
+ UINT8 EnableActivePolicy; // 757 DPTF: Active Policy enable/disable
+ UINT32 DptfGenericActiveTemperature0; // 758 DPTF Generic sensor0 participant Active temperature
+ UINT32 DptfGenericCR3Temperature0; // 762 DPTF Generic sensor0 participant CR3 temperature
+ UINT32 DptfGenericHotTemperature0; // 766 DPTF Generic sensor0 participant HOT temperature
+ UINT32 DptfGenericActiveTemperature1; // 770 DPTF Generic sensor1 participant Active temperature
+ UINT32 DptfGenericCR3Temperature1; // 774 DPTF Generic sensor1 participant CR3 temperature
+ UINT32 DptfGenericHotTemperature1; // 778 DPTF Generic sensor1 participant HOT temperature
+ UINT32 DptfGenericActiveTemperature2; // 782 DPTF Generic sensor2 participant Active temperature
+ UINT32 DptfGenericCR3Temperature2; // 786 DPTF Generic sensor2 participant CR3 temperature
+ UINT32 DptfGenericHotTemperature2; // 790 DPTF Generic sensor2 participant HOT temperature
+ UINT32 DptfProcActiveTemperatureSA; // 794 DPTF Processor participant active temperature
+ UINT32 DptfProcCriticalTemperatureSA; // 798 DPTF Processor participant critical temperature
+ UINT32 DptfProcCR3TemperatureSA; // 802 DPTF Processor participant CR3 temperature
+ UINT32 DptfProcHotTemperatureSA; // 806 DPTF Processor participant Hot temperature
+ UINT32 DptfProcPassiveTemperatureSA; // 810 DPTF Processor participant passive temperature
+
+ UINT8 ToggleSelfClkDisabling; // 814 Toggle Self Clock Disabling Feature: Enable/Disable in ASL
+ UINT8 ISPEn; // 815 ISP Device Enable/Disable
+ UINT32 PAVPSerpentMemBase; // 816 PAVP Memory Base
+ UINT32 PAVPSerpentMemLength; // 820 PAVP Memory Length
+ UINT64 Drmb; // 824 DRM DMA Allocated Buffer Address
+
+} EFI_GLOBAL_NVS_AREA;
+
+#pragma pack ()
+
+//
+// Global NVS Area Protocol
+//
+typedef struct _EFI_GLOBAL_NVS_AREA_PROTOCOL {
+ EFI_GLOBAL_NVS_AREA *Area;
+} EFI_GLOBAL_NVS_AREA_PROTOCOL;
+
+#endif
diff --git a/ChvRefCodePkg/CherryViewSoc/NorthCluster/Include/Protocol/GopComponentName2.h b/ChvRefCodePkg/CherryViewSoc/NorthCluster/Include/Protocol/GopComponentName2.h new file mode 100644 index 0000000000..4239c94697 --- /dev/null +++ b/ChvRefCodePkg/CherryViewSoc/NorthCluster/Include/Protocol/GopComponentName2.h @@ -0,0 +1,69 @@ +/** @file
+ Protocol to retrieve the GOP driver version
+
+ Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _GOP_COMPONENT_NAME2_H_
+#define _GOP_COMPONENT_NAME2_H_
+
+typedef struct _GOP_COMPONENT_NAME2_PROTOCOL GOP_COMPONENT_NAME2_PROTOCOL;
+
+///
+/// GOP Component protocol for retrieving driver name
+///
+typedef
+EFI_STATUS
+(EFIAPI *GOP_COMPONENT_NAME2_GET_DRIVER_NAME) (
+ IN GOP_COMPONENT_NAME2_PROTOCOL *This,
+ IN CHAR8 *Language,
+ OUT CHAR16 **DriverName
+ );
+
+///
+/// GOP Component protocol for retrieving controller name
+///
+typedef
+EFI_STATUS
+(EFIAPI *GOP_COMPONENT_NAME2_GET_CONTROLLER_NAME) (
+ IN GOP_COMPONENT_NAME2_PROTOCOL *This,
+ IN EFI_HANDLE ControllerHandle,
+ IN EFI_HANDLE ChildHandle OPTIONAL,
+ IN CHAR8 *Language,
+ OUT CHAR16 **ControllerName
+ );
+
+///
+/// GOP Component protocol for retrieving driver version
+///
+typedef
+EFI_STATUS
+(EFIAPI *GOP_COMPONENT_NAME2_GET_DRIVER_VERSION) (
+ IN GOP_COMPONENT_NAME2_PROTOCOL *This,
+ IN CHAR8 *Language,
+ OUT CHAR16 **DriverVersion
+ );
+
+/**
+ GOP Component protocol\n
+ This protocol will be installed by GOP driver and can be used to retrieve GOP information.
+**/
+struct _GOP_COMPONENT_NAME2_PROTOCOL {
+ GOP_COMPONENT_NAME2_GET_DRIVER_NAME GetDriverName; ///< Protocol function to get driver name
+ GOP_COMPONENT_NAME2_GET_DRIVER_VERSION GetDriverVersion; ///< Protocol function to get driver version
+ GOP_COMPONENT_NAME2_GET_CONTROLLER_NAME GetControllerName; ///< Protocol function to get controller name
+ CHAR8 *SupportedLanguages; ///< Number of Supported languages.
+};
+
+extern EFI_GUID gGopComponentName2ProtocolGuid;
+
+#endif
diff --git a/ChvRefCodePkg/CherryViewSoc/NorthCluster/Include/Protocol/IgdOpRegion.h b/ChvRefCodePkg/CherryViewSoc/NorthCluster/Include/Protocol/IgdOpRegion.h new file mode 100644 index 0000000000..7142c0d966 --- /dev/null +++ b/ChvRefCodePkg/CherryViewSoc/NorthCluster/Include/Protocol/IgdOpRegion.h @@ -0,0 +1,202 @@ +/** @file
+ This file is part of the IGD OpRegion Implementation. The IGD OpRegion is
+ an interface between system BIOS, ASL code, and Graphics drivers.
+
+ Supporting Specifiction: IGD OpRegion/Software SCI SPEC
+
+ Note: Data structures defined in this protocol are packed not naturally
+ aligned.
+
+ GUID forms:
+ {CDC5DDDF-E79D-41ec-A9B0-6565490DB9D3}
+ (0xcdc5dddf, 0xe79d, 0x41ec, 0xa9, 0xb0, 0x65, 0x65, 0x49, 0xd, 0xb9, 0xd3);
+
+ Acronyms:
+ NVS: ACPI Non Volatile Storage
+ OpRegion: ACPI Operational Region
+ VBT: Video BIOS Table (OEM customizable data)
+
+ Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _IGD_OPREGION_PROTOCOL_H_
+#define _IGD_OPREGION_PROTOCOL_H_
+
+//
+// Extern the GUID for protocol users.
+//
+extern EFI_GUID gIgdOpRegionProtocolGuid;
+
+//
+// Forward reference for pure ANSI compatability
+//
+typedef struct _IGD_OPREGION_PROTOCOL IGD_OPREGION_PROTOCOL;
+
+//
+// Protocol data definitions
+//
+
+//
+// OpRegion structures:
+// Sub-structures define the different parts of the OpRegion followed by the
+// main structure representing the entire OpRegion.
+//
+// Note: These structures are packed to 1 byte offsets because the exact
+// data location is requred by the supporting design specification due to
+// the fact that the data is used by ASL and Graphics driver code compiled
+// separatly.
+//
+
+//
+// OpRegion header (mailbox 0) structure and #defines.
+//
+#pragma pack (1)
+typedef struct {
+ CHAR8 SIGN[0x10]; // 0 OpRegion signature
+ UINT32 SIZE; // 0x10 OpRegion size
+ UINT32 OVER; // 0x14 OpRegion structure version
+ UINT8 SVER[0x20]; // 0x18 System BIOS build version
+ UINT8 VVER[0x10]; // 0x38 Video BIOS build version
+ UINT8 GVER[0x10]; // 0x48 Graphic driver build version
+ UINT32 MBOX; // 0x58 Mailboxes supported
+ UINT32 DMOD; // 0x5C Driver Model
+ UINT32 PCON; // 0x60 Platform Configuration Info
+ CHAR8 GOPV[0x20]; // 0X64 GOP build version
+ UINT8 RSV[0x7C]; // Reserved
+} OPREGION_HEADER;
+#pragma pack ()
+
+//
+// OpRegion mailbox 1 (public ACPI Methods).
+//
+#pragma pack (1)
+typedef struct {
+ UINT32 DRDY; // 0 Driver readiness
+ UINT32 CSTS; // 4 Status
+ UINT32 CEVT; // 8 Current event
+ UINT8 RM11[0x14]; // 12 Reserved
+ UINT32 DIDL; // 32 Supported display devices list
+ UINT32 DDL2; // 8 Devices.
+ UINT32 DDL3;
+ UINT32 DDL4;
+ UINT32 DDL5;
+ UINT32 DDL6;
+ UINT32 DDL7;
+ UINT32 DDL8;
+ UINT32 CPDL; // 64 Currently present display devices list
+ UINT32 CPL2; // 8 Devices.
+ UINT32 CPL3;
+ UINT32 CPL4;
+ UINT32 CPL5;
+ UINT32 CPL6;
+ UINT32 CPL7;
+ UINT32 CPL8;
+ UINT32 CADL; // 96 Currently active display devices list
+ UINT32 CAL2; // 8 Devices.
+ UINT32 CAL3;
+ UINT32 CAL4;
+ UINT32 CAL5;
+ UINT32 CAL6;
+ UINT32 CAL7;
+ UINT32 CAL8;
+ UINT32 NADL; // 128 Next active device list
+ UINT32 NDL2; // 8 Devices.
+ UINT32 NDL3;
+ UINT32 NDL4;
+ UINT32 NDL5;
+ UINT32 NDL6;
+ UINT32 NDL7;
+ UINT32 NDL8;
+ UINT32 ASLP; // 160 ASL sleep timeout
+ UINT32 TIDX; // 164 Toggle table index
+ UINT32 CHPD; // 168 Current hot plug enable indicator
+ UINT32 CLID; // 172 Current lid state indicator
+ UINT32 CDCK; // 176 Current docking state indicator
+ UINT32 SXSW; // 180 Display Switch notification on Sx State resume
+ UINT32 EVTS; // 184 Events supported by ASL
+ UINT32 CNOT; // 188 Current OS Notification
+ UINT32 NRDY; // 192 Reasons for DRDY = 0
+ UINT8 RM12[0x3C]; // 196 Reserved
+} OPREGION_MBOX1;
+#pragma pack ()
+
+//
+// OpRegion mailbox 2 (Software SCI Interface).
+//
+#pragma pack (1)
+typedef struct {
+ UINT32 SCIC; // 0 Software SCI function number parameters
+ UINT32 PARM; // 4 Software SCI additional parameters
+ UINT32 DSLP; // 8 Driver sleep timeout
+ UINT8 RM21[0xF4]; // 12 Reserved
+} OPREGION_MBOX2;
+#pragma pack ()
+
+//
+// OpRegion mailbox 3 (Power Conservation).
+//
+#pragma pack (1)
+typedef struct {
+ UINT32 ARDY; // 0 Driver readiness
+ UINT32 ASLC; // 4 ASLE interrupt command / status
+ UINT32 TCHE; // 8 Technology enabled indicator
+ UINT32 ALSI; // 12 Current ALS illuminance reading
+ UINT32 BCLP; // 16 Backlight britness to set
+ UINT32 PFIT; // 20 Panel fitting Current State or Request
+ UINT32 CBLV; // 24 Brightness Current State
+ UINT16 BCLM[0x14]; // 28 Backlight Brightness Level Duty Cycle Mapping Table
+ UINT32 CPFM; // 68 Panel Fitting Current Mode
+ UINT32 EPFM; // 72 Enabled Panel Fitting Mode
+ UINT8 PLUT[0x4A]; // 76 Panel Look Up Table
+ UINT32 PFMB; // 150 PWM Frequency and Minimum Brightness
+ UINT32 CCDV; // 154 Color Correction Default Values
+ UINT32 PCFT; // 158 Power Conservation Features
+ UINT8 RM31[0x5E]; // 162 Reserved
+} OPREGION_MBOX3;
+#pragma pack ()
+
+//
+// OpRegion mailbox 4 (VBT).
+//
+#pragma pack (1)
+typedef struct {
+ UINT8 GVD1[0x1800]; // 6K Reserved
+} OPREGION_VBT;
+#pragma pack ()
+
+#pragma pack (1)
+typedef struct {
+ UINT8 EDIDOVRD[0x400]; // 6K Edid overriding data
+} OPREGION_MBOX5;
+#pragma pack ()
+//
+// Entire OpRegion
+//
+#pragma pack (1)
+typedef struct {
+ OPREGION_HEADER Header; // OpRegion header
+ OPREGION_MBOX1 MBox1; // Mailbox 1: Public ACPI Methods
+ OPREGION_MBOX2 MBox2; // Mailbox 2: Software SCI Inteface
+ OPREGION_MBOX3 MBox3; // Mailbox 3: Power Conservation
+ OPREGION_VBT VBT; // VBT: Video BIOS Table (OEM customizable data)
+ OPREGION_MBOX5 MBox5;
+} IGD_OPREGION_STRUC;
+#pragma pack ()
+
+//
+// Protocol data structure definition
+//
+struct _IGD_OPREGION_PROTOCOL {
+ IGD_OPREGION_STRUC *OpRegion;
+};
+
+#endif
diff --git a/ChvRefCodePkg/CherryViewSoc/NorthCluster/Include/Protocol/MemInfo.h b/ChvRefCodePkg/CherryViewSoc/NorthCluster/Include/Protocol/MemInfo.h new file mode 100644 index 0000000000..af116bb1f3 --- /dev/null +++ b/ChvRefCodePkg/CherryViewSoc/NorthCluster/Include/Protocol/MemInfo.h @@ -0,0 +1,75 @@ +/** @file
+ This protocol provides the memory information data, such as
+ total physical memory size, memory frequency, memory size
+ of each dimm and rank.
+
+ This protocol is EFI compatible.
+
+ Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _MEM_INFO_PROTOCOL_H_
+#define _MEM_INFO_PROTOCOL_H_
+
+//
+// Extern the GUID for protocol users.
+//
+extern EFI_GUID gMemInfoProtocolGuid;
+
+//
+// Forward reference for ANSI C compatibility
+//
+typedef struct _MEM_INFO_PROTOCOL MEM_INFO_PROTOCOL;
+
+//
+// Protocol definitions
+//
+
+#define CH_NUM 2
+#define DIMM_NUM 1
+#define RANK_NUM 2
+
+#pragma pack(1)
+typedef struct {
+ UINT32 memSize;
+ UINT16 ddrFreq;
+ UINT8 ddrType;
+ BOOLEAN EccSupport;
+ UINT16 dimmSize[CH_NUM * DIMM_NUM];
+ UINT8 DimmPresent[CH_NUM * DIMM_NUM];
+ UINT8 *DimmsSpdData[CH_NUM * DIMM_NUM];
+ UINT8 reserved;
+ UINT16 reserved2;
+ UINT8 BusWidth;
+} MEMORY_INFO_DATA;
+#pragma pack()
+
+/**
+ Data definition:
+
+ memSize Total physical memory size
+ ddrFreq DDR Frequency
+ EccSupport ECC Support
+ dimmSize Dimm Size
+ DimmExist Dimm Present or not
+ RankInDimm No. of ranks in a dimm
+
+**/
+
+//
+// Protocol definition
+//
+struct _MEM_INFO_PROTOCOL {
+ MEMORY_INFO_DATA MemInfoData;
+};
+
+#endif
diff --git a/ChvRefCodePkg/CherryViewSoc/NorthCluster/Include/Protocol/PlatformGopPolicy.h b/ChvRefCodePkg/CherryViewSoc/NorthCluster/Include/Protocol/PlatformGopPolicy.h new file mode 100644 index 0000000000..88392155ab --- /dev/null +++ b/ChvRefCodePkg/CherryViewSoc/NorthCluster/Include/Protocol/PlatformGopPolicy.h @@ -0,0 +1,76 @@ +/** @file
+ The GOP Policy of Platform.
+
+ Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _PLATFORM_GOP_POLICY_PROTOCOL_H_
+#define _PLATFORM_GOP_POLICY_PROTOCOL_H_
+
+#define EFI_PLATFORM_GOP_POLICY_PROTOCOL_GUID \
+ { 0xec2e931b, 0x3281, 0x48a5, 0x81, 0x7, 0xdf, 0x8a, 0x8b, 0xed, 0x3c, 0x5d }
+
+#define EFI_BMP_IMAGE_GUID \
+ { 0x878AC2CC, 0x5343, 0x46F2, 0xB5, 0x63, 0x51, 0xF8, 0x9D, 0xAF, 0x56, 0xBA }
+
+#define PLATFORM_GOP_POLICY_PROTOCOL_REVISION_01 0x01
+#define PLATFORM_GOP_POLICY_PROTOCOL_REVISION_02 x0222
+
+#pragma pack(1)
+
+typedef enum {
+ LidClosed,
+ LidOpen,
+ LidStatusMax
+} LID_STATUS;
+
+typedef enum {
+ Docked,
+ UnDocked,
+ DockStatusMax
+} DOCK_STATUS;
+
+typedef
+EFI_STATUS
+(EFIAPI *GET_PLATFORM_LID_STATUS) (
+ OUT LID_STATUS *CurrentLidStatus
+);
+
+typedef
+EFI_STATUS
+(EFIAPI *GET_VBT_DATA) (
+ OUT EFI_PHYSICAL_ADDRESS *VbtAddress,
+ OUT UINT32 *VbtSize
+);
+
+#pragma pack()
+
+typedef struct _PLATFORM_GOP_POLICY_PROTOCOL {
+ UINT32 Revision;
+ GET_PLATFORM_LID_STATUS GetPlatformLidStatus;
+ GET_VBT_DATA GetVbtData;
+} PLATFORM_GOP_POLICY_PROTOCOL;
+
+//
+// Extern the GUID for protocol users.
+//
+extern EFI_GUID gPlatformGOPPolicyGuid;
+extern EFI_GUID gBmpImageGuid;
+extern EFI_GUID gMipiPanelVbtGuid;
+extern EFI_GUID gLgPanelVbtGuid;
+extern EFI_GUID gInnoluxPanelVbtGuid;
+extern EFI_GUID gHdmiDpVbtGuid;
+extern EFI_GUID gCopopLgPanelVbtGuid;
+extern EFI_GUID gFfdLgPanelVbtGuid;
+extern EFI_GUID gCrLgPanelVbtGuid;
+extern EFI_GUID gHrFfdLgPanelVbtGuid;
+#endif
|