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authoroliviermartin <oliviermartin@6f19259b-4bc3-4df7-8a09-765794883524>2011-11-01 23:45:41 +0000
committeroliviermartin <oliviermartin@6f19259b-4bc3-4df7-8a09-765794883524>2011-11-01 23:45:41 +0000
commit710b8acb569a0dc86e509d8cb6341504eeb0bbbf (patch)
tree5aa890d64bb9caf75050904d70eb74f2f1127792
parentaa26b8f6c86af5c179ef63ed5e0f0d31d4dbb39c (diff)
downloadedk2-platforms-710b8acb569a0dc86e509d8cb6341504eeb0bbbf.tar.xz
ArmPlatform/Sec: Ensure all the CPU cores are calling ArmCpuSetup()
Only the primary core was calling this function. git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@12646 6f19259b-4bc3-4df7-8a09-765794883524
-rw-r--r--ArmPlatformPkg/Sec/Sec.c23
1 files changed, 12 insertions, 11 deletions
diff --git a/ArmPlatformPkg/Sec/Sec.c b/ArmPlatformPkg/Sec/Sec.c
index d9831a5c44..f6b89648f9 100644
--- a/ArmPlatformPkg/Sec/Sec.c
+++ b/ArmPlatformPkg/Sec/Sec.c
@@ -35,10 +35,20 @@ CEntryPoint (
UINTN CharCount;
UINTN JumpAddress;
+ // Invalidate the data cache. Doesn't have to do the Data cache clean.
+ ArmInvalidateDataCache();
+
+ // Invalidate Instruction Cache
+ ArmInvalidateInstructionCache();
+
+ // Invalidate I & D TLBs
+ ArmInvalidateInstructionAndDataTlb();
+
+ // CPU specific settings
+ ArmCpuSetup (MpId);
+
// Primary CPU clears out the SCU tag RAMs, secondaries wait
if (IS_PRIMARY_CORE(MpId)) {
- ArmCpuSetup (MpId);
-
if (ArmIsMpCore()) {
ArmCpuSynchronizeSignal (ARM_CPU_EVENT_BOOT_MEM_INIT);
}
@@ -69,15 +79,6 @@ CEntryPoint (
ArmGicEnableInterruptInterface (PcdGet32(PcdGicInterruptInterfaceBase));
}
- // Invalidate the data cache. Doesn't have to do the Data cache clean.
- ArmInvalidateDataCache();
-
- // Invalidate Instruction Cache
- ArmInvalidateInstructionCache();
-
- // Invalidate I & D TLBs
- ArmInvalidateInstructionAndDataTlb();
-
// Enable Full Access to CoProcessors
ArmWriteCPACR (CPACR_CP_FULL_ACCESS);