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| author | Ruiyu Ni <ruiyu.ni@intel.com> | 2016-08-23 10:38:02 +0800 |
|---|---|---|
| committer | Ruiyu Ni <ruiyu.ni@intel.com> | 2017-03-31 13:57:30 +0800 |
| commit | 78c4992529c3954417068ee165a072c096d0b186 (patch) | |
| tree | 99067c83f2997c6758d74dad41a091e6ee3975f8 | |
| parent | 341fea6438482458f23d41c27cf710e0096ebb96 (diff) | |
| download | edk2-platforms-78c4992529c3954417068ee165a072c096d0b186.tar.xz | |
UefiCpuPkg/MtrrLib: Add CacheInvalid enum type to MtrrLib.h
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
| -rw-r--r-- | UefiCpuPkg/Include/Library/MtrrLib.h | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/UefiCpuPkg/Include/Library/MtrrLib.h b/UefiCpuPkg/Include/Library/MtrrLib.h index c37e776d9a..a63da4d1f5 100644 --- a/UefiCpuPkg/Include/Library/MtrrLib.h +++ b/UefiCpuPkg/Include/Library/MtrrLib.h @@ -119,7 +119,8 @@ typedef enum { CacheWriteCombining = 1,
CacheWriteThrough = 4,
CacheWriteProtected = 5,
- CacheWriteBack = 6
+ CacheWriteBack = 6,
+ CacheInvalid = 7
} MTRR_MEMORY_CACHE_TYPE;
#define MTRR_CACHE_UNCACHEABLE 0
|