ArmPkg/ArmLib: Removed duplicated invalidate TLB function

ArmInvalidateInstructionAndDataTlb() was doing the same thing as
ArmInvalidateTlb().
Both invalidate Data and Instruction TLBs.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16253 6f19259b-4bc3-4df7-8a09-765794883524

6 files changed, 4 insertions, 37 deletions

diff --git a/ArmPkg/Include/Library/ArmLib.h b/ArmPkg/Include/Library/ArmLib.h
index 0bb0d4a063..526b06a5ca 100644
--- a/ArmPkg/Include/Library/ArmLib.h
+++ b/ArmPkg/Include/Library/ArmLib.h
@@ -338,12 +338,6 @@ ArmDisableCachesAndMmu (
 

 VOID

 EFIAPI

-ArmInvalidateInstructionAndDataTlb (

-  VOID

-  );

-

-VOID

-EFIAPI

 ArmEnableInterrupts (

   VOID

   );

@@ -402,6 +396,9 @@ ArmGetFiqState (
   VOID

   );

 

+/**

+ * Invalidate Data and Instruction TLBs

+ */

 VOID

 EFIAPI

 ArmInvalidateTlb (

diff --git a/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S b/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S
index 76007505f3..98eba3cac2 100644
--- a/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S
+++ b/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S
@@ -48,7 +48,6 @@ GCC_ASM_EXPORT (ArmWriteVBar)
 GCC_ASM_EXPORT (ArmReadVBar)

 GCC_ASM_EXPORT (ArmEnableVFP)

 GCC_ASM_EXPORT (ArmCallWFI)

-GCC_ASM_EXPORT (ArmInvalidateInstructionAndDataTlb)

 GCC_ASM_EXPORT (ArmReadMpidr)

 GCC_ASM_EXPORT (ArmReadTpidrurw)

 GCC_ASM_EXPORT (ArmWriteTpidrurw)

@@ -450,18 +449,6 @@ ASM_PFX(ArmCallWFI):
   ret

 

 

-ASM_PFX(ArmInvalidateInstructionAndDataTlb):

-   EL1_OR_EL2_OR_EL3(x0)

-1: tlbi  vmalle1

-   b     4f

-2: tlbi  alle2

-   b     4f

-3: tlbi  alle3

-4: dsb   sy

-   isb

-   ret

-

-

 ASM_PFX(ArmReadMpidr):

   mrs   x0, mpidr_el1           // read EL1 MPIDR

   ret

diff --git a/ArmPkg/Library/ArmLib/Arm11/Arm11Support.S b/ArmPkg/Library/ArmLib/Arm11/Arm11Support.S
index 60e92fdc6a..25612f35ec 100644
--- a/ArmPkg/Library/ArmLib/Arm11/Arm11Support.S
+++ b/ArmPkg/Library/ArmLib/Arm11/Arm11Support.S
@@ -18,7 +18,6 @@
 .text

 .align 2

 GCC_ASM_EXPORT(ArmDisableCachesAndMmu)

-GCC_ASM_EXPORT(ArmInvalidateInstructionAndDataTlb)

 GCC_ASM_EXPORT(ArmCleanInvalidateDataCache)

 GCC_ASM_EXPORT(ArmCleanDataCache)

 GCC_ASM_EXPORT(ArmInvalidateDataCache)

@@ -68,10 +67,6 @@ ASM_PFX(ArmDisableCachesAndMmu):
   mcr   p15, 0, r0, c1, c0, 0           @ Write control register

   bx      LR

 

-ASM_PFX(ArmInvalidateInstructionAndDataTlb):

-  mcr     p15, 0, r0, c8, c7, 0      @ Invalidate Inst TLB and Data TLB

-  bx lr

-

 ASM_PFX(ArmInvalidateDataCacheEntryByMVA):

   mcr     p15, 0, r0, c7, c6, 1   @invalidate single data cache line

   bx      lr

diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S
index c31d49bcfb..af5ec23a1a 100644
--- a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S
+++ b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S
@@ -47,7 +47,6 @@ GCC_ASM_EXPORT (ArmWriteVBar)
 GCC_ASM_EXPORT (ArmEnableVFP)

 GCC_ASM_EXPORT (ArmCallWFI)

 GCC_ASM_EXPORT (ArmReadCbar)

-GCC_ASM_EXPORT (ArmInvalidateInstructionAndDataTlb)

 GCC_ASM_EXPORT (ArmReadMpidr)

 GCC_ASM_EXPORT (ArmReadTpidrurw)

 GCC_ASM_EXPORT (ArmWriteTpidrurw)

@@ -368,11 +367,6 @@ ASM_PFX(ArmReadCbar):
   mrc     p15, 4, r0, c15, c0, 0  @ Read Configuration Base Address Register

   bx      lr

 

-ASM_PFX(ArmInvalidateInstructionAndDataTlb):

-  mcr     p15, 0, r0, c8, c7, 0      @ Invalidate Inst TLB and Data TLB

-  dsb

-  bx lr

-

 ASM_PFX(ArmReadMpidr):

   mrc     p15, 0, r0, c0, c0, 5       @ read MPIDR

   bx      lr

diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm
index 368138933a..2b13811dc6 100644
--- a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm
+++ b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm
@@ -44,7 +44,6 @@
     EXPORT  ArmEnableVFP

     EXPORT  ArmCallWFI

     EXPORT  ArmReadCbar

-    EXPORT  ArmInvalidateInstructionAndDataTlb

     EXPORT  ArmReadMpidr

     EXPORT  ArmReadTpidrurw

     EXPORT  ArmWriteTpidrurw

@@ -362,11 +361,6 @@ ArmReadCbar
   mrc     p15, 4, r0, c15, c0, 0  //Read Configuration Base Address Register

   bx      lr

 

-ArmInvalidateInstructionAndDataTlb

-  mcr     p15, 0, r0, c8, c7, 0      ; Invalidate Inst TLB and Data TLB

-  dsb

-  bx lr

-

 ArmReadMpidr

   mrc     p15, 0, r0, c0, c0, 5     ; read MPIDR

   bx      lr

diff --git a/ArmPlatformPkg/Sec/Sec.c b/ArmPlatformPkg/Sec/Sec.c
index 015c1613c6..15584f1901 100644
--- a/ArmPlatformPkg/Sec/Sec.c
+++ b/ArmPlatformPkg/Sec/Sec.c
@@ -42,7 +42,7 @@ CEntryPoint (
   ArmInvalidateInstructionCache ();

 

   // Invalidate I & D TLBs

-  ArmInvalidateInstructionAndDataTlb ();

+  ArmInvalidateTlb ();

 

   // CPU specific settings

   ArmCpuSetup (MpId);