diff options
| author | Guo Dong <guo.dong@intel.com> | 2015-06-03 04:55:58 +0000 |
|---|---|---|
| committer | gdong1 <gdong1@Edk2> | 2015-06-03 04:55:58 +0000 |
| commit | baae777b8e6370ab856ec9088864ab698f5e9b0f (patch) | |
| tree | 126574940d8b0fdca0c6ff6fa43685115e23e4e3 | |
| parent | 51492422806c7d9cc932e8d27f1e32bab7ac7cf0 (diff) | |
| download | edk2-platforms-baae777b8e6370ab856ec9088864ab698f5e9b0f.tar.xz | |
IntelFspPkg: correct comments and rename a label
Corrects a word typo and a comment error.
Rename a label to match its function name.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Guo Dong <guo.dong@intel.com>
Reviewed-by: Yao Jiewen <Jiewen.Yao@intel.com>
Reviewed-by: Haojian Zhuang <haojian.zhuang@linaro.org>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17553 6f19259b-4bc3-4df7-8a09-765794883524
| -rw-r--r-- | IntelFspPkg/FspSecCore/Ia32/FspApiEntry.asm | 10 | ||||
| -rw-r--r-- | IntelFspPkg/FspSecCore/SecMain.c | 2 | ||||
| -rw-r--r-- | IntelFspPkg/Library/BaseCacheLib/CacheLib.c | 2 |
3 files changed, 7 insertions, 7 deletions
diff --git a/IntelFspPkg/FspSecCore/Ia32/FspApiEntry.asm b/IntelFspPkg/FspSecCore/Ia32/FspApiEntry.asm index d0e56b2360..71e3e5a1e2 100644 --- a/IntelFspPkg/FspSecCore/Ia32/FspApiEntry.asm +++ b/IntelFspPkg/FspSecCore/Ia32/FspApiEntry.asm @@ -368,15 +368,15 @@ TempRamInitApi PROC NEAR PUBLIC mov eax, dword ptr [esp + 4]
cmp eax, 0
mov eax, 80000002h
- jz NemInitExit
+ jz TempRamInitExit
;
; Sec Platform Init
;
CALL_MMX SecPlatformInit
cmp eax, 0
- jnz NemInitExit
-
+ jnz TempRamInitExit
+
; Load microcode
LOAD_ESP
CALL_MMX LoadMicrocode
@@ -387,14 +387,14 @@ TempRamInitApi PROC NEAR PUBLIC LOAD_ESP
CALL_MMX SecCarInit
cmp eax, 0
- jnz NemInitExit
+ jnz TempRamInitExit
LOAD_ESP
CALL_MMX EstablishStackFsp
LXMMN xmm6, eax, 3 ;Restore microcode status if no CAR init error from ECX-SLOT 3 in xmm6.
-NemInitExit:
+TempRamInitExit:
;
; Load EBP, EBX, ESI, EDI & ESP from XMM7 & XMM6
;
diff --git a/IntelFspPkg/FspSecCore/SecMain.c b/IntelFspPkg/FspSecCore/SecMain.c index 63376e9b6e..99acefaefa 100644 --- a/IntelFspPkg/FspSecCore/SecMain.c +++ b/IntelFspPkg/FspSecCore/SecMain.c @@ -104,7 +104,7 @@ SecStartup ( AsmWriteIdtr (&IdtDescriptor);
//
- // Iniitalize the global FSP data region
+ // Initialize the global FSP data region
//
FspGlobalDataInit (&PeiFspData, BootLoaderStack, (UINT8)ApiIdx);
diff --git a/IntelFspPkg/Library/BaseCacheLib/CacheLib.c b/IntelFspPkg/Library/BaseCacheLib/CacheLib.c index 1a08918597..b38dce32a8 100644 --- a/IntelFspPkg/Library/BaseCacheLib/CacheLib.c +++ b/IntelFspPkg/Library/BaseCacheLib/CacheLib.c @@ -45,7 +45,7 @@ SearchForExactMtrr ( @param[in] MemoryCacheType input cache type to be checked.
@retval TRUE MemoryCacheType is default MTRR setting.
- @retval TRUE MemoryCacheType is NOT default MTRR setting.
+ @retval FALSE MemoryCacheType is NOT default MTRR setting.
**/
BOOLEAN
IsDefaultType (
|