diff options
| author | oliviermartin <oliviermartin@6f19259b-4bc3-4df7-8a09-765794883524> | 2011-07-01 16:33:22 +0000 |
|---|---|---|
| committer | oliviermartin <oliviermartin@6f19259b-4bc3-4df7-8a09-765794883524> | 2011-07-01 16:33:22 +0000 |
| commit | c52e2dca64d90140130444fb647590763b4594ad (patch) | |
| tree | 79bab40fea57b46ec956d6a2344da52b3937b0e2 | |
| parent | 3c4b742c182785b0e3ae0217a8e3a08b47b5c7a8 (diff) | |
| download | edk2-platforms-c52e2dca64d90140130444fb647590763b4594ad.tar.xz | |
ArmPlatformPkg/PL35xSmc: Clean SMC driver to replace hardcoded Chip Select into the driver itself by passing SMC configuration to the driver
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@11959 6f19259b-4bc3-4df7-8a09-765794883524
14 files changed, 419 insertions, 466 deletions
diff --git a/ArmPlatformPkg/ArmRealViewEbPkg/Library/ArmRealViewEbLibRTSM/ArmRealViewEbBoot.S b/ArmPlatformPkg/ArmRealViewEbPkg/Library/ArmRealViewEbLibRTSM/ArmRealViewEbBoot.S new file mode 100755 index 0000000000..037efd9c20 --- /dev/null +++ b/ArmPlatformPkg/ArmRealViewEbPkg/Library/ArmRealViewEbLibRTSM/ArmRealViewEbBoot.S @@ -0,0 +1,37 @@ +//
+// Copyright (c) 2011, ARM Limited. All rights reserved.
+//
+// This program and the accompanying materials
+// are licensed and made available under the terms and conditions of the BSD License
+// which accompanies this distribution. The full text of the license may be found at
+// http://opensource.org/licenses/bsd-license.php
+//
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+//
+
+#include <AsmMacroIoLib.h>
+#include <Base.h>
+#include <Library/ArmPlatformLib.h>
+#include <ArmPlatform.h>
+#include <AutoGen.h>
+
+.text
+.align 3
+
+GCC_ASM_EXPORT(ArmPlatformInitializeBootMemory)
+
+/**
+ Initialize the memory where the initial stacks will reside
+
+ This memory can contain the initial stacks (Secure and Secure Monitor stacks).
+ In some platform, this region is already initialized and the implementation of this function can
+ do nothing. This memory can also represent the Secure RAM.
+ This function is called before the satck has been set up. Its implementation must ensure the stack
+ pointer is not used (probably required to use assembly language)
+
+**/
+ASM_PFX(ArmPlatformInitializeBootMemory):
+ // The SMC does not need to be initialized for RTSM
+ bx lr
diff --git a/ArmPlatformPkg/ArmRealViewEbPkg/Library/ArmRealViewEbLibRTSM/ArmRealViewEbBoot.asm b/ArmPlatformPkg/ArmRealViewEbPkg/Library/ArmRealViewEbLibRTSM/ArmRealViewEbBoot.asm new file mode 100755 index 0000000000..272a05a8fa --- /dev/null +++ b/ArmPlatformPkg/ArmRealViewEbPkg/Library/ArmRealViewEbLibRTSM/ArmRealViewEbBoot.asm @@ -0,0 +1,39 @@ +//
+// Copyright (c) 2011, ARM Limited. All rights reserved.
+//
+// This program and the accompanying materials
+// are licensed and made available under the terms and conditions of the BSD License
+// which accompanies this distribution. The full text of the license may be found at
+// http://opensource.org/licenses/bsd-license.php
+//
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+//
+
+#include <AsmMacroIoLib.h>
+#include <Base.h>
+#include <Library/ArmPlatformLib.h>
+#include <ArmPlatform.h>
+#include <AutoGen.h>
+
+ INCLUDE AsmMacroIoLib.inc
+
+ EXPORT ArmPlatformInitializeBootMemory
+
+ PRESERVE8
+ AREA CTA9x4BootMode, CODE, READONLY
+
+/**
+ Initialize the memory where the initial stacks will reside
+
+ This memory can contain the initial stacks (Secure and Secure Monitor stacks).
+ In some platform, this region is already initialized and the implementation of this function can
+ do nothing. This memory can also represent the Secure RAM.
+ This function is called before the satck has been set up. Its implementation must ensure the stack
+ pointer is not used (probably required to use assembly language)
+
+**/
+ArmPlatformInitializeBootMemory
+ // The SMC does not need to be initialized for RTSM
+ bx lr
diff --git a/ArmPlatformPkg/ArmRealViewEbPkg/Library/ArmRealViewEbLibRTSM/ArmRealViewEbHelper.S b/ArmPlatformPkg/ArmRealViewEbPkg/Library/ArmRealViewEbLibRTSM/ArmRealViewEbHelper.S index ca18aa88dd..3bbdf6f52d 100644 --- a/ArmPlatformPkg/ArmRealViewEbPkg/Library/ArmRealViewEbLibRTSM/ArmRealViewEbHelper.S +++ b/ArmPlatformPkg/ArmRealViewEbPkg/Library/ArmRealViewEbLibRTSM/ArmRealViewEbHelper.S @@ -14,14 +14,13 @@ #include <AsmMacroIoLib.h>
#include <Base.h>
#include <Library/PcdLib.h>
+#include <Library/ArmPlatformLib.h>
#include <ArmPlatform.h>
#include <AutoGen.h>
-#Start of Code section
.text
.align 3
-GCC_ASM_EXPORT(ArmPlatformIsMemoryInitialized)
GCC_ASM_EXPORT(ArmPlatformInitializeBootMemory)
/**
@@ -45,18 +44,4 @@ ASM_PFX(ArmPlatformIsMemoryInitialized): tst r0, #0x200
bx lr
-/**
- Initialize the memory where the initial stacks will reside
-
- This memory can contain the initial stacks (Secure and Secure Monitor stacks).
- In some platform, this region is already initialized and the implementation of this function can
- do nothing. This memory can also represent the Secure RAM.
- This function is called before the satck has been set up. Its implementation must ensure the stack
- pointer is not used (probably required to use assembly language)
-
-**/
-ASM_PFX(ArmPlatformInitializeBootMemory):
- // The SMC does not need to be initialized for RTSM
- bx lr
-
ASM_FUNCTION_REMOVE_IF_UNREFERENCED
\ No newline at end of file diff --git a/ArmPlatformPkg/ArmRealViewEbPkg/Library/ArmRealViewEbLibRTSM/ArmRealViewEbHelper.asm b/ArmPlatformPkg/ArmRealViewEbPkg/Library/ArmRealViewEbLibRTSM/ArmRealViewEbHelper.asm index c0b4263a35..b72fc6f37e 100644 --- a/ArmPlatformPkg/ArmRealViewEbPkg/Library/ArmRealViewEbLibRTSM/ArmRealViewEbHelper.asm +++ b/ArmPlatformPkg/ArmRealViewEbPkg/Library/ArmRealViewEbLibRTSM/ArmRealViewEbHelper.asm @@ -1,26 +1,26 @@ //
// Copyright (c) 2011, ARM Limited. All rights reserved.
-//
-// This program and the accompanying materials
-// are licensed and made available under the terms and conditions of the BSD License
-// which accompanies this distribution. The full text of the license may be found at
-// http://opensource.org/licenses/bsd-license.php
//
-// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+// This program and the accompanying materials
+// are licensed and made available under the terms and conditions of the BSD License
+// which accompanies this distribution. The full text of the license may be found at
+// http://opensource.org/licenses/bsd-license.php
+//
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
//
//
#include <AsmMacroIoLib.h>
#include <Base.h>
#include <Library/PcdLib.h>
+#include <Library/ArmPlatformLib.h>
#include <ArmPlatform.h>
#include <AutoGen.h>
INCLUDE AsmMacroIoLib.inc
EXPORT ArmPlatformIsMemoryInitialized
- EXPORT ArmPlatformInitializeBootMemory
PRESERVE8
AREA ArmRealViewEbHelper, CODE, READONLY
@@ -45,19 +45,4 @@ ArmPlatformIsMemoryInitialized and r0, r0, #0x200
tst r0, #0x200
bx lr
-
-/**
- Initialize the memory where the initial stacks will reside
-
- This memory can contain the initial stacks (Secure and Secure Monitor stacks).
- In some platform, this region is already initialized and the implementation of this function can
- do nothing. This memory can also represent the Secure RAM.
- This function is called before the satck has been set up. Its implementation must ensure the stack
- pointer is not used (probably required to use assembly language)
-
-**/
-ArmPlatformInitializeBootMemory
- // The SMC does not need to be initialized for RTSM
- bx lr
-
END
diff --git a/ArmPlatformPkg/ArmRealViewEbPkg/Library/ArmRealViewEbLibRTSM/ArmRealViewEbSecLib.inf b/ArmPlatformPkg/ArmRealViewEbPkg/Library/ArmRealViewEbLibRTSM/ArmRealViewEbSecLib.inf index dc4d560b14..d4a603718b 100644 --- a/ArmPlatformPkg/ArmRealViewEbPkg/Library/ArmRealViewEbLibRTSM/ArmRealViewEbSecLib.inf +++ b/ArmPlatformPkg/ArmRealViewEbPkg/Library/ArmRealViewEbLibRTSM/ArmRealViewEbSecLib.inf @@ -34,6 +34,8 @@ ArmRealViewEb.c
ArmRealViewEbHelper.asm | RVCT
ArmRealViewEbHelper.S | GCC
+ ArmRealViewEbBoot.asm | RVCT
+ ArmRealViewEbBoot.S | GCC
[Protocols]
diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/ArmVExpressLib.inf b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/ArmVExpressLib.inf index 5670fab7c4..f160622d78 100644 --- a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/ArmVExpressLib.inf +++ b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/ArmVExpressLib.inf @@ -31,7 +31,6 @@ ArmLib ArmTrustZoneLib MemoryAllocationLib - PL354SmcLib PL341DmcLib PL301AxiLib L2X0CacheLib @@ -40,6 +39,8 @@ [Sources.common] CTA9x4.c CTA9x4Mem.c + CTA9x4Helper.asm | RVCT + CTA9x4Helper.S | GCC [Protocols] diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/ArmVExpressSecLib.inf b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/ArmVExpressSecLib.inf index 0a1054a28b..3f08784ff5 100644 --- a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/ArmVExpressSecLib.inf +++ b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/ArmVExpressSecLib.inf @@ -34,7 +34,7 @@ L2X0CacheLib
PL301AxiLib
PL341DmcLib
- PL354SmcLib
+ PL35xSmcLib
SerialPortLib
[Sources.common]
@@ -42,6 +42,8 @@ CTA9x4.c
CTA9x4Helper.asm | RVCT
CTA9x4Helper.S | GCC
+ CTA9x4Boot.asm | RVCT
+ CTA9x4Boot.S | GCC
[Protocols]
diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/CTA9x4Boot.S b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/CTA9x4Boot.S new file mode 100755 index 0000000000..c53c11f370 --- /dev/null +++ b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/CTA9x4Boot.S @@ -0,0 +1,110 @@ +//
+// Copyright (c) 2011, ARM Limited. All rights reserved.
+//
+// This program and the accompanying materials
+// are licensed and made available under the terms and conditions of the BSD License
+// which accompanies this distribution. The full text of the license may be found at
+// http://opensource.org/licenses/bsd-license.php
+//
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+//
+
+#include <AsmMacroIoLib.h>
+#include <Base.h>
+#include <Library/ArmPlatformLib.h>
+#include <Drivers/PL35xSmc.h>
+#include <ArmPlatform.h>
+#include <AutoGen.h>
+
+.text
+.align 3
+
+GCC_ASM_EXPORT(ArmPlatformInitializeBootMemory)
+GCC_ASM_IMPORT(PL35xSmcInitialize)
+
+//
+// For each Chip Select: ChipSelect / SetCycle / SetOpMode
+//
+VersatileExpressSmcConfiguration:
+ // NOR Flash 0
+ .word PL350_SMC_DIRECT_CMD_ADDR_CS(0)
+ .word PL350_SMC_SET_CYCLE_NAND_T_RC(0xA) :OR: PL350_SMC_SET_CYCLE_NAND_T_WC(0x3) :OR: PL350_SMC_SET_CYCLE_NAND_T_REA(0x1) :OR: PL350_SMC_SET_CYCLE_NAND_T_WP(0x7) :OR: PL350_SMC_SET_CYCLE_NAND_T_AR(0x1)
+ .word PL350_SMC_SET_OPMODE_MEM_WIDTH_32 :OR: PL350_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_CONT :OR: PL350_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_CONT :OR: PL350_SMC_SET_OPMODE_SET_ADV
+
+ // NOR Flash 1
+ .word PL350_SMC_DIRECT_CMD_ADDR_CS(4)
+ .word PL350_SMC_SET_CYCLE_NAND_T_RC(0xA) :OR: PL350_SMC_SET_CYCLE_NAND_T_WC(0x3) :OR: PL350_SMC_SET_CYCLE_NAND_T_REA(0x1) :OR: PL350_SMC_SET_CYCLE_NAND_T_WP(0x7) :OR: PL350_SMC_SET_CYCLE_NAND_T_AR(0x1)
+ .word PL350_SMC_SET_OPMODE_MEM_WIDTH_32 :OR: PL350_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_CONT :OR: PL350_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_CONT :OR: PL350_SMC_SET_OPMODE_SET_ADV
+
+ // SRAM
+ .word PL350_SMC_DIRECT_CMD_ADDR_CS(2)
+ .word PL350_SMC_SET_CYCLE_SRAM_T_RC(0x8) :OR: PL350_SMC_SET_CYCLE_SRAM_T_WC(0x5) :OR: PL350_SMC_SET_CYCLE_SRAM_T_CEOE(0x1) :OR: PL350_SMC_SET_CYCLE_SRAM_T_WP(0x6) :OR: PL350_SMC_SET_CYCLE_SRAM_T_PC(0x1) :OR: PL350_SMC_SET_CYCLE_SRAM_T_TR(0x1)
+ .word PL350_SMC_SET_OPMODE_MEM_WIDTH_32 :OR: PL350_SMC_SET_OPMODE_SET_ADV
+
+ // Usb/Eth/VRAM
+ .word PL350_SMC_DIRECT_CMD_ADDR_CS(3)
+ .word PL350_SMC_SET_CYCLE_SRAM_T_RC(0xA) :OR: PL350_SMC_SET_CYCLE_SRAM_T_WC(0xA) :OR: PL350_SMC_SET_CYCLE_SRAM_T_CEOE(0x2) :OR: PL350_SMC_SET_CYCLE_SRAM_T_WP(0x2) :OR: PL350_SMC_SET_CYCLE_SRAM_T_PC(0x3) :OR: PL350_SMC_SET_CYCLE_SRAM_T_TR(0x6)
+ .word PL350_SMC_SET_OPMODE_MEM_WIDTH_32 :OR: PL350_SMC_SET_OPMODE_SET_RD_SYNC :OR: PL350_SMC_SET_OPMODE_SET_WR_SYNC
+
+ // Memory Mapped Peripherals
+ .word PL350_SMC_DIRECT_CMD_ADDR_CS(7)
+ .word PL350_SMC_SET_CYCLE_SRAM_T_RC(0x6) :OR: PL350_SMC_SET_CYCLE_SRAM_T_WC(0x5) :OR: PL350_SMC_SET_CYCLE_SRAM_T_CEOE(0x1) :OR: PL350_SMC_SET_CYCLE_SRAM_T_WP(0x2) :OR: PL350_SMC_SET_CYCLE_SRAM_T_PC(0x1) :OR: PL350_SMC_SET_CYCLE_SRAM_T_TR(0x1)
+ .word PL350_SMC_SET_OPMODE_MEM_WIDTH_32 :OR: PL350_SMC_SET_OPMODE_SET_RD_SYNC :OR: PL350_SMC_SET_OPMODE_SET_WR_SYNC
+
+ // VRAM
+ .word PL350_SMC_DIRECT_CMD_ADDR_CS(1)
+ .word 0x00049249
+ .word PL350_SMC_SET_OPMODE_MEM_WIDTH_32 :OR: PL350_SMC_SET_OPMODE_SET_RD_SYNC :OR: PL350_SMC_SET_OPMODE_SET_WR_SYNC
+VersatileExpressSmcConfigurationEnd:
+
+/**
+ Initialize the memory where the initial stacks will reside
+
+ This memory can contain the initial stacks (Secure and Secure Monitor stacks).
+ In some platform, this region is already initialized and the implementation of this function can
+ do nothing. This memory can also represent the Secure RAM.
+ This function is called before the satck has been set up. Its implementation must ensure the stack
+ pointer is not used (probably required to use assembly language)
+
+**/
+ASM_PFX(ArmPlatformInitializeBootMemory):
+ mov r5, lr
+
+ //
+ // Initialize PL354 SMC
+ //
+ LoadConstantToReg (ARM_VE_SMC_CTRL_BASE, r1)
+ ldr r2, =VersatileExpressSmcConfiguration
+ ldr r3, =VersatileExpressSmcConfigurationEnd
+ blx ASM_PFX(PL35xSmcInitialize)
+
+ //
+ // Page mode setup for VRAM
+ //
+ LoadConstantToReg (VRAM_MOTHERBOARD_BASE, r2)
+
+ // Read current state
+ ldr r0, [r2, #0]
+ ldr r0, [r2, #0]
+ ldr r0, = 0x00000000
+ str r0, [r2, #0]
+ ldr r0, [r2, #0]
+
+ // Enable page mode
+ ldr r0, [r2, #0]
+ ldr r0, [r2, #0]
+ ldr r0, = 0x00000000
+ str r0, [r2, #0]
+ ldr r0, = 0x00900090
+ str r0, [r2, #0]
+
+ // Confirm page mode enabled
+ ldr r0, [r2, #0]
+ ldr r0, [r2, #0]
+ ldr r0, = 0x00000000
+ str r0, [r2, #0]
+ ldr r0, [r2, #0]
+
+ bx r5
diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/CTA9x4Boot.asm b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/CTA9x4Boot.asm new file mode 100755 index 0000000000..5a08307e13 --- /dev/null +++ b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/CTA9x4Boot.asm @@ -0,0 +1,112 @@ +//
+// Copyright (c) 2011, ARM Limited. All rights reserved.
+//
+// This program and the accompanying materials
+// are licensed and made available under the terms and conditions of the BSD License
+// which accompanies this distribution. The full text of the license may be found at
+// http://opensource.org/licenses/bsd-license.php
+//
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+//
+
+#include <AsmMacroIoLib.h>
+#include <Base.h>
+#include <Library/ArmPlatformLib.h>
+#include <Drivers/PL35xSmc.h>
+#include <ArmPlatform.h>
+#include <AutoGen.h>
+
+ INCLUDE AsmMacroIoLib.inc
+
+ EXPORT ArmPlatformInitializeBootMemory
+ IMPORT PL35xSmcInitialize
+
+ PRESERVE8
+ AREA CTA9x4BootMode, CODE, READONLY
+
+//
+// For each Chip Select: ChipSelect / SetCycle / SetOpMode
+//
+VersatileExpressSmcConfiguration
+ // NOR Flash 0
+ DCD PL350_SMC_DIRECT_CMD_ADDR_CS(0)
+ DCD PL350_SMC_SET_CYCLE_NAND_T_RC(0xA) :OR: PL350_SMC_SET_CYCLE_NAND_T_WC(0x3) :OR: PL350_SMC_SET_CYCLE_NAND_T_REA(0x1) :OR: PL350_SMC_SET_CYCLE_NAND_T_WP(0x7) :OR: PL350_SMC_SET_CYCLE_NAND_T_AR(0x1)
+ DCD PL350_SMC_SET_OPMODE_MEM_WIDTH_32 :OR: PL350_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_CONT :OR: PL350_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_CONT :OR: PL350_SMC_SET_OPMODE_SET_ADV
+
+ // NOR Flash 1
+ DCD PL350_SMC_DIRECT_CMD_ADDR_CS(4)
+ DCD PL350_SMC_SET_CYCLE_NAND_T_RC(0xA) :OR: PL350_SMC_SET_CYCLE_NAND_T_WC(0x3) :OR: PL350_SMC_SET_CYCLE_NAND_T_REA(0x1) :OR: PL350_SMC_SET_CYCLE_NAND_T_WP(0x7) :OR: PL350_SMC_SET_CYCLE_NAND_T_AR(0x1)
+ DCD PL350_SMC_SET_OPMODE_MEM_WIDTH_32 :OR: PL350_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_CONT :OR: PL350_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_CONT :OR: PL350_SMC_SET_OPMODE_SET_ADV
+
+ // SRAM
+ DCD PL350_SMC_DIRECT_CMD_ADDR_CS(2)
+ DCD PL350_SMC_SET_CYCLE_SRAM_T_RC(0x8) :OR: PL350_SMC_SET_CYCLE_SRAM_T_WC(0x5) :OR: PL350_SMC_SET_CYCLE_SRAM_T_CEOE(0x1) :OR: PL350_SMC_SET_CYCLE_SRAM_T_WP(0x6) :OR: PL350_SMC_SET_CYCLE_SRAM_T_PC(0x1) :OR: PL350_SMC_SET_CYCLE_SRAM_T_TR(0x1)
+ DCD PL350_SMC_SET_OPMODE_MEM_WIDTH_32 :OR: PL350_SMC_SET_OPMODE_SET_ADV
+
+ // Usb/Eth/VRAM
+ DCD PL350_SMC_DIRECT_CMD_ADDR_CS(3)
+ DCD PL350_SMC_SET_CYCLE_SRAM_T_RC(0xA) :OR: PL350_SMC_SET_CYCLE_SRAM_T_WC(0xA) :OR: PL350_SMC_SET_CYCLE_SRAM_T_CEOE(0x2) :OR: PL350_SMC_SET_CYCLE_SRAM_T_WP(0x2) :OR: PL350_SMC_SET_CYCLE_SRAM_T_PC(0x3) :OR: PL350_SMC_SET_CYCLE_SRAM_T_TR(0x6)
+ DCD PL350_SMC_SET_OPMODE_MEM_WIDTH_32 :OR: PL350_SMC_SET_OPMODE_SET_RD_SYNC :OR: PL350_SMC_SET_OPMODE_SET_WR_SYNC
+
+ // Memory Mapped Peripherals
+ DCD PL350_SMC_DIRECT_CMD_ADDR_CS(7)
+ DCD PL350_SMC_SET_CYCLE_SRAM_T_RC(0x6) :OR: PL350_SMC_SET_CYCLE_SRAM_T_WC(0x5) :OR: PL350_SMC_SET_CYCLE_SRAM_T_CEOE(0x1) :OR: PL350_SMC_SET_CYCLE_SRAM_T_WP(0x2) :OR: PL350_SMC_SET_CYCLE_SRAM_T_PC(0x1) :OR: PL350_SMC_SET_CYCLE_SRAM_T_TR(0x1)
+ DCD PL350_SMC_SET_OPMODE_MEM_WIDTH_32 :OR: PL350_SMC_SET_OPMODE_SET_RD_SYNC :OR: PL350_SMC_SET_OPMODE_SET_WR_SYNC
+
+ // VRAM
+ DCD PL350_SMC_DIRECT_CMD_ADDR_CS(1)
+ DCD 0x00049249
+ DCD PL350_SMC_SET_OPMODE_MEM_WIDTH_32 :OR: PL350_SMC_SET_OPMODE_SET_RD_SYNC :OR: PL350_SMC_SET_OPMODE_SET_WR_SYNC
+VersatileExpressSmcConfigurationEnd
+
+/**
+ Initialize the memory where the initial stacks will reside
+
+ This memory can contain the initial stacks (Secure and Secure Monitor stacks).
+ In some platform, this region is already initialized and the implementation of this function can
+ do nothing. This memory can also represent the Secure RAM.
+ This function is called before the satck has been set up. Its implementation must ensure the stack
+ pointer is not used (probably required to use assembly language)
+
+**/
+ArmPlatformInitializeBootMemory
+ mov r5, lr
+
+ //
+ // Initialize PL354 SMC
+ //
+ LoadConstantToReg (ARM_VE_SMC_CTRL_BASE, r1)
+ ldr r2, =VersatileExpressSmcConfiguration
+ ldr r3, =VersatileExpressSmcConfigurationEnd
+ blx PL35xSmcInitialize
+
+ //
+ // Page mode setup for VRAM
+ //
+ LoadConstantToReg (VRAM_MOTHERBOARD_BASE, r2)
+
+ // Read current state
+ ldr r0, [r2, #0]
+ ldr r0, [r2, #0]
+ ldr r0, = 0x00000000
+ str r0, [r2, #0]
+ ldr r0, [r2, #0]
+
+ // Enable page mode
+ ldr r0, [r2, #0]
+ ldr r0, [r2, #0]
+ ldr r0, = 0x00000000
+ str r0, [r2, #0]
+ ldr r0, = 0x00900090
+ str r0, [r2, #0]
+
+ // Confirm page mode enabled
+ ldr r0, [r2, #0]
+ ldr r0, [r2, #0]
+ ldr r0, = 0x00000000
+ str r0, [r2, #0]
+ ldr r0, [r2, #0]
+
+ bx r5
diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/CTA9x4Helper.S b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/CTA9x4Helper.S index 2987cbee53..b66b051907 100644 --- a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/CTA9x4Helper.S +++ b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/CTA9x4Helper.S @@ -15,18 +15,13 @@ #include <Base.h>
#include <Library/PcdLib.h>
#include <Library/ArmPlatformLib.h>
-#include <Drivers/PL354Smc.h>
+#include <ArmPlatform.h>
#include <AutoGen.h>
.text
.align 3
GCC_ASM_EXPORT(ArmPlatformIsMemoryInitialized)
-GCC_ASM_EXPORT(ArmPlatformInitializeBootMemory)
-.extern ASM_PFX(SMCInitializeNOR)
-.extern ASM_PFX(SMCInitializeSRAM)
-.extern ASM_PFX(SMCInitializePeripherals)
-.extern ASM_PFX(SMCInitializeVRAM)
/**
Called at the early stage of the Boot phase to know if the memory has already been initialized
@@ -49,44 +44,3 @@ ASM_PFX(ArmPlatformIsMemoryInitialized): tst r0, #0x40000000
bx lr
-/**
- Initialize the memory where the initial stacks will reside
-
- This memory can contain the initial stacks (Secure and Secure Monitor stacks).
- In some platform, this region is already initialized and the implementation of this function can
- do nothing. This memory can also represent the Secure RAM.
- This function is called before the satck has been set up. Its implementation must ensure the stack
- pointer is not used (probably required to use assembly language)
-
-**/
-ASM_PFX(ArmPlatformInitializeBootMemory):
- mov r5, lr
-
- //
- // Initialize PL354 SMC
- //
- LoadConstantToReg (ARM_VE_SMC_CTRL_BASE, r1)
-
- // NOR Flash 0
- LoadConstantToReg (PL354_SMC_DIRECT_CMD_ADDR_CS(0,0), r2)
- blx ASM_PFX(SMCInitializeNOR)
-
- // NOR Flash 1
- LoadConstantToReg (PL354_SMC_DIRECT_CMD_ADDR_CS(1,0), r2)
- blx ASM_PFX(SMCInitializeNOR)
-
- // Setup SRAM
- blx ASM_PFX(SMCInitializeSRAM)
-
- // Memory Mapped Peripherals
- blx ASM_PFX(SMCInitializePeripherals)
-
- // Initialize VRAM
- //TODO: Check if we really must inititialize Video SRAM in UEFI. Does Linux can do it ? Does the Video driver can do it ?
- // It will be faster (only initialize if required) and easier (remove assembly code because of a stack available) to move this initialization.
- LoadConstantToReg (VRAM_MOTHERBOARD_BASE, r2)
- blx ASM_PFX(SMCInitializeVRAM)
-
- bx r5
-
-.end
diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/CTA9x4Helper.asm b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/CTA9x4Helper.asm index 3b353558e6..e81888c9fb 100644 --- a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/CTA9x4Helper.asm +++ b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/CTA9x4Helper.asm @@ -1,32 +1,27 @@ //
// Copyright (c) 2011, ARM Limited. All rights reserved.
-//
-// This program and the accompanying materials
-// are licensed and made available under the terms and conditions of the BSD License
-// which accompanies this distribution. The full text of the license may be found at
-// http://opensource.org/licenses/bsd-license.php
//
-// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+// This program and the accompanying materials
+// are licensed and made available under the terms and conditions of the BSD License
+// which accompanies this distribution. The full text of the license may be found at
+// http://opensource.org/licenses/bsd-license.php
+//
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
//
//
#include <AsmMacroIoLib.h>
#include <Base.h>
#include <Library/PcdLib.h>
+#include <Library/ArmPlatformLib.h>
#include <ArmPlatform.h>
-#include <Drivers/PL354Smc.h>
#include <AutoGen.h>
INCLUDE AsmMacroIoLib.inc
-
- EXPORT ArmPlatformIsMemoryInitialized
+
EXPORT ArmPlatformInitializeBootMemory
- IMPORT SMCInitializeNOR
- IMPORT SMCInitializeSRAM
- IMPORT SMCInitializePeripherals
- IMPORT SMCInitializeVRAM
-
+
PRESERVE8
AREA CTA9x4Helper, CODE, READONLY
@@ -51,44 +46,3 @@ ArmPlatformIsMemoryInitialized tst r0, #0x40000000
bx lr
-/**
- Initialize the memory where the initial stacks will reside
-
- This memory can contain the initial stacks (Secure and Secure Monitor stacks).
- In some platform, this region is already initialized and the implementation of this function can
- do nothing. This memory can also represent the Secure RAM.
- This function is called before the satck has been set up. Its implementation must ensure the stack
- pointer is not used (probably required to use assembly language)
-
-**/
-ArmPlatformInitializeBootMemory
- mov r5, lr
-
- //
- // Initialize PL354 SMC
- //
- LoadConstantToReg (ARM_VE_SMC_CTRL_BASE, r1)
-
- // NOR Flash 0
- mov r2, PL354_SMC_DIRECT_CMD_ADDR_CS(0,0)
- blx SMCInitializeNOR
-
- // NOR Flash 1
- mov r2, PL354_SMC_DIRECT_CMD_ADDR_CS(1,0)
- blx SMCInitializeNOR
-
- // Setup SRAM
- blx SMCInitializeSRAM
-
- // Memory Mapped Peripherals
- blx SMCInitializePeripherals
-
- // Initialize VRAM
- //TODO: Check if we really must inititialize Video SRAM in UEFI. Does Linux can do it ? Does the Video driver can do it ?
- // It will be faster (only initialize if required) and easier (remove assembly code because of a stack available) to move this initialization.
- LoadConstantToReg (VRAM_MOTHERBOARD_BASE, r2)
- blx SMCInitializeVRAM
-
- bx r5
-
- END
diff --git a/ArmPlatformPkg/Drivers/PL35xSmc/InitializeSMC.S b/ArmPlatformPkg/Drivers/PL35xSmc/InitializeSMC.S index 789c12cfe6..c7c535985e 100755 --- a/ArmPlatformPkg/Drivers/PL35xSmc/InitializeSMC.S +++ b/ArmPlatformPkg/Drivers/PL35xSmc/InitializeSMC.S @@ -21,176 +21,33 @@ #Maintain 8 byte alignment
.align 3
+GCC_ASM_EXPORT(PL35xSmcInitialize)
-GCC_ASM_EXPORT(SMCInitializeNOR)
-GCC_ASM_EXPORT(SMCInitializeSRAM)
-GCC_ASM_EXPORT(SMCInitializePeripherals)
-GCC_ASM_EXPORT(SMCInitializeVRAM)
-
-
-# CS0 CS0-Interf0 NOR1 flash on the motherboard
-# CS1 CS1-Interf0 Reserved for the motherboard
-# CS2 CS2-Interf0 SRAM on the motherboard
-# CS3 CS3-Interf0 memory-mapped Ethernet and USB controllers on the motherboard
-# CS4 CS0-Interf1 NOR2 flash on the motherboard
-# CS5 CS1-Interf1 memory-mapped peripherals
-# CS6 CS2-Interf1 memory-mapped peripherals
-# CS7 CS3-Interf1 system memory-mapped peripherals on the motherboard.
-
-// IN r1 SmcBase
-// IN r2 ChipSelect
+// IN r1 Smc Base Address
+// IN r2 Smc Configuration Start Address
+// IN r3 Smc Configuration End Address
// NOTE: This code is been called before any stack has been setup. It means some registers
// could be overwritten (case of 'r0')
-ASM_PFX(SMCInitializeNOR):
-#
-# Setup NOR1 (CS0-Interface0)
-#
-
- # Write to set_cycle register(holding register for NOR 1 cycle register or NAND cycle register)
- #Read cycle timeout = 0xA (0:3)
- #Write cycle timeout = 0x3(7:4)
- #OE Assertion Delay = 0x9(11:8)
- #WE Assertion delay = 0x3(15:12)
- #Page cycle timeout = 0x2(19:16)
- LoadConstantToReg (0x0002393A,r0) @ldr r0, = 0x0002393A
- str r0, [r1, #PL354_SMC_SET_CYCLES_OFFSET]
-
- # Write to set_opmode register(holding register for NOR 1 opomode register or NAND opmode register)
- # 0x00000002 = MemoryWidth: 32bit
- # 0x00000028 = ReadMemoryBurstLength:continuous
- # 0x00000280 = WriteMemoryBurstLength:continuous
- # 0x00000800 = Set Address Valid
- LoadConstantToReg (0x00000AAA,r0) @ldr r0, = 0x00000AAA
- str r0, [r1, #PL354_SMC_SET_OPMODE_OFFSET]
-
- # Write to direct_cmd register so that the NOR 1 registers(set-cycles and opmode) are updated with holding registers
- # 0x00000000 = ChipSelect0-Interface 0
- # 0x00400000 = CmdTypes: UpdateRegs
- LoadConstantToReg (0x00400000,r0) @ldr r0, = 0x00400000
- str r0, [r1, #PL354_SMC_DIRECT_CMD_OFFSET]
-
- bx lr
-
-ASM_PFX(SMCInitializeSRAM):
-#
-# Setup SRAM (CS2-Interface0)
-#
- LoadConstantToReg (0x00027158,r0) @ldr r0, = 0x00027158
- str r0, [r1, #PL354_SMC_SET_CYCLES_OFFSET]
-
- # 0x00000002 = MemoryWidth: 32bit
- # 0x00000800 = Set Address Valid
- LoadConstantToReg (0x00000802,r0) @ldr r0, = 0x00000802
- str r0, [r1, #PL354_SMC_SET_OPMODE_OFFSET]
-
- # 0x01000000 = ChipSelect2-Interface 0
- # 0x00400000 = CmdTypes: UpdateRegs
- LoadConstantToReg (0x01400000,r0) @ldr r0, = 0x01400000
- str r0, [r1, #PL354_SMC_DIRECT_CMD_OFFSET]
-
- bx lr
+ASM_PFX(PL35xSmcInitialize):
+ // While (SmcConfigurationStart < SmcConfigurationEnd)
+ cmp r2, r3
+ blxge lr
-ASM_PFX(SMCInitializePeripherals):
-#
-# USB/Eth/VRAM (CS3-Interface0)
-#
- LoadConstantToReg (0x000CD2AA,r0) @ldr r0, = 0x000CD2AA
- str r0, [r1, #PL354_SMC_SET_CYCLES_OFFSET]
-
- # 0x00000002 = MemoryWidth: 32bit
- # 0x00000004 = Memory reads are synchronous
- # 0x00000040 = Memory writes are synchronous
- LoadConstantToReg (0x00000046,r0) @ldr r0, = 0x00000046
- str r0, [r1, #PL354_SMC_SET_OPMODE_OFFSET]
-
- # 0x01800000 = ChipSelect3-Interface 0
- # 0x00400000 = CmdTypes: UpdateRegs
- LoadConstantToReg (0x01C00000,r0) @ldr r0, = 0x01C00000
- str r0, [r1, #PL354_SMC_DIRECT_CMD_OFFSET]
+ // Write to set_cycle register(holding register for NOR 1 cycle register or NAND cycle register)
+ ldr r0, [r2, #0x4]
+ str r0, [r1, #PL350_SMC_SET_CYCLES_OFFSET]
-#
-# Setup NOR3 (CS0-Interface1)
-#
- LoadConstantToReg (0x0002393A,r0) @ldr r0, = 0x0002393A
- str r0, [r1, #PL354_SMC_SET_CYCLES_OFFSET]
-
- # 0x00000002 = MemoryWidth: 32bit
- # 0x00000028 = ReadMemoryBurstLength:continuous
- # 0x00000280 = WriteMemoryBurstLength:continuous
- # 0x00000800 = Set Address Valid
- LoadConstantToReg (0x00000AAA,r0) @ldr r0, = 0x00000AAA
- str r0, [r1, #PL354_SMC_SET_OPMODE_OFFSET]
-
- # 0x02000000 = ChipSelect0-Interface 1
- # 0x00400000 = CmdTypes: UpdateRegs
- LoadConstantToReg (0x02400000,r0) @ldr r0, = 0x02400000
- str r0, [r1, #PL354_SMC_DIRECT_CMD_OFFSET]
-
-#
-# Setup Peripherals (CS3-Interface1)
-#
- LoadConstantToReg (0x00025156,r0) @ldr r0, = 0x00025156
- str r0, [r1, #PL354_SMC_SET_CYCLES_OFFSET]
-
- # 0x00000002 = MemoryWidth: 32bit
- # 0x00000004 = Memory reads are synchronous
- # 0x00000040 = Memory writes are synchronous
- LoadConstantToReg (0x00000046,r0) @ldr r0, = 0x00000046
- str r0, [r1, #PL354_SMC_SET_OPMODE_OFFSET]
-
- # 0x03800000 = ChipSelect3-Interface 1
- # 0x00400000 = CmdTypes: UpdateRegs
- LoadConstantToReg (0x03C00000,r0) @ldr r0, = 0x03C00000
- str r0, [r1, #PL354_SMC_DIRECT_CMD_OFFSET]
- bx lr
+ // Write to set_opmode register(holding register for NOR 1 opomode register or NAND opmode register)
+ ldr r0, [r2, #0x8]
+ str r0, [r1, #PL350_SMC_SET_OPMODE_OFFSET]
-// IN r1 SmcBase
-// IN r2 VideoSRamBase
-// NOTE: This code is been called before any stack has been setup. It means some registers
-// could be overwritten (case of 'r0')
-ASM_PFX(SMCInitializeVRAM):
-#
-# Setup VRAM (CS1-Interface0)
-#
- LoadConstantToReg (0x00049249,r0) @ldr r0, = 0x00049249
- str r0, [r1, #PL354_SMC_SET_CYCLES_OFFSET]
-
- # 0x00000002 = MemoryWidth: 32bit
- # 0x00000004 = Memory reads are synchronous
- # 0x00000040 = Memory writes are synchronous
- LoadConstantToReg (0x00000046,r0) @ldr r0, = 0x00000046
- str r0, [r1, #PL354_SMC_SET_OPMODE_OFFSET]
-
- # 0x00800000 = ChipSelect1-Interface 0
- # 0x00400000 = CmdTypes: UpdateRegs
- LoadConstantToReg (0x00C00000,r0) @ldr r0, = 0x00C00000
- str r0, [r1, #PL354_SMC_DIRECT_CMD_OFFSET]
-
-#
-# Page mode setup for VRAM
-#
- #read current state
- ldr r0, [r2, #0]
- ldr r0, [r2, #0]
- LoadConstantToReg (0x00000000,r0) @ldr r0, = 0x00000000
- str r0, [r2, #0]
- ldr r0, [r2, #0]
+ // Write to direct_cmd register so that the NOR 1 registers(set-cycles and opmode) are updated with holding registers
+ ldr r0, =PL350_SMC_DIRECT_CMD_ADDR_CMD_UPDATE
+ ldr r4, [r2, #0x0]
+ orr r0, r0, r4
+ str r0, [r1, #PL350_SMC_DIRECT_CMD_OFFSET]
- #enable page mode
- ldr r0, [r2, #0]
- ldr r0, [r2, #0]
- LoadConstantToReg (0x00000000,r0) @ldr r0, = 0x00000000
- str r0, [r2, #0]
- LoadConstantToReg (0x00900090,r0) @ldr r0, = 0x00900090
- str r0, [r2, #0]
+ add r2, #0xC
+ b ASM_PFX(PL350SmcInitialize)
- #confirm page mode enabled
- ldr r0, [r2, #0]
- ldr r0, [r2, #0]
- LoadConstantToReg (0x00000000,r0) @ldr r0, = 0x00000000
- str r0, [r2, #0]
- ldr r0, [r2, #0]
-
- bx lr
-
ASM_FUNCTION_REMOVE_IF_UNREFERENCED
\ No newline at end of file diff --git a/ArmPlatformPkg/Drivers/PL35xSmc/InitializeSMC.asm b/ArmPlatformPkg/Drivers/PL35xSmc/InitializeSMC.asm index 732500e13a..8edc6c1028 100755 --- a/ArmPlatformPkg/Drivers/PL35xSmc/InitializeSMC.asm +++ b/ArmPlatformPkg/Drivers/PL35xSmc/InitializeSMC.asm @@ -18,136 +18,35 @@ INCLUDE AsmMacroIoLib.inc
- EXPORT SMCInitializeNOR
- EXPORT SMCInitializeSRAM
- EXPORT SMCInitializePeripherals
- EXPORT SMCInitializeVRAM
+ EXPORT PL35xSmcInitialize
PRESERVE8
AREA ModuleInitializeSMC, CODE, READONLY
-// CS0 CS0-Interf0 NOR1 flash on the motherboard
-// CS1 CS1-Interf0 Reserved for the motherboard
-// CS2 CS2-Interf0 SRAM on the motherboard
-// CS3 CS3-Interf0 memory-mapped Ethernet and USB controllers on the motherboard
-// CS4 CS0-Interf1 NOR2 flash on the motherboard
-// CS5 CS1-Interf1 memory-mapped peripherals
-// CS6 CS2-Interf1 memory-mapped peripherals
-// CS7 CS3-Interf1 system memory-mapped peripherals on the motherboard.
-
-// IN r1 SmcBase
-// IN r2 ChipSelect
+// IN r1 Smc Base Address
+// IN r2 Smc Configuration Start Address
+// IN r3 Smc Configuration End Address
// NOTE: This code is been called before any stack has been setup. It means some registers
// could be overwritten (case of 'r0')
-SMCInitializeNOR
+PL35xSmcInitialize
+ // While (SmcConfigurationStart < SmcConfigurationEnd)
+ cmp r2, r3
+ blxge lr
+
// Write to set_cycle register(holding register for NOR 1 cycle register or NAND cycle register)
- // - Read cycle timeout = 0xA (0:3)
- // - Write cycle timeout = 0x3(7:4)
- // - OE Assertion Delay = 0x9(11:8)
- // - WE Assertion delay = 0x3(15:12)
- // - Page cycle timeout = 0x2(19:16)
- ldr r0, = 0x0002393A
- str r0, [r1, #PL354_SMC_SET_CYCLES_OFFSET]
-
+ ldr r0, [r2, #0x4]
+ str r0, [r1, #PL350_SMC_SET_CYCLES_OFFSET]
+
// Write to set_opmode register(holding register for NOR 1 opomode register or NAND opmode register)
- ldr r0, = (PL354_SMC_SET_OPMODE_MEM_WIDTH_32 :OR: PL354_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_CONT :OR: PL354_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_CONT :OR: PL354_SMC_SET_OPMODE_SET_ADV)
- str r0, [r1, #PL354_SMC_SET_OPMODE_OFFSET]
+ ldr r0, [r2, #0x8]
+ str r0, [r1, #PL350_SMC_SET_OPMODE_OFFSET]
// Write to direct_cmd register so that the NOR 1 registers(set-cycles and opmode) are updated with holding registers
- ldr r0, =PL354_SMC_DIRECT_CMD_ADDR_CMD_UPDATE
- orr r0, r0, r2
- str r0, [r1, #PL354_SMC_DIRECT_CMD_OFFSET]
-
- bx lr
-
-
-//
-// Setup SRAM (CS2-Interface0)
-//
-SMCInitializeSRAM
- ldr r0, = 0x00027158
- str r0, [r1, #PL354_SMC_SET_CYCLES_OFFSET]
-
- ldr r0, =(PL354_SMC_SET_OPMODE_MEM_WIDTH_32 :OR: PL354_SMC_SET_OPMODE_SET_ADV)
- str r0, [r1, #PL354_SMC_SET_OPMODE_OFFSET]
-
- ldr r0, =(PL354_SMC_DIRECT_CMD_ADDR_CMD_UPDATE :OR: PL354_SMC_DIRECT_CMD_ADDR_CS(0,2))
- str r0, [r1, #PL354_SMC_DIRECT_CMD_OFFSET]
-
- bx lr
-
-SMCInitializePeripherals
-//
-// USB/Eth/VRAM (CS3-Interface0)
-//
- ldr r0, = 0x000CD2AA
- str r0, [r1, #PL354_SMC_SET_CYCLES_OFFSET]
-
- ldr r0, =(PL354_SMC_SET_OPMODE_MEM_WIDTH_32 :OR: PL354_SMC_SET_OPMODE_SET_RD_SYNC :OR: PL354_SMC_SET_OPMODE_SET_WR_SYNC)
- str r0, [r1, #PL354_SMC_SET_OPMODE_OFFSET]
-
- ldr r0, =(PL354_SMC_DIRECT_CMD_ADDR_CMD_UPDATE :OR: PL354_SMC_DIRECT_CMD_ADDR_CS(0,3))
- str r0, [r1, #PL354_SMC_DIRECT_CMD_OFFSET]
-
-
-//
-// Setup Peripherals (CS3-Interface1)
-//
- ldr r0, = 0x00025156
- str r0, [r1, #PL354_SMC_SET_CYCLES_OFFSET]
-
- ldr r0, =(PL354_SMC_SET_OPMODE_MEM_WIDTH_32 :OR: PL354_SMC_SET_OPMODE_SET_RD_SYNC :OR: PL354_SMC_SET_OPMODE_SET_WR_SYNC)
- str r0, [r1, #PL354_SMC_SET_OPMODE_OFFSET]
-
- ldr r0, =(PL354_SMC_DIRECT_CMD_ADDR_CMD_UPDATE :OR: PL354_SMC_DIRECT_CMD_ADDR_CS(1,3))
- str r0, [r1, #PL354_SMC_DIRECT_CMD_OFFSET]
-
- bx lr
-
+ ldr r0, =PL350_SMC_DIRECT_CMD_ADDR_CMD_UPDATE
+ ldr r4, [r2, #0x0]
+ orr r0, r0, r4
+ str r0, [r1, #PL350_SMC_DIRECT_CMD_OFFSET]
-// IN r1 SmcBase
-// IN r2 VideoSRamBase
-// NOTE: This code is been called before any stack has been setup. It means some registers
-// could be overwritten (case of 'r0')
-SMCInitializeVRAM
- //
- // Setup VRAM (CS1-Interface0)
- //
- ldr r0, = 0x00049249
- str r0, [r1, #PL354_SMC_SET_CYCLES_OFFSET]
-
- ldr r0, = (PL354_SMC_SET_OPMODE_MEM_WIDTH_32 :OR: PL354_SMC_SET_OPMODE_SET_RD_SYNC :OR: PL354_SMC_SET_OPMODE_SET_WR_SYNC)
- str r0, [r1, #PL354_SMC_SET_OPMODE_OFFSET]
-
- ldr r0, = (PL354_SMC_DIRECT_CMD_ADDR_CMD_UPDATE :OR: PL354_SMC_DIRECT_CMD_ADDR_CS(0,1))
- str r0, [r1, #PL354_SMC_DIRECT_CMD_OFFSET]
-
- //
- // Page mode setup for VRAM
- //
-
- // Read current state
- ldr r0, [r2, #0]
- ldr r0, [r2, #0]
- ldr r0, = 0x00000000
- str r0, [r2, #0]
- ldr r0, [r2, #0]
+ add r2, #0xC
+ b PL35xSmcInitialize
- // Enable page mode
- ldr r0, [r2, #0]
- ldr r0, [r2, #0]
- ldr r0, = 0x00000000
- str r0, [r2, #0]
- ldr r0, = 0x00900090
- str r0, [r2, #0]
-
- // Confirm page mode enabled
- ldr r0, [r2, #0]
- ldr r0, [r2, #0]
- ldr r0, = 0x00000000
- str r0, [r2, #0]
- ldr r0, [r2, #0]
-
- bx lr
-
- END
diff --git a/ArmPlatformPkg/Include/Drivers/PL35xSmc.h b/ArmPlatformPkg/Include/Drivers/PL35xSmc.h index 0da47f9982..52d64f482b 100644 --- a/ArmPlatformPkg/Include/Drivers/PL35xSmc.h +++ b/ArmPlatformPkg/Include/Drivers/PL35xSmc.h @@ -12,46 +12,62 @@ *
**/
-#ifndef PL354SMC_H_
-#define PL354SMC_H_
+#ifndef PL35xSMC_H_
+#define PL35xSMC_H_
-#define PL354_SMC_DIRECT_CMD_OFFSET 0x10
-#define PL354_SMC_SET_CYCLES_OFFSET 0x14
-#define PL354_SMC_SET_OPMODE_OFFSET 0x18
+#define PL350_SMC_DIRECT_CMD_OFFSET 0x10
+#define PL350_SMC_SET_CYCLES_OFFSET 0x14
+#define PL350_SMC_SET_OPMODE_OFFSET 0x18
-#define PL354_SMC_DIRECT_CMD_ADDR(addr) ((addr) & 0xFFFFF)
-#define PL354_SMC_DIRECT_CMD_ADDR_SET_CRE (1 << 20)
-#define PL354_SMC_DIRECT_CMD_ADDR_CMD_MODE_UPDATE (3 << 21)
-#define PL354_SMC_DIRECT_CMD_ADDR_CMD_UPDATE (2 << 21)
-#define PL354_SMC_DIRECT_CMD_ADDR_CMD_MODE (1 << 21)
-#define PL354_SMC_DIRECT_CMD_ADDR_CMD_UPDATE_AXI (0 << 21)
-#define PL354_SMC_DIRECT_CMD_ADDR_CS(interf,chip) (((interf) << 25) | ((chip) << 23))
+#define PL350_SMC_DIRECT_CMD_ADDR(addr) ((addr) & 0xFFFFF)
+#define PL350_SMC_DIRECT_CMD_ADDR_SET_CRE (1 << 20)
+#define PL350_SMC_DIRECT_CMD_ADDR_CMD_MODE_UPDATE (3 << 21)
+#define PL350_SMC_DIRECT_CMD_ADDR_CMD_UPDATE (2 << 21)
+#define PL350_SMC_DIRECT_CMD_ADDR_CMD_MODE (1 << 21)
+#define PL350_SMC_DIRECT_CMD_ADDR_CMD_UPDATE_AXI (0 << 21)
+#define PL350_SMC_DIRECT_CMD_ADDR_CS_INTERF(interf,chip) (((interf) << 25) | ((chip) << 23))
+#define PL350_SMC_DIRECT_CMD_ADDR_CS(ChipSelect) (((ChipSelect) & 0x7) << 23)
-#define PL354_SMC_SET_OPMODE_MEM_WIDTH_8 (0 << 0)
-#define PL354_SMC_SET_OPMODE_MEM_WIDTH_16 (1 << 0)
-#define PL354_SMC_SET_OPMODE_MEM_WIDTH_32 (2 << 0)
-#define PL354_SMC_SET_OPMODE_SET_RD_SYNC (1 << 2)
-#define PL354_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_1 (0 << 3)
-#define PL354_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_4 (1 << 3)
-#define PL354_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_8 (2 << 3)
-#define PL354_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_16 (3 << 3)
-#define PL354_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_32 (4 << 3)
-#define PL354_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_CONT (5 << 3)
-#define PL354_SMC_SET_OPMODE_SET_WR_SYNC (1 << 6)
-#define PL354_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_1 (0 << 7)
-#define PL354_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_4 (1 << 7)
-#define PL354_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_8 (2 << 7)
-#define PL354_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_16 (3 << 7)
-#define PL354_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_32 (4 << 7)
-#define PL354_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_CONT (5 << 7)
-#define PL354_SMC_SET_OPMODE_SET_BAA (1 << 10)
-#define PL354_SMC_SET_OPMODE_SET_ADV (1 << 11)
-#define PL354_SMC_SET_OPMODE_SET_BLS (1 << 12)
-#define PL354_SMC_SET_OPMODE_SET_BURST_ALIGN_ANY (0 << 13)
-#define PL354_SMC_SET_OPMODE_SET_BURST_ALIGN_32 (1 << 13)
-#define PL354_SMC_SET_OPMODE_SET_BURST_ALIGN_64 (2 << 13)
-#define PL354_SMC_SET_OPMODE_SET_BURST_ALIGN_128 (3 << 13)
-#define PL354_SMC_SET_OPMODE_SET_BURST_ALIGN_256 (4 << 13)
+#define PL350_SMC_SET_OPMODE_MEM_WIDTH_8 (0 << 0)
+#define PL350_SMC_SET_OPMODE_MEM_WIDTH_16 (1 << 0)
+#define PL350_SMC_SET_OPMODE_MEM_WIDTH_32 (2 << 0)
+#define PL350_SMC_SET_OPMODE_SET_RD_SYNC (1 << 2)
+#define PL350_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_1 (0 << 3)
+#define PL350_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_4 (1 << 3)
+#define PL350_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_8 (2 << 3)
+#define PL350_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_16 (3 << 3)
+#define PL350_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_32 (4 << 3)
+#define PL350_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_CONT (5 << 3)
+#define PL350_SMC_SET_OPMODE_SET_WR_SYNC (1 << 6)
+#define PL350_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_1 (0 << 7)
+#define PL350_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_4 (1 << 7)
+#define PL350_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_8 (2 << 7)
+#define PL350_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_16 (3 << 7)
+#define PL350_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_32 (4 << 7)
+#define PL350_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_CONT (5 << 7)
+#define PL350_SMC_SET_OPMODE_SET_BAA (1 << 10)
+#define PL350_SMC_SET_OPMODE_SET_ADV (1 << 11)
+#define PL350_SMC_SET_OPMODE_SET_BLS (1 << 12)
+#define PL350_SMC_SET_OPMODE_SET_BURST_ALIGN_ANY (0 << 13)
+#define PL350_SMC_SET_OPMODE_SET_BURST_ALIGN_32 (1 << 13)
+#define PL350_SMC_SET_OPMODE_SET_BURST_ALIGN_64 (2 << 13)
+#define PL350_SMC_SET_OPMODE_SET_BURST_ALIGN_128 (3 << 13)
+#define PL350_SMC_SET_OPMODE_SET_BURST_ALIGN_256 (4 << 13)
+#define PL350_SMC_SET_CYCLE_NAND_T_RC(t) (((t) & 0xF) << 0)
+#define PL350_SMC_SET_CYCLE_NAND_T_WC(t) (((t) & 0xF) << 4)
+#define PL350_SMC_SET_CYCLE_NAND_T_REA(t) (((t) & 0x7) << 8)
+#define PL350_SMC_SET_CYCLE_NAND_T_WP(t) (((t) & 0x7) << 11)
+#define PL350_SMC_SET_CYCLE_NAND_T_CLR(t) (((t) & 0x7) << 14)
+#define PL350_SMC_SET_CYCLE_NAND_T_AR(t) (((t) & 0x7) << 17)
+#define PL350_SMC_SET_CYCLE_NAND_T_RR(t) (((t) & 0x7) << 20)
+
+#define PL350_SMC_SET_CYCLE_SRAM_T_RC(t) (((t) & 0xF) << 0)
+#define PL350_SMC_SET_CYCLE_SRAM_T_WC(t) (((t) & 0xF) << 4)
+#define PL350_SMC_SET_CYCLE_SRAM_T_CEOE(t) (((t) & 0x7) << 8)
+#define PL350_SMC_SET_CYCLE_SRAM_T_WP(t) (((t) & 0x7) << 11)
+#define PL350_SMC_SET_CYCLE_SRAM_T_PC(t) (((t) & 0x7) << 14)
+#define PL350_SMC_SET_CYCLE_SRAM_T_TR(t) (((t) & 0x7) << 17)
+#define PL350_SMC_SET_CYCLE_SRAM_WE_TIME (1 << 20)
#endif
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