Integrate MR3 FSP

Change code to integrate MR3 FSP.

Contributed-under: TianoCore Contribution Agreement 1.1

Signed-off-by: Guo Mang <mang.guo@intel.com>

11 files changed, 137 insertions, 111 deletions

diff --git a/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPreMem/BoardInitMiscs.c b/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPreMem/BoardInitMiscs.c
index 5424df06f0..d0987bbbf4 100644
--- a/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPreMem/BoardInitMiscs.c
+++ b/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPreMem/BoardInitMiscs.c
@@ -19,6 +19,16 @@
 UPDATE_FSPM_UPD_FUNC mBgUpdateFspmUpdPtr = BgUpdateFspmUpd;

 DRAM_CREATE_POLICY_DEFAULTS_FUNC   mBgDramCreatePolicyDefaultsPtr = BgDramCreatePolicyDefaults;

 

+//

+// Benson Glacier swizzling

+//

+UINT8 ChSwizzle_BG[DRAM_POLICY_NUMBER_CHANNELS][DRAM_POLICY_NUMBER_BITS] = {

+  {9,11,10,12,14,15,8,13,0,3,5,1,2,6,7,4,28,25,27,26,29,30,31,24,17,22,23,18,19,20,21,16}, // Channel 0

+  {0,1,5,4,3,6,7,2,12,13,10,14,15,8,9,11,20,23,22,17,21,19,18,16,26,28,29,24,31,25,30,27}, // Channel 1

+  {13,9,15,8,11,10,12,14,2,3,7,4,1,6,0,5,31,29,26,28,25,24,30,27,21,23,16,18,20,19,17,22}, // Channel 2

+  {3,1,6,7,2,5,4,0,8,9,11,10,12,14,13,15,21,17,18,19,23,22,16,20,29,27,25,30,28,24,31,26}  // Channel 3

+};

+

 EFI_STATUS

 EFIAPI

 BgUpdateFspmUpd (

@@ -30,7 +40,8 @@ BgUpdateFspmUpd (
   EFI_PLATFORM_INFO_HOB          *PlatformInfo = NULL;

   DRAM_POLICY_PPI                *DramPolicy;

   EFI_STATUS                     Status;

-  MRC_NV_DATA_FRAME              *MrcNvData;

+  MRC_PARAMS_SAVE_RESTORE        *MrcNvData;

+  BOOT_VARIABLE_NV_DATA          *BootVariableNvData;

   MRC_PARAMS_SAVE_RESTORE        *MrcParamsHob;

   BOOT_VARIABLE_NV_DATA          *BootVariableNvDataHob;

 

@@ -73,13 +84,18 @@ BgUpdateFspmUpd (
     CopyMem (&(FspUpdRgn->FspmConfig.Ch0_Bit_swizzling), &DramPolicy->ChSwizzle, sizeof (DramPolicy->ChSwizzle));

 

     if (((VOID *)(UINT32)DramPolicy->MrcTrainingDataPtr != 0) &&

-        ((VOID *)(UINT32)DramPolicy->MrcBootDataPtr     != 0)) {

-      MrcNvData = (MRC_NV_DATA_FRAME *) AllocateZeroPool (sizeof (MRC_NV_DATA_FRAME));

-      MrcParamsHob = (MRC_PARAMS_SAVE_RESTORE*)((UINT32)DramPolicy->MrcTrainingDataPtr);

+       ((VOID *)(UINT32)DramPolicy->MrcBootDataPtr     != 0)) {

+      DEBUG ((DEBUG_INFO, "UpdateFspmUpd - NvsBufferPtr\n"));

+      MrcNvData          = (MRC_PARAMS_SAVE_RESTORE *) AllocateZeroPool (sizeof (MRC_PARAMS_SAVE_RESTORE));

+      BootVariableNvData = (BOOT_VARIABLE_NV_DATA *) AllocateZeroPool (sizeof (BOOT_VARIABLE_NV_DATA));

+

+      MrcParamsHob          = (MRC_PARAMS_SAVE_RESTORE*)((UINT32)DramPolicy->MrcTrainingDataPtr);

       BootVariableNvDataHob = (BOOT_VARIABLE_NV_DATA*)((UINT32)DramPolicy->MrcBootDataPtr);

-      CopyMem(&(MrcNvData->MrcParamsSaveRestore), MrcParamsHob, sizeof (MRC_PARAMS_SAVE_RESTORE));

-      CopyMem(&(MrcNvData->BootVariableNvData), BootVariableNvDataHob, sizeof (BOOT_VARIABLE_NV_DATA));

-      FspUpdRgn->FspmArchUpd.NvsBufferPtr = (VOID *)(UINT32)MrcNvData;

+

+      CopyMem(MrcNvData, MrcParamsHob, sizeof (MRC_PARAMS_SAVE_RESTORE));

+      CopyMem(BootVariableNvData, BootVariableNvDataHob, sizeof (BOOT_VARIABLE_NV_DATA));

+      FspUpdRgn->FspmArchUpd.NvsBufferPtr        = (VOID *)(UINT32)MrcNvData;

+      FspUpdRgn->FspmConfig.VariableNvsBufferPtr = (VOID *)(UINT32)BootVariableNvData;

     }

 

   }

@@ -89,7 +105,7 @@ BgUpdateFspmUpd (
   ASSERT (Hob.Raw != NULL);

   PlatformInfo = GET_GUID_HOB_DATA (Hob.Raw);

 

-  DEBUG ((DEBUG_INFO, "**** BG - UpdateFspmUpd,BoardId = %d\n", PlatformInfo->BoardId));

+  DEBUG ((DEBUG_INFO, "**** BG - UpdateFspmUpd,BoardId = 0x%02x\n", PlatformInfo->BoardId));

   if (PlatformInfo->BoardId != BOARD_ID_BENSON) {

     //

     // ASSERT false if BoardId isn't Benson

@@ -97,36 +113,43 @@ BgUpdateFspmUpd (
     ASSERT (FALSE);

   }

 

-  FspUpdRgn->FspmConfig.Package         = 1;

-  FspUpdRgn->FspmConfig.Profile         = 11;

-  FspUpdRgn->FspmConfig.MemoryDown      = 1;

-  FspUpdRgn->FspmConfig.DDR3LPageSize   = 0;

-  FspUpdRgn->FspmConfig.DDR3LASR        = 0;

-  FspUpdRgn->FspmConfig.MemorySizeLimit = 0x1800;

-  FspUpdRgn->FspmConfig.DIMM0SPDAddress = 0;

-  FspUpdRgn->FspmConfig.DIMM1SPDAddress = 0;

-  FspUpdRgn->FspmConfig.DDR3LPageSize   = 0;

-  FspUpdRgn->FspmConfig.DDR3LASR        = 0;

-

-  FspUpdRgn->FspmConfig.Ch0_RankEnable   = 1;

-  FspUpdRgn->FspmConfig.Ch0_DeviceWidth  = 2;

-  FspUpdRgn->FspmConfig.Ch0_DramDensity  = 2;

-  FspUpdRgn->FspmConfig.Ch0_Option       = 3;

-

-  FspUpdRgn->FspmConfig.Ch1_RankEnable   = 1;

-  FspUpdRgn->FspmConfig.Ch1_DeviceWidth  = 2;

-  FspUpdRgn->FspmConfig.Ch1_DramDensity  = 2;

-  FspUpdRgn->FspmConfig.Ch1_Option       = 3;

-

-  FspUpdRgn->FspmConfig.Ch2_RankEnable   = 1;

-  FspUpdRgn->FspmConfig.Ch2_DeviceWidth  = 2;

-  FspUpdRgn->FspmConfig.Ch2_DramDensity  = 2;

-  FspUpdRgn->FspmConfig.Ch2_Option       = 3;

-

-  FspUpdRgn->FspmConfig.Ch3_RankEnable   = 1;

-  FspUpdRgn->FspmConfig.Ch3_DeviceWidth  = 2;

-  FspUpdRgn->FspmConfig.Ch3_DramDensity  = 2;

-  FspUpdRgn->FspmConfig.Ch3_Option       = 3;

+  //

+  // Overrides for Benson Glacier (Micron #MT53B512M32D2NP-062 AIT:C) from Platfrom4 profile

+  //

+  FspUpdRgn->FspmConfig.Package               = 0x01;

+  FspUpdRgn->FspmConfig.Profile               = 0x0B; // LPDDR4_2400_24_22_22

+  FspUpdRgn->FspmConfig.MemoryDown            = 0x01;

+  FspUpdRgn->FspmConfig.DualRankSupportEnable = 0x01;

+  

+  FspUpdRgn->FspmConfig.Ch0_RankEnable        = 0x03; // [0]: Rank 0 [1]: Rank 1

+  FspUpdRgn->FspmConfig.Ch0_DeviceWidth       = 0x01; // x16

+  FspUpdRgn->FspmConfig.Ch0_DramDensity       = 0x02; // 8Gb

+  FspUpdRgn->FspmConfig.Ch0_Option            = 0x03;

+

+  FspUpdRgn->FspmConfig.Ch1_RankEnable        = 0x03; // [0]: Rank 0 [1]: Rank 1

+  FspUpdRgn->FspmConfig.Ch1_DeviceWidth       = 0x01; // x16

+  FspUpdRgn->FspmConfig.Ch1_DramDensity       = 0x02; // 8Gb

+  FspUpdRgn->FspmConfig.Ch1_Option            = 0x03;

+

+  FspUpdRgn->FspmConfig.Ch2_RankEnable        = 0x03; // [0]: Rank 0 [1]: Rank 1

+  FspUpdRgn->FspmConfig.Ch2_DeviceWidth       = 0x01; // x16

+  FspUpdRgn->FspmConfig.Ch2_DramDensity       = 0x02; // 8Gb

+  FspUpdRgn->FspmConfig.Ch2_Option            = 0x03;

+

+  FspUpdRgn->FspmConfig.Ch3_RankEnable        = 0x03; // [0]: Rank 0 [1]: Rank 1

+  FspUpdRgn->FspmConfig.Ch3_DeviceWidth       = 0x01; // x16

+  FspUpdRgn->FspmConfig.Ch3_DramDensity       = 0x02; // 8Gb

+  FspUpdRgn->FspmConfig.Ch3_Option            = 0x03;

+

+  //

+  // Swizzling

+  //

+  if (ChSwizzle_BG != NULL) {

+    CopyMem (&(FspUpdRgn->FspmConfig.Ch0_Bit_swizzling), ChSwizzle_BG[0], DRAM_POLICY_NUMBER_BITS * sizeof(UINT8));

+    CopyMem (&(FspUpdRgn->FspmConfig.Ch1_Bit_swizzling), ChSwizzle_BG[1], DRAM_POLICY_NUMBER_BITS * sizeof(UINT8));

+    CopyMem (&(FspUpdRgn->FspmConfig.Ch2_Bit_swizzling), ChSwizzle_BG[2], DRAM_POLICY_NUMBER_BITS * sizeof(UINT8));

+    CopyMem (&(FspUpdRgn->FspmConfig.Ch3_Bit_swizzling), ChSwizzle_BG[3], DRAM_POLICY_NUMBER_BITS * sizeof(UINT8));

+  }

 

   return EFI_SUCCESS;

 }

@@ -160,7 +183,6 @@ BgDramCreatePolicyDefaults (
   UINT8                               (*ChSwizlePtr)[DRAM_POLICY_NUMBER_CHANNELS][DRAM_POLICY_NUMBER_BITS];

   PlatfromDramConf                    *DramConfig;

   BOOLEAN                             ReadSetupVars;

-  EFI_PEI_HOB_POINTERS                Hob;

 

   DEBUG ((EFI_D_INFO, "*** Benson Glacier DramCreatePolicyDefaults\n"));

   DramPolicy = (DRAM_POLICY_PPI *) AllocateZeroPool (sizeof (DRAM_POLICY_PPI));

@@ -257,12 +279,22 @@ BgDramCreatePolicyDefaults (
     DramPolicy->InterleavedMode         = DramConfig->InterleavedMode;

     DramPolicy->MinRefRate2xEnabled     = DramConfig->MinRefRate2xEnabled;

     DramPolicy->DualRankSupportEnabled  = DramConfig->DualRankSupportEnabled;

-}

+  }

 

+  //

+  // DRP

+  //

   if (DrpPtr != NULL) {

     CopyMem (DramPolicy->ChDrp, DrpPtr, sizeof (DramPolicy->ChDrp));

   }

 

+  //

+  // Swizzling

+  //

+  if (ChSwizlePtr != NULL) {

+    CopyMem (DramPolicy->ChSwizzle, ChSwizlePtr, sizeof (DramPolicy->ChSwizzle));

+  }

+

   Status = VariablePpi->GetVariable (

                           VariablePpi,

                           PLATFORM_SETUP_VARIABLE_NAME,

@@ -278,33 +310,10 @@ BgDramCreatePolicyDefaults (
     }

   }

 

-  if (ChSwizlePtr != NULL) CopyMem (DramPolicy->ChSwizzle, ChSwizlePtr, sizeof (DramPolicy->ChSwizzle));

-

   DramPolicy->MrcTrainingDataPtr = (EFI_PHYSICAL_ADDRESS) *MrcTrainingDataAddr;

   DramPolicy->MrcBootDataPtr     = (EFI_PHYSICAL_ADDRESS) *MrcBootDataAddr;

 

-  //

-  // WA for MH board to 6GB. We just apply it if memory size has not been override in smip XML.

-  //

-  if (DramPolicy->SystemMemorySizeLimit == 0) {

-    DramPolicy->SystemMemorySizeLimit = 0x1800;

-    if ((DramPolicy->ChDrp[2].RankEnable == 0) && (DramPolicy->ChDrp[3].RankEnable == 0)) {  //half config

-      DramPolicy->SystemMemorySizeLimit /= 2;

-    }

-  }

-

-  //

-  // Get Platform Info HOB

-  //

-  Hob.Raw = GetFirstGuidHob (&gEfiPlatformInfoGuid);

-  ASSERT (Hob.Raw != NULL);

-

-

-  DEBUG ((EFI_D_INFO, "Benson has single rank memory\n"));

-  DramPolicy->DualRankSupportEnabled = FALSE;

-

   *DramPolicyPpi = DramPolicy;

 

   return EFI_SUCCESS;

 }

-

diff --git a/Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPreMem/BoardInitMiscs.c b/Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPreMem/BoardInitMiscs.c
index fe8ece0b88..6abeb1d349 100644
--- a/Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPreMem/BoardInitMiscs.c
+++ b/Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPreMem/BoardInitMiscs.c
@@ -30,7 +30,8 @@ LhUpdateFspmUpd (
   EFI_PLATFORM_INFO_HOB          *PlatformInfo = NULL;

   DRAM_POLICY_PPI                *DramPolicy;

   EFI_STATUS                     Status;

-  MRC_NV_DATA_FRAME              *MrcNvData;

+  MRC_PARAMS_SAVE_RESTORE        *MrcNvData;

+  BOOT_VARIABLE_NV_DATA          *BootVariableNvData;

   MRC_PARAMS_SAVE_RESTORE        *MrcParamsHob;

   BOOT_VARIABLE_NV_DATA          *BootVariableNvDataHob;

 

@@ -74,12 +75,17 @@ LhUpdateFspmUpd (
 

     if (((VOID *)(UINT32)DramPolicy->MrcTrainingDataPtr != 0) &&

         ((VOID *)(UINT32)DramPolicy->MrcBootDataPtr     != 0)) {

-      MrcNvData = (MRC_NV_DATA_FRAME *) AllocateZeroPool (sizeof (MRC_NV_DATA_FRAME));

-      MrcParamsHob = (MRC_PARAMS_SAVE_RESTORE*)((UINT32)DramPolicy->MrcTrainingDataPtr);

+      DEBUG ((DEBUG_INFO, "UpdateFspmUpd - NvsBufferPtr\n"));

+      MrcNvData          = (MRC_PARAMS_SAVE_RESTORE *) AllocateZeroPool (sizeof (MRC_PARAMS_SAVE_RESTORE));

+      BootVariableNvData = (BOOT_VARIABLE_NV_DATA *) AllocateZeroPool (sizeof (BOOT_VARIABLE_NV_DATA));

+

+      MrcParamsHob          = (MRC_PARAMS_SAVE_RESTORE*)((UINT32)DramPolicy->MrcTrainingDataPtr);

       BootVariableNvDataHob = (BOOT_VARIABLE_NV_DATA*)((UINT32)DramPolicy->MrcBootDataPtr);

-      CopyMem(&(MrcNvData->MrcParamsSaveRestore), MrcParamsHob, sizeof (MRC_PARAMS_SAVE_RESTORE));

-      CopyMem(&(MrcNvData->BootVariableNvData), BootVariableNvDataHob, sizeof (BOOT_VARIABLE_NV_DATA));

-      FspUpdRgn->FspmArchUpd.NvsBufferPtr = (VOID *)(UINT32)MrcNvData;

+

+      CopyMem(MrcNvData, MrcParamsHob, sizeof (MRC_PARAMS_SAVE_RESTORE));

+      CopyMem(BootVariableNvData, BootVariableNvDataHob, sizeof (BOOT_VARIABLE_NV_DATA));

+      FspUpdRgn->FspmArchUpd.NvsBufferPtr        = (VOID *)(UINT32)MrcNvData;

+      FspUpdRgn->FspmConfig.VariableNvsBufferPtr = (VOID *)(UINT32)BootVariableNvData;

     }

 

   }

diff --git a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPreMem/BoardInitMiscs.c b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPreMem/BoardInitMiscs.c
index 7e0b525608..0c5307811d 100644
--- a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPreMem/BoardInitMiscs.c
+++ b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPreMem/BoardInitMiscs.c
@@ -30,7 +30,8 @@ Mb3UpdateFspmUpd (
   EFI_PLATFORM_INFO_HOB          *PlatformInfo = NULL;

   DRAM_POLICY_PPI                *DramPolicy;

   EFI_STATUS                     Status;

-  MRC_NV_DATA_FRAME              *MrcNvData;

+  MRC_PARAMS_SAVE_RESTORE        *MrcNvData;

+  BOOT_VARIABLE_NV_DATA          *BootVariableNvData;

   MRC_PARAMS_SAVE_RESTORE        *MrcParamsHob;

   BOOT_VARIABLE_NV_DATA          *BootVariableNvDataHob;

 

@@ -74,12 +75,17 @@ Mb3UpdateFspmUpd (
 

     if (((VOID *)(UINT32)DramPolicy->MrcTrainingDataPtr != 0) &&

         ((VOID *)(UINT32)DramPolicy->MrcBootDataPtr     != 0)) {

-      MrcNvData = (MRC_NV_DATA_FRAME *) AllocateZeroPool (sizeof (MRC_NV_DATA_FRAME));

-      MrcParamsHob = (MRC_PARAMS_SAVE_RESTORE*)((UINT32)DramPolicy->MrcTrainingDataPtr);

+      DEBUG ((DEBUG_INFO, "UpdateFspmUpd - NvsBufferPtr\n"));

+      MrcNvData          = (MRC_PARAMS_SAVE_RESTORE *) AllocateZeroPool (sizeof (MRC_PARAMS_SAVE_RESTORE));

+      BootVariableNvData = (BOOT_VARIABLE_NV_DATA *) AllocateZeroPool (sizeof (BOOT_VARIABLE_NV_DATA));

+

+      MrcParamsHob          = (MRC_PARAMS_SAVE_RESTORE*)((UINT32)DramPolicy->MrcTrainingDataPtr);

       BootVariableNvDataHob = (BOOT_VARIABLE_NV_DATA*)((UINT32)DramPolicy->MrcBootDataPtr);

-      CopyMem(&(MrcNvData->MrcParamsSaveRestore), MrcParamsHob, sizeof (MRC_PARAMS_SAVE_RESTORE));

-      CopyMem(&(MrcNvData->BootVariableNvData), BootVariableNvDataHob, sizeof (BOOT_VARIABLE_NV_DATA));

-      FspUpdRgn->FspmArchUpd.NvsBufferPtr = (VOID *)(UINT32)MrcNvData;

+

+      CopyMem(MrcNvData, MrcParamsHob, sizeof (MRC_PARAMS_SAVE_RESTORE));

+      CopyMem(BootVariableNvData, BootVariableNvDataHob, sizeof (BOOT_VARIABLE_NV_DATA));

+      FspUpdRgn->FspmArchUpd.NvsBufferPtr        = (VOID *)(UINT32)MrcNvData;

+      FspUpdRgn->FspmConfig.VariableNvsBufferPtr = (VOID *)(UINT32)BootVariableNvData;

     }

 

   }

diff --git a/Platform/BroxtonPlatformPkg/Common/FspSupport/Library/PeiFspHobProcessLib/FspHobProcessLib.c b/Platform/BroxtonPlatformPkg/Common/FspSupport/Library/PeiFspHobProcessLib/FspHobProcessLib.c
index ec3ea8dcfe..6fe9918eb2 100644
--- a/Platform/BroxtonPlatformPkg/Common/FspSupport/Library/PeiFspHobProcessLib/FspHobProcessLib.c
+++ b/Platform/BroxtonPlatformPkg/Common/FspSupport/Library/PeiFspHobProcessLib/FspHobProcessLib.c
@@ -368,6 +368,8 @@ ProcessFspHobList (
       } else if (CompareGuid(&FspHob.Guid->Name, &gFspNonVolatileStorageHobGuid)) {

         DEBUG ((DEBUG_INFO, "Transfer Memory Config Data HOB!\n"));

         TransferFlag = TRUE;

+      } else if (CompareGuid(&FspHob.Guid->Name, &gFspVariableNvDataHobGuid)) {

+        TransferFlag = TRUE;

       } else if (CompareGuid(&FspHob.Guid->Name, &gEfiBootMediaHobGuid)) {

         TransferFlag = TRUE;

       } else if (CompareGuid(&FspHob.Guid->Name, &gEfiIfwiDnxRequestHobGuid)) {

diff --git a/Platform/BroxtonPlatformPkg/Common/FspSupport/Library/PeiFspHobProcessLib/PeiFspHobProcessLib.inf b/Platform/BroxtonPlatformPkg/Common/FspSupport/Library/PeiFspHobProcessLib/PeiFspHobProcessLib.inf
index 7d4b1b49fd..7e049223e0 100644
--- a/Platform/BroxtonPlatformPkg/Common/FspSupport/Library/PeiFspHobProcessLib/PeiFspHobProcessLib.inf
+++ b/Platform/BroxtonPlatformPkg/Common/FspSupport/Library/PeiFspHobProcessLib/PeiFspHobProcessLib.inf
@@ -1,7 +1,7 @@
 ## @file

 #  Implement Process Fsp Hob.

 #

-#  Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.<BR>

+#  Copyright (c) 2014 - 2017, Intel Corporation. All rights reserved.<BR>

 #

 #  This program and the accompanying materials

 #  are licensed and made available under the terms and conditions of the BSD License

@@ -102,6 +102,7 @@
 

   ## SOMETIMES_CONSUMES ## Guid

   gFspNonVolatileStorageHobGuid

+  gFspVariableNvDataHobGuid

 

   ## SOMETIMES_CONSUMES ## HOB

   ## SOMETIMES_PRODUCES ## HOB

diff --git a/Platform/BroxtonPlatformPkg/Common/SaveMemoryConfigDxe/SaveMemoryConfig.c b/Platform/BroxtonPlatformPkg/Common/SaveMemoryConfigDxe/SaveMemoryConfig.c
index 01a73bda84..58b19c0236 100644
--- a/Platform/BroxtonPlatformPkg/Common/SaveMemoryConfigDxe/SaveMemoryConfig.c
+++ b/Platform/BroxtonPlatformPkg/Common/SaveMemoryConfigDxe/SaveMemoryConfig.c
@@ -2,7 +2,7 @@
   This is the driver that locates the MemoryConfigurationData HOB, if it

   exists, and saves the data to NVRAM.

 

-  Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved.<BR>

+  Copyright (c) 1999 - 2017, Intel Corporation. All rights reserved.<BR>

 

   This program and the accompanying materials

   are licensed and made available under the terms and conditions of the BSD License

@@ -183,10 +183,12 @@ SaveMemoryConfigEntryPoint (
   EFI_STATUS               Status;

   EFI_HANDLE               Handle                       = NULL;

   EFI_HOB_GUID_TYPE        *GuidHob                     = NULL;

+  EFI_HOB_GUID_TYPE        *VariableGuidHob             = NULL;

   EFI_PLATFORM_INFO_HOB    *PlatformInfoHob             = NULL;

   EFI_PLATFORM_SETUP_ID    *BootModeBuffer              = NULL;

   MEM_INFO_PROTOCOL        *MemInfoHobProtocol          = NULL;

-  MRC_NV_DATA_FRAME        *MemoryConfigHobData         = NULL;

+  MRC_PARAMS_SAVE_RESTORE  *MemoryConfigHobData         = NULL;

+  BOOT_VARIABLE_NV_DATA    *VariableNvHobData           = NULL;

   UINTN                    MemoryConfigHobDataSize      = 0;

   UINT8                    Channel                      = 0;

   UINT8                    Slot                         = 0;

@@ -239,6 +241,14 @@ SaveMemoryConfigEntryPoint (
     return EFI_NOT_FOUND;

   }

 

+  if ((VariableGuidHob = GetFirstGuidHob (&gFspVariableNvDataHobGuid)) != NULL) {

+    VariableNvHobData = GET_GUID_HOB_DATA(VariableGuidHob);

+  }

+

+  if (VariableNvHobData == NULL) {

+    return EFI_NOT_FOUND;

+  }

+

   //

   // Populate and install the MemInfoHobProtocol

   //

@@ -249,21 +259,21 @@ SaveMemoryConfigEntryPoint (
 

     for (Channel = 0; Channel < CH_NUM; Channel++) {

       for (Slot = 0; Slot < DIMM_NUM; Slot++) {

-        MemInfoHobProtocol->MemInfoData.memSize += MemoryConfigHobData->MrcParamsSaveRestore.Channel[Channel].SlotMem[Slot];

-        MemInfoHobProtocol->MemInfoData.dimmSize[Slot + (Channel * DIMM_NUM)] = MemoryConfigHobData->MrcParamsSaveRestore.Channel[Channel].SlotMem[Slot];

-        MemInfoHobProtocol->MemInfoData.DimmPresent[Slot + (Channel * DIMM_NUM)] = MemoryConfigHobData->MrcParamsSaveRestore.Channel[Channel].DimmPresent[Slot];

+        MemInfoHobProtocol->MemInfoData.memSize += MemoryConfigHobData->Channel[Channel].SlotMem[Slot];

+        MemInfoHobProtocol->MemInfoData.dimmSize[Slot + (Channel * DIMM_NUM)] = MemoryConfigHobData->Channel[Channel].SlotMem[Slot];

+        MemInfoHobProtocol->MemInfoData.DimmPresent[Slot + (Channel * DIMM_NUM)] = MemoryConfigHobData->Channel[Channel].DimmPresent[Slot];

         if (MemInfoHobProtocol->MemInfoData.DimmPresent[Slot + (Channel * DIMM_NUM)]) {

-          MemInfoHobProtocol->MemInfoData.DimmsSpdData[Slot + (Channel * DIMM_NUM)] = MemoryConfigHobData->MrcParamsSaveRestore.Channel[Channel].SpdData[Slot].Buffer;

+          MemInfoHobProtocol->MemInfoData.DimmsSpdData[Slot + (Channel * DIMM_NUM)] = MemoryConfigHobData->Channel[Channel].SpdData[Slot].Buffer;

         } else {

           MemInfoHobProtocol->MemInfoData.DimmsSpdData[Slot + (Channel * DIMM_NUM)] = NULL;

         }

       }

     }

 

-    MemInfoHobProtocol->MemInfoData.ddrFreq   = MemoryConfigHobData->MrcParamsSaveRestore.CurrentFrequency;

-    MemInfoHobProtocol->MemInfoData.memSize   = MemoryConfigHobData->MrcParamsSaveRestore.SystemMemorySize;

-    MemInfoHobProtocol->MemInfoData.ddrType   = MemoryConfigHobData->MrcParamsSaveRestore.Channel[0].DramType;

-    MemInfoHobProtocol->MemInfoData.BusWidth  = MemoryConfigHobData->MrcParamsSaveRestore.BusWidth;

+    MemInfoHobProtocol->MemInfoData.ddrFreq   = MemoryConfigHobData->CurrentFrequency;

+    MemInfoHobProtocol->MemInfoData.memSize   = MemoryConfigHobData->SystemMemorySize;

+    MemInfoHobProtocol->MemInfoData.ddrType   = MemoryConfigHobData->Channel[0].DramType;

+    MemInfoHobProtocol->MemInfoData.BusWidth  = MemoryConfigHobData->BusWidth;

 

     DEBUG ((EFI_D_INFO, "SaveMemoryConfigEntryPoint - Freq:0x%x\n", MemInfoHobProtocol->MemInfoData.ddrFreq));

     DEBUG ((EFI_D_INFO, "SaveMemoryConfigEntryPoint - Memsize:0x%x\n", MemInfoHobProtocol->MemInfoData.memSize));

@@ -276,13 +286,13 @@ SaveMemoryConfigEntryPoint (
                     );

   }

 

-  Status = SaveMrcData (mMemoryConfigVariable, (UINT8 *) &(MemoryConfigHobData->MrcParamsSaveRestore), sizeof (MRC_PARAMS_SAVE_RESTORE));

-  if (EFI_ERROR(Status)) {

+  Status = SaveMrcData(mMemoryConfigVariable, (UINT8 *) MemoryConfigHobData, sizeof(MRC_PARAMS_SAVE_RESTORE));

+  if (EFI_ERROR(Status)){

     return Status;

   }

 

-  Status = SaveMrcData (mMemoryBootVariable, (UINT8 *) &(MemoryConfigHobData->BootVariableNvData), sizeof (BOOT_VARIABLE_NV_DATA));

-  if (EFI_ERROR (Status)) {

+  Status = SaveMrcData(mMemoryBootVariable, (UINT8 *) VariableNvHobData, sizeof(BOOT_VARIABLE_NV_DATA));

+  if (EFI_ERROR(Status)){

     return Status;

   }

 

diff --git a/Platform/BroxtonPlatformPkg/Common/SaveMemoryConfigDxe/SaveMemoryConfigDxe.inf b/Platform/BroxtonPlatformPkg/Common/SaveMemoryConfigDxe/SaveMemoryConfigDxe.inf
index 8c1573f060..919f16779a 100644
--- a/Platform/BroxtonPlatformPkg/Common/SaveMemoryConfigDxe/SaveMemoryConfigDxe.inf
+++ b/Platform/BroxtonPlatformPkg/Common/SaveMemoryConfigDxe/SaveMemoryConfigDxe.inf
@@ -1,7 +1,7 @@
 ## @file

 #  Component description for driver that locates the MemoryConfigurationData HOB, which saves the data to NVRAM.

 #

-#  Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved.<BR>

+#  Copyright (c) 1999 - 2017, Intel Corporation. All rights reserved.<BR>

 #

 #  This program and the accompanying materials

 #  are licensed and made available under the terms and conditions of the BSD License

@@ -51,6 +51,7 @@
   gEfiPlatformBootModeGuid

   gEfiBxtVariableGuid

   gFspNonVolatileStorageHobGuid  ##CONSUMES

+  gFspVariableNvDataHobGuid

 

 [Depex]

   gEfiVariableArchProtocolGuid   AND

diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/BroxtonSiPkg.dec b/Silicon/BroxtonSoC/BroxtonSiPkg/BroxtonSiPkg.dec
index da728e8886..f17a3e0e55 100644
--- a/Silicon/BroxtonSoC/BroxtonSiPkg/BroxtonSiPkg.dec
+++ b/Silicon/BroxtonSoC/BroxtonSiPkg/BroxtonSiPkg.dec
@@ -161,6 +161,7 @@
   gCsePrimaryIndexFileDataHobGuid         = { 0x8d97b52d, 0x2805, 0x46a1, { 0x97, 0xd4, 0x07, 0xd4, 0x82, 0x7a, 0xa1, 0x5e}}

   gFdoModeEnabledHobGuid                  = { 0x7e4b2acb, 0x7391, 0x408f, { 0xb1, 0x43, 0x3a, 0x0b, 0x07, 0xc6, 0xe1, 0x65}}

   gEfiMemoryConfigVariableGuid            = { 0xb0767cbc, 0x4705, 0x4d35, { 0x88, 0x66, 0x17, 0xa9, 0xb8, 0x5e, 0x38, 0x43}}

+  gFspVariableNvDataHobGuid               = { 0xa034147d, 0x690c, 0x4154, { 0x8d, 0xe6, 0xc0, 0x44, 0x64, 0x1d, 0xe9, 0x42}}

   #

   # Reset type GUID for S5 charging

   #

diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/ResetVector/Vtf0/Ia32/InitNEM.asm b/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/ResetVector/Vtf0/Ia32/InitNEM.asm
index 12d274676c..905e615a2c 100644
--- a/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/ResetVector/Vtf0/Ia32/InitNEM.asm
+++ b/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/ResetVector/Vtf0/Ia32/InitNEM.asm
@@ -183,7 +183,7 @@ istruc HobStruc
     dd 0x00100000   ; .CarSize

     dd 0xFFF00000   ; .IBBSource  = Not used

     dd 0xFEF45000   ; .IBBBase    = .CarBase

-    dd 0x0008D000   ; .IBBSize    = size of (FVIBBM.fv+FSP_M.fv) = BLD_IBBM_SIZE + FSP_IBBM_SIZE = 0x8D000

+    dd 0x0008E000   ; .IBBSize    = size of (FVIBBM.fv+FSP_M.fv) = BLD_IBBM_SIZE + FSP_IBBM_SIZE = 0x8D000

     dd 0xFFFFF000   ; .IBBLSource = 0x100000000 - .IBBLSize = PcdFlashFvIBBLBase

     dd 0xFEF40000   ; .IBBLBase   = .IBBBase + .IBBSize

     dd 0x00001000   ; .IBBLSize   = PcdFlashFvIBBLSize = FLASH_REGION_FV_IBBL_SIZE in .fdf

diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/MemoryInit/Mmrc/ProjectData/BXTP/Include/MmrcProjectDefinitionsGenerated.h b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/MemoryInit/Mmrc/ProjectData/BXTP/Include/MmrcProjectDefinitionsGenerated.h
index b0b6a01376..b89c0d075a 100644
--- a/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/MemoryInit/Mmrc/ProjectData/BXTP/Include/MmrcProjectDefinitionsGenerated.h
+++ b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/MemoryInit/Mmrc/ProjectData/BXTP/Include/MmrcProjectDefinitionsGenerated.h
@@ -15,7 +15,7 @@
   here. This file needs to be included by most MMRC components,

   including Mmrc.h.

 

-  Copyright (c) 2005 - 2016, Intel Corporation. All rights reserved.<BR>

+  Copyright (c) 2005 - 2017, Intel Corporation. All rights reserved.<BR>

 

   This program and the accompanying materials

   are licensed and made available under the terms and conditions of the BSD License

@@ -97,7 +97,7 @@
 //

 // Minor Version

 //

-#define VERSION_MINOR                                      0

+#define VERSION_MINOR                                      20

 //

 // Print MRC functions as they execute

 //

@@ -777,10 +777,6 @@
 //

 //

 //

-#define LDO_TRAINING                                       0

-//

-//

-//

 #define CTLE_MIN                                           0

 //

 //

diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/MemoryInit/Mmrc/ProjectIndependent/Include/MmrcData.h b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/MemoryInit/Mmrc/ProjectIndependent/Include/MmrcData.h
index eb0f973a29..5e906fbd81 100644
--- a/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/MemoryInit/Mmrc/ProjectIndependent/Include/MmrcData.h
+++ b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/MemoryInit/Mmrc/ProjectIndependent/Include/MmrcData.h
@@ -22,16 +22,9 @@
 #include <stdio.h>

 #endif

 

-#if USE_64_BIT_VARIABLES

-#define UINTX UINT64

-#else

-#define UINTX UINT32

-#endif

-typedef UINT32           MMRC_STATUS;

-

-//

-// MRC version description.

-//

+///

+/// MRC version description.

+///

 typedef union {

   struct{

     UINT8      Major;             ///< Major version number

@@ -179,8 +172,8 @@ typedef struct {
 //

 typedef struct {

   UINT16                    ScramblerSeed[MAX_CHANNELS];

-  UINT32                    SaMemCfgCrc;

-  UINT32                    MrcParamsSaveRestoreCrc;

+  UINT16                    LP4_MR4VALUE[MAX_CHANNELS];

+  UINT32                    BootVariableNvDataCrc;

 } BOOT_VARIABLE_NV_DATA;

 

 typedef struct {

@@ -233,7 +226,6 @@ typedef struct {
   UINT8                     ASR_Supported;

   UINT8                     OdtHigh;

   UINT16                    LP4_MR0VALUE;

-  UINT16                    LP4_MR4VALUE;

   CHANNEL_OPTION            ChOption;

 } CHANNEL;

 

@@ -254,6 +246,8 @@ typedef struct {
   UINT32        MuxcodeNv[MaxFrequencyIndex];

   BOOLEAN       SetupMaxPiDone[MaxFrequencyIndex];

   UINT32        DataSize;

+  UINT32        SaMemCfgCrc;

+  UINT32        MrcParamsSaveRestoreCrc;

 } MRC_PARAMS_SAVE_RESTORE;

 

 //