diff options
| author | Yao, Jiewen <jiewen.yao@intel.com> | 2015-11-30 19:57:45 +0000 |
|---|---|---|
| committer | Hao Wu <hao.a.wu@intel.com> | 2016-02-25 09:13:25 +0800 |
| commit | f48825541ade03c576ecc2357b5fc9ca2db83e71 (patch) | |
| tree | bc8d4973ee35d06b40ba70244e36dde8c8c9999e | |
| parent | cd5e29959f602cddd8e4b42b207f2101b6e92e89 (diff) | |
| download | edk2-platforms-f48825541ade03c576ecc2357b5fc9ca2db83e71.tar.xz | |
UefiCpuPkg/PiSmmCpu: Always set WP in CR0
So that we can use write-protection for code later.
It is REPOST.
It includes suggestion from Michael Kinney <michael.d.kinney@intel.com>:
- "For IA32 assembly, can we combine into a single OR instruction that
sets both page enable and WP?"
- "For X64, does it make sense to use single OR instruction instead of 2
BTS instructions as well?"
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: "Yao, Jiewen" <jiewen.yao@intel.com>
Suggested-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
Cc: "Fan, Jeff" <jeff.fan@intel.com>
Cc: "Kinney, Michael D" <michael.d.kinney@intel.com>
Cc: "Laszlo Ersek" <lersek@redhat.com>
Cc: "Paolo Bonzini" <pbonzini@redhat.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19068 6f19259b-4bc3-4df7-8a09-765794883524
(cherry picked from commit 53ba3fb8aaf91df4a65244480deb6fa60968c146)
| -rw-r--r-- | UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.S | 2 | ||||
| -rw-r--r-- | UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.asm | 2 | ||||
| -rw-r--r-- | UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.S | 2 | ||||
| -rw-r--r-- | UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.asm | 2 |
4 files changed, 4 insertions, 4 deletions
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.S b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.S index fbaa0725f0..ec5b9a0b04 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.S +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.S @@ -123,7 +123,7 @@ L11: L12: # as cr4.PGE is not set here, refresh cr3
movl %eax, %cr4 # in PreModifyMtrrs() to flush TLB.
movl %cr0, %ebx
- orl $0x080000000, %ebx # enable paging
+ orl $0x080010000, %ebx # enable paging + WP
movl %ebx, %cr0
leal DSC_OFFSET(%edi),%ebx
movw DSC_DS(%ebx),%ax
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.asm b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.asm index 8a12927300..ac1a9b48dd 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.asm +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.asm @@ -129,7 +129,7 @@ gSmiCr3 DD ? @@: ; as cr4.PGE is not set here, refresh cr3
mov cr4, eax ; in PreModifyMtrrs() to flush TLB.
mov ebx, cr0
- or ebx, 080000000h ; enable paging
+ or ebx, 080010000h ; enable paging + WP
mov cr0, ebx
lea ebx, [edi + DSC_OFFSET]
mov ax, [ebx + DSC_DS]
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.S b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.S index b488b74b70..7e9ac58cb2 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.S +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.S @@ -144,7 +144,7 @@ Base: orb $1,%ah
wrmsr
movq %cr0, %rbx
- btsl $31, %ebx
+ orl $0x080010000, %ebx # enable paging + WP
movq %rbx, %cr0
retf
LongMode: # long mode (64-bit code) starts here
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.asm b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.asm index 4f5c03c5cf..094cf2c3da 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.asm +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.asm @@ -140,7 +140,7 @@ Base: or ah, 1
wrmsr
mov rbx, cr0
- bts ebx, 31
+ or ebx, 080010000h ; enable paging + WP
mov cr0, rbx
retf
@LongMode: ; long mode (64-bit code) starts here
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