diff options
| author | oliviermartin <oliviermartin@6f19259b-4bc3-4df7-8a09-765794883524> | 2011-09-27 16:26:03 +0000 |
|---|---|---|
| committer | oliviermartin <oliviermartin@6f19259b-4bc3-4df7-8a09-765794883524> | 2011-09-27 16:26:03 +0000 |
| commit | 3127615b4d6ce75b5c22780847a83124c5f2e552 (patch) | |
| tree | f9752e3610116f8b5380f48540823826fed8c83c /ArmPkg/Drivers/ArmCpuLib/ArmCortexA9Lib/ArmCortexA9Lib.c | |
| parent | aa84fef5fe4579ef21b223cf68428bf55b0f4f43 (diff) | |
| download | edk2-platforms-3127615b4d6ce75b5c22780847a83124c5f2e552.tar.xz | |
ArmPkg: Introduce ArmCpuLib to abstract ARM Cpu specific initialization (2)
Missed new files.
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@12450 6f19259b-4bc3-4df7-8a09-765794883524
Diffstat (limited to 'ArmPkg/Drivers/ArmCpuLib/ArmCortexA9Lib/ArmCortexA9Lib.c')
| -rw-r--r-- | ArmPkg/Drivers/ArmCpuLib/ArmCortexA9Lib/ArmCortexA9Lib.c | 102 |
1 files changed, 102 insertions, 0 deletions
diff --git a/ArmPkg/Drivers/ArmCpuLib/ArmCortexA9Lib/ArmCortexA9Lib.c b/ArmPkg/Drivers/ArmCpuLib/ArmCortexA9Lib/ArmCortexA9Lib.c new file mode 100644 index 0000000000..7c5c3ee6a9 --- /dev/null +++ b/ArmPkg/Drivers/ArmCpuLib/ArmCortexA9Lib/ArmCortexA9Lib.c @@ -0,0 +1,102 @@ +/** @file
+
+ Copyright (c) 2011, ARM Limited. All rights reserved.
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Base.h>
+#include <Library/ArmLib.h>
+#include <Library/ArmCpuLib.h>
+#include <Library/ArmGicLib.h>
+#include <Library/IoLib.h>
+#include <Library/PcdLib.h>
+
+#include <Chipset/ArmCortexA9.h>
+
+VOID
+ArmCpuSynchronizeSignal (
+ IN ARM_CPU_SYNCHRONIZE_EVENT Event
+ )
+{
+ if (Event == ARM_CPU_EVENT_BOOT_MEM_INIT) {
+ // Do nothing, Cortex A9 secondary cores are waiting for the SCU to be
+ // enabled (done by ArmCpuSetup()) as a way to know when the Init Boot
+ // Mem as been initialized
+ } else {
+ // Send SGI to all Secondary core to wake them up from WFI state.
+ ArmGicSendSgiTo (PcdGet32(PcdGicDistributorBase), ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E);
+ }
+}
+
+VOID
+CArmCpuSynchronizeWait (
+ IN ARM_CPU_SYNCHRONIZE_EVENT Event
+ )
+{
+ // Waiting for the SGI from the primary core
+ ArmCallWFI ();
+
+ // Acknowledge the interrupt and send End of Interrupt signal.
+ ArmGicAcknowledgeSgiFrom (PcdGet32(PcdGicInterruptInterfaceBase), PRIMARY_CORE_ID);
+}
+
+VOID
+ArmEnableScu (
+ VOID
+ )
+{
+ INTN ScuBase;
+
+ ScuBase = ArmGetScuBaseAddress();
+
+ // Invalidate all: write -1 to SCU Invalidate All register
+ MmioWrite32(ScuBase + A9_SCU_INVALL_OFFSET, 0xffffffff);
+ // Enable SCU
+ MmioWrite32(ScuBase + A9_SCU_CONTROL_OFFSET, 0x1);
+}
+
+VOID
+ArmCpuSetup (
+ IN UINTN MpId
+ )
+{
+ // Enable SWP instructions
+ ArmEnableSWPInstruction ();
+
+ // Enable program flow prediction, if supported.
+ ArmEnableBranchPrediction ();
+
+ // If MPCore then Enable the SCU
+ if (ArmIsMpCore()) {
+ ArmEnableScu ();
+ }
+}
+
+
+VOID
+ArmCpuSetupSmpNonSecure (
+ IN UINTN MpId
+ )
+{
+ INTN ScuBase;
+
+ ArmSetAuxCrBit (A9_FEATURE_SMP);
+
+ // Make the SCU accessible in Non Secure world
+ if (IS_PRIMARY_CORE(MpId)) {
+ ScuBase = ArmGetScuBaseAddress();
+
+ // Allow NS access to SCU register
+ MmioOr32 (ScuBase + A9_SCU_SACR_OFFSET, 0xf);
+ // Allow NS access to Private Peripherals
+ MmioOr32 (ScuBase + A9_SCU_SSACR_OFFSET, 0xfff);
+ }
+}
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