diff options
author | andrewfish <andrewfish@6f19259b-4bc3-4df7-8a09-765794883524> | 2011-02-02 22:52:07 +0000 |
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committer | andrewfish <andrewfish@6f19259b-4bc3-4df7-8a09-765794883524> | 2011-02-02 22:52:07 +0000 |
commit | 58b5d037b4627460242c9333860faabf6115069e (patch) | |
tree | 17a4f5527bd2fa5ae655916cd1acfd704d4d0a00 /ArmPkg/Drivers/CpuDxe/Mmu.c | |
parent | 6111eb855592438cc6f2da44e5887f8065bcef6e (diff) | |
download | edk2-platforms-58b5d037b4627460242c9333860faabf6115069e.tar.xz |
Remove tabs from all text files in the package.
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@11295 6f19259b-4bc3-4df7-8a09-765794883524
Diffstat (limited to 'ArmPkg/Drivers/CpuDxe/Mmu.c')
-rw-r--r-- | ArmPkg/Drivers/CpuDxe/Mmu.c | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/ArmPkg/Drivers/CpuDxe/Mmu.c b/ArmPkg/Drivers/CpuDxe/Mmu.c index d7ea0eb551..0b86b8bc98 100644 --- a/ArmPkg/Drivers/CpuDxe/Mmu.c +++ b/ArmPkg/Drivers/CpuDxe/Mmu.c @@ -338,11 +338,11 @@ UpdatePageEntries ( // modify cacheability attributes
EntryMask |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK;
if (FeaturePcdGet(PcdEfiUncachedMemoryToStronglyOrdered)) {
- // map to strongly ordered
- EntryValue |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_STRONGLY_ORDERED; // TEX[2:0] = 0, C=0, B=0
+\s\s\s\s // map to strongly ordered
+\s\s\s\s EntryValue |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_STRONGLY_ORDERED; // TEX[2:0] = 0, C=0, B=0
} else {
- // map to normal non-cachable
- EntryValue |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_NON_CACHEABLE; // TEX [2:0]= 001 = 0x2, B=0, C=0
+ \s\s // map to normal non-cachable
+ \s\s EntryValue |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_NON_CACHEABLE; // TEX [2:0]= 001 = 0x2, B=0, C=0
}
break;
@@ -486,11 +486,11 @@ UpdateSectionEntries ( // modify cacheability attributes
EntryMask |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK;
if (FeaturePcdGet(PcdEfiUncachedMemoryToStronglyOrdered)) {
- // map to strongly ordered
- EntryValue |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_STRONGLY_ORDERED; // TEX[2:0] = 0, C=0, B=0
+\s\s\s\s // map to strongly ordered
+\s\s\s\s EntryValue |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_STRONGLY_ORDERED; // TEX[2:0] = 0, C=0, B=0
} else {
- // map to normal non-cachable
- EntryValue |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_CACHEABLE; // TEX [2:0]= 001 = 0x2, B=0, C=0
+ \s\s // map to normal non-cachable
+ \s\s EntryValue |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_CACHEABLE; // TEX [2:0]= 001 = 0x2, B=0, C=0
}
break;
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