diff options
| author | Ard Biesheuvel <ard.biesheuvel@linaro.org> | 2017-02-24 09:58:38 +0000 |
|---|---|---|
| committer | Ard Biesheuvel <ard.biesheuvel@linaro.org> | 2017-02-28 14:59:50 +0000 |
| commit | 3b44bb552781777d55661d3c5750bc85c9c17150 (patch) | |
| tree | 669f5523766e461816e176f836241c348e417971 /ArmPkg/Drivers | |
| parent | c325e41585e374d40fb36b434e61a1ab0fca5b1c (diff) | |
| download | edk2-platforms-3b44bb552781777d55661d3c5750bc85c9c17150.tar.xz | |
ArmPkg/CpuDxe: ignore attribute changes during SyncCacheConfig()
To prevent the initial MMU->GCD memory space map synchronization from
stripping permissions attributes [which we cannot use in the GCD memory
space map, unfortunately], implement the same approach as x86, and ignore
SetMemoryAttributes() calls during the time SyncCacheConfig() is in
progress. This is a horrible hack, but is currently the only way we can
implement strict permissions on arbitrary memory regions [as opposed to
PE/COFF text/data sections only]
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Diffstat (limited to 'ArmPkg/Drivers')
| -rw-r--r-- | ArmPkg/Drivers/CpuDxe/CpuDxe.c | 3 | ||||
| -rw-r--r-- | ArmPkg/Drivers/CpuDxe/CpuDxe.h | 1 | ||||
| -rw-r--r-- | ArmPkg/Drivers/CpuDxe/CpuMmuCommon.c | 4 |
3 files changed, 8 insertions, 0 deletions
diff --git a/ArmPkg/Drivers/CpuDxe/CpuDxe.c b/ArmPkg/Drivers/CpuDxe/CpuDxe.c index 5aa5b87414..5e923d45b7 100644 --- a/ArmPkg/Drivers/CpuDxe/CpuDxe.c +++ b/ArmPkg/Drivers/CpuDxe/CpuDxe.c @@ -17,6 +17,7 @@ #include <Guid/IdleLoopEvent.h>
+BOOLEAN mIsFlushingGCD;
/**
This function flushes the range of addresses from Start to Start+Length
@@ -261,7 +262,9 @@ CpuDxeInitialize ( // and that calls EFI_CPU_ARCH_PROTOCOL.SetMemoryAttributes, so this code needs to go
// after the protocol is installed
//
+ mIsFlushingGCD = TRUE;
SyncCacheConfig (&mCpu);
+ mIsFlushingGCD = FALSE;
// If the platform is a MPCore system then install the Configuration Table describing the
// secondary core states
diff --git a/ArmPkg/Drivers/CpuDxe/CpuDxe.h b/ArmPkg/Drivers/CpuDxe/CpuDxe.h index a00fc30643..a46db8d257 100644 --- a/ArmPkg/Drivers/CpuDxe/CpuDxe.h +++ b/ArmPkg/Drivers/CpuDxe/CpuDxe.h @@ -37,6 +37,7 @@ #include <Protocol/DebugSupportPeriodicCallback.h>
#include <Protocol/LoadedImage.h>
+extern BOOLEAN mIsFlushingGCD;
/**
This function registers and enables the handler specified by InterruptHandler for a processor
diff --git a/ArmPkg/Drivers/CpuDxe/CpuMmuCommon.c b/ArmPkg/Drivers/CpuDxe/CpuMmuCommon.c index ebe593d1c3..0f36a05840 100644 --- a/ArmPkg/Drivers/CpuDxe/CpuMmuCommon.c +++ b/ArmPkg/Drivers/CpuDxe/CpuMmuCommon.c @@ -188,6 +188,10 @@ CpuSetMemoryAttributes ( UINTN RegionLength;
UINTN RegionArmAttributes;
+ if (mIsFlushingGCD) {
+ return EFI_SUCCESS;
+ }
+
if ((BaseAddress & (SIZE_4KB - 1)) != 0) {
// Minimum granularity is SIZE_4KB (4KB on ARM)
DEBUG ((EFI_D_PAGE, "CpuSetMemoryAttributes(%lx, %lx, %lx): Minimum ganularity is SIZE_4KB\n", BaseAddress, Length, EfiAttributes));
|