ArmPkg/ArmCpuLib: Replaced complex functions ArmCpuSynchronizeWait & ArmCpuSynchronizeSignal by sev & wfe

Previsouly the synchronization of MpCore was using the SGI (Software
Generated Interrupt) to synchronize MpCore during the early boot.
This commit replaced this mechanism by the more appropriate SEV/WFE
instructions (Send/Wait Event instructions).
That also eases the port to a new cpu/platform.

Signed-off-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13249 6f19259b-4bc3-4df7-8a09-765794883524

9 files changed, 10 insertions, 235 deletions

diff --git a/ArmPkg/Drivers/ArmCpuLib/Arm11MpCoreLib/Arm11Lib.c b/ArmPkg/Drivers/ArmCpuLib/Arm11MpCoreLib/Arm11Lib.c
index 2e285d54c7..a08b7b1aee 100644
--- a/ArmPkg/Drivers/ArmCpuLib/Arm11MpCoreLib/Arm11Lib.c
+++ b/ArmPkg/Drivers/ArmCpuLib/Arm11MpCoreLib/Arm11Lib.c
@@ -1,6 +1,6 @@
 /** @file

 

-  Copyright (c) 2011, ARM Limited. All rights reserved.

+  Copyright (c) 2011-2012, ARM Limited. All rights reserved.

 

   This program and the accompanying materials

   are licensed and made available under the terms and conditions of the BSD License

@@ -15,76 +15,15 @@
 #include <Base.h>

 #include <Library/ArmLib.h>

 #include <Library/ArmCpuLib.h>

-#include <Library/ArmGicLib.h>

 #include <Library/IoLib.h>

 #include <Library/PcdLib.h>

 

 VOID

-ArmCpuSynchronizeSignal (

-  IN ARM_CPU_SYNCHRONIZE_EVENT   Event

-  )

-{

-  if (Event == ARM_CPU_EVENT_BOOT_MEM_INIT) {

-    // Do nothing, Cortex A9 secondary cores are waiting for the SCU to be

-    // enabled (done by ArmCpuSetup()) as a way to know when the Init Boot

-    // Mem as been initialized

-  } else {

-    // Send SGI to all Secondary core to wake them up from WFI state.

-    ArmGicSendSgiTo (PcdGet32(PcdGicDistributorBase), ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E);

-  }

-}

-

-VOID

-CArmCpuSynchronizeWait (

-  IN ARM_CPU_SYNCHRONIZE_EVENT   Event

-  )

-{

-  // Waiting for the SGI from the primary core

-  ArmCallWFI ();

-

-  // Acknowledge the interrupt and send End of Interrupt signal.

-  ArmGicAcknowledgeSgiFrom (PcdGet32(PcdGicInterruptInterfaceBase), PRIMARY_CORE_ID);

-}

-

-#if 0

-VOID

-ArmEnableScu (

-  VOID

-  )

-{

-  INTN          ScuBase;

-

-  ScuBase = ArmGetScuBaseAddress();

-

-  // Invalidate all: write -1 to SCU Invalidate All register

-  MmioWrite32(ScuBase + A9_SCU_INVALL_OFFSET, 0xffffffff);

-  // Enable SCU

-  MmioWrite32(ScuBase + A9_SCU_CONTROL_OFFSET, 0x1);

-}

-#endif

-

-VOID

 ArmCpuSetup (

   IN  UINTN         MpId

   )

 {

-  /*AMP mode and SMP mode

-

-   By default, the processor is in AMP mode (bit 5 reset to 0). To prevent coherent data corruption the sequence to turn on MP11 CPUs in SMP mode is:

-

-   1.Write the SCU register to change CPU mode.

-   2.Disable interrupts.

-   3.Clean and invalidate all the D-cache.

-   4.Write SMP/nAMP bit as 1.

-   5.Enable interrupts.

-

-  Source: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0360e/BIHHFGEC.html

-  */

-

-  // If MPCore then Enable the SCU

-  if (ArmIsMpCore()) {

-    //ArmEnableScu ();

-  }

+  ASSERT(0); //TODO: Implement me

 }

 

 

@@ -93,20 +32,6 @@ ArmCpuSetupSmpNonSecure (
   IN  UINTN         MpId

   )

 {

-#if 0

-  INTN          ScuBase;

-

-  ArmSetAuxCrBit (A9_FEATURE_SMP);

-

-  // Make the SCU accessible in Non Secure world

-  if (IS_PRIMARY_CORE(MpId)) {

-    ScuBase = ArmGetScuBaseAddress();

-

-    // Allow NS access to SCU register

-    MmioOr32 (ScuBase + A9_SCU_SACR_OFFSET, 0xf);

-    // Allow NS access to Private Peripherals

-    MmioOr32 (ScuBase + A9_SCU_SSACR_OFFSET, 0xfff);

-  }

-#endif

+  ASSERT(0); //TODO: Implement me

 }

 

diff --git a/ArmPkg/Drivers/ArmCpuLib/Arm11MpCoreLib/Arm11MpCoreLib.inf b/ArmPkg/Drivers/ArmCpuLib/Arm11MpCoreLib/Arm11MpCoreLib.inf
index 2b9621c6ec..f7ecfb0900 100644
--- a/ArmPkg/Drivers/ArmCpuLib/Arm11MpCoreLib/Arm11MpCoreLib.inf
+++ b/ArmPkg/Drivers/ArmCpuLib/Arm11MpCoreLib/Arm11MpCoreLib.inf
@@ -1,5 +1,5 @@
 #/* @file

-#  Copyright (c) 2011, ARM Limited. All rights reserved.

+#  Copyright (c) 2011-2012, ARM Limited. All rights reserved.

 #  

 #  This program and the accompanying materials                          

 #  are licensed and made available under the terms and conditions of the BSD License         

@@ -25,18 +25,8 @@
 

 [LibraryClasses]

   ArmLib

-  ArmGicSecLib

   IoLib

   PcdLib

 

 [Sources.common]

   Arm11Lib.c

-  Arm11Helper.asm     | RVCT

-  Arm11Helper.S       | GCC

-

-[FixedPcd]

-  gArmTokenSpaceGuid.PcdArmPrimaryCoreMask

-  gArmTokenSpaceGuid.PcdArmPrimaryCore

-

-  gArmTokenSpaceGuid.PcdGicDistributorBase

-  gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase

diff --git a/ArmPkg/Drivers/ArmCpuLib/ArmCortexA15Lib/ArmCortexA15Lib.c b/ArmPkg/Drivers/ArmCpuLib/ArmCortexA15Lib/ArmCortexA15Lib.c
index a3af3a8c55..9b64d662d9 100644
--- a/ArmPkg/Drivers/ArmCpuLib/ArmCortexA15Lib/ArmCortexA15Lib.c
+++ b/ArmPkg/Drivers/ArmCpuLib/ArmCortexA15Lib/ArmCortexA15Lib.c
@@ -1,6 +1,6 @@
 /** @file

 

-  Copyright (c) 2011, ARM Limited. All rights reserved.

+  Copyright (c) 2011-2012, ARM Limited. All rights reserved.

 

   This program and the accompanying materials

   are licensed and made available under the terms and conditions of the BSD License

@@ -15,7 +15,6 @@
 #include <Base.h>

 #include <Library/ArmLib.h>

 #include <Library/ArmCpuLib.h>

-#include <Library/ArmGicLib.h>

 #include <Library/ArmV7ArchTimerLib.h>

 #include <Library/DebugLib.h>

 #include <Library/IoLib.h>

@@ -24,33 +23,6 @@
 #include <Chipset/ArmV7.h>

 

 VOID

-ArmCpuSynchronizeSignal (

-  IN ARM_CPU_SYNCHRONIZE_EVENT   Event

-  )

-{

-  if (Event == ARM_CPU_EVENT_BOOT_MEM_INIT) {

-    // Do nothing, Cortex A15 secondary cores are waiting for the GIC Distributor

-    // to be enabled (done by the Sec module itself) as a way to know when the Init Boot

-    // Mem as been initialized

-  } else {

-    // Send SGI to all Secondary core to wake them up from WFI state.

-    ArmGicSendSgiTo (PcdGet32(PcdGicDistributorBase), ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E);

-  }

-}

-

-VOID

-CArmCpuSynchronizeWait (

-  IN ARM_CPU_SYNCHRONIZE_EVENT   Event

-  )

-{

-  // Waiting for the SGI from the primary core

-  ArmCallWFI ();

-

-  // Acknowledge the interrupt and send End of Interrupt signal.

-  ArmGicAcknowledgeSgiFrom (PcdGet32(PcdGicInterruptInterfaceBase), PRIMARY_CORE_ID);

-}

-

-VOID

 ArmCpuSetup (

   IN  UINTN         MpId

   )

diff --git a/ArmPkg/Drivers/ArmCpuLib/ArmCortexA15Lib/ArmCortexA15Lib.inf b/ArmPkg/Drivers/ArmCpuLib/ArmCortexA15Lib/ArmCortexA15Lib.inf
index 69ecfb109c..bcf7f6bfba 100644
--- a/ArmPkg/Drivers/ArmCpuLib/ArmCortexA15Lib/ArmCortexA15Lib.inf
+++ b/ArmPkg/Drivers/ArmCpuLib/ArmCortexA15Lib/ArmCortexA15Lib.inf
@@ -1,5 +1,5 @@
 #/* @file

-#  Copyright (c) 2011, ARM Limited. All rights reserved.

+#  Copyright (c) 2011-2012, ARM Limited. All rights reserved.

 #  

 #  This program and the accompanying materials                          

 #  are licensed and made available under the terms and conditions of the BSD License         

@@ -25,14 +25,11 @@
 

 [LibraryClasses]

   ArmLib

-  ArmGicSecLib

   IoLib

   PcdLib

 

 [Sources.common]

   ArmCortexA15Lib.c

-  ArmCortexA15Helper.asm     | RVCT

-  ArmCortexA15Helper.S       | GCC

 

 [FeaturePcd]

 

@@ -40,7 +37,4 @@
   gArmTokenSpaceGuid.PcdArmPrimaryCoreMask

   gArmTokenSpaceGuid.PcdArmPrimaryCore

 

-  gArmTokenSpaceGuid.PcdGicDistributorBase

-  gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase

-

   gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz

diff --git a/ArmPkg/Drivers/ArmCpuLib/ArmCortexA8Lib/ArmCortexA8Lib.c b/ArmPkg/Drivers/ArmCpuLib/ArmCortexA8Lib/ArmCortexA8Lib.c
index d755f68243..e0ba1fab8d 100644
--- a/ArmPkg/Drivers/ArmCpuLib/ArmCortexA8Lib/ArmCortexA8Lib.c
+++ b/ArmPkg/Drivers/ArmCpuLib/ArmCortexA8Lib/ArmCortexA8Lib.c
@@ -20,24 +20,6 @@
 #include <Chipset/ArmV7.h>

 

 VOID

-ArmCpuSynchronizeWait (

-  IN ARM_CPU_SYNCHRONIZE_EVENT   Event

-  )

-{

-  // The CortexA8 is a Unicore CPU. We must not use Synchronization functions

-  ASSERT(0);

-}

-

-VOID

-ArmCpuSynchronizeSignal (

-  IN ARM_CPU_SYNCHRONIZE_EVENT   Event

-  )

-{

-  // The CortexA8 is a Unicore CPU. We must not use Synchronization functions

-  ASSERT(0);

-}

-

-VOID

 ArmCpuSetup (

   IN  UINTN         MpId

   )

diff --git a/ArmPkg/Drivers/ArmCpuLib/ArmCortexA9Lib/ArmCortexA9Helper.S b/ArmPkg/Drivers/ArmCpuLib/ArmCortexA9Lib/ArmCortexA9Helper.S
index c69c8d44c5..5db5861922 100644
--- a/ArmPkg/Drivers/ArmCpuLib/ArmCortexA9Lib/ArmCortexA9Helper.S
+++ b/ArmPkg/Drivers/ArmCpuLib/ArmCortexA9Lib/ArmCortexA9Helper.S
@@ -1,5 +1,5 @@
 //

-//  Copyright (c) 2011, ARM Limited. All rights reserved.

+//  Copyright (c) 2011-2012, ARM Limited. All rights reserved.

 //

 //  This program and the accompanying materials

 //  are licensed and made available under the terms and conditions of the BSD License

@@ -18,24 +18,7 @@
 .text

 .align 3

 

-GCC_ASM_EXPORT(ArmCpuSynchronizeWait)

 GCC_ASM_EXPORT(ArmGetScuBaseAddress)

-GCC_ASM_IMPORT(CArmCpuSynchronizeWait)

-

-// VOID

-// ArmCpuSynchronizeWait (

-//   IN ARM_CPU_SYNCHRONIZE_EVENT   Event

-//   );

-ASM_PFX(ArmCpuSynchronizeWait):

-  cmp   r0, #ARM_CPU_EVENT_BOOT_MEM_INIT

-  // The SCU enabled is the event to tell us the Init Boot Memory is initialized

-  beq   ASM_PFX(ArmWaitScuEnabled)

-  // Case when the stack has been set up

-  push	{r1,lr}

-  LoadConstantToReg (ASM_PFX(CArmCpuSynchronizeWait), r1)

-  blx   r1

-  pop	{r1,lr}

-  bx	lr

 

 // IN None

 // OUT r0 = SCU Base Address

@@ -45,14 +28,3 @@ ASM_PFX(ArmGetScuBaseAddress):
   // offset 0x0000 from the Private Memory Region.

   mrc   p15, 4, r0, c15, c0, 0

   bx  lr

-

-ASM_PFX(ArmWaitScuEnabled):

-  // Read Configuration Base Address Register. ArmCBar cannot be called to get

-  // the Configuration BAR as a stack is not necessary setup. The SCU is at the

-  // offset 0x0000 from the Private Memory Region.

-  mrc   p15, 4, r0, c15, c0, 0

-  add   r0, r0, #A9_SCU_CONTROL_OFFSET

-  ldr   r0, [r0]

-  cmp   r0, #1

-  bne   ASM_PFX(ArmWaitScuEnabled)

-  bx    lr

diff --git a/ArmPkg/Drivers/ArmCpuLib/ArmCortexA9Lib/ArmCortexA9Helper.asm b/ArmPkg/Drivers/ArmCpuLib/ArmCortexA9Lib/ArmCortexA9Helper.asm
index ef5015c189..7150834b02 100644
--- a/ArmPkg/Drivers/ArmCpuLib/ArmCortexA9Lib/ArmCortexA9Helper.asm
+++ b/ArmPkg/Drivers/ArmCpuLib/ArmCortexA9Lib/ArmCortexA9Helper.asm
@@ -1,5 +1,5 @@
 //

-//  Copyright (c) 2011, ARM Limited. All rights reserved.

+//  Copyright (c) 2011-2012, ARM Limited. All rights reserved.

 //

 //  This program and the accompanying materials

 //  are licensed and made available under the terms and conditions of the BSD License

@@ -17,28 +17,11 @@
 

   INCLUDE AsmMacroIoLib.inc

 

-  EXPORT  ArmCpuSynchronizeWait

   EXPORT  ArmGetScuBaseAddress

-  IMPORT  CArmCpuSynchronizeWait

 

   PRESERVE8

   AREA    ArmCortexA9Helper, CODE, READONLY

 

-// VOID

-// ArmCpuSynchronizeWait (

-//   IN ARM_CPU_SYNCHRONIZE_EVENT   Event

-//   );

-ArmCpuSynchronizeWait

-  cmp   r0, #ARM_CPU_EVENT_BOOT_MEM_INIT

-  // The SCU enabled is the event to tell us the Init Boot Memory is initialized

-  beq   ArmWaitScuEnabled

-  // Case when the stack has been set up

-  push	{r1,lr}

-  LoadConstantToReg (CArmCpuSynchronizeWait, r1)

-  blx   r1

-  pop	{r1,lr}

-  bx	lr

-

 // IN None

 // OUT r0 = SCU Base Address

 ArmGetScuBaseAddress

@@ -48,15 +31,4 @@ ArmGetScuBaseAddress
   mrc   p15, 4, r0, c15, c0, 0

   bx  lr

 

-ArmWaitScuEnabled

-  // Read Configuration Base Address Register. ArmCBar cannot be called to get

-  // the Configuration BAR as a stack is not necessary setup. The SCU is at the

-  // offset 0x0000 from the Private Memory Region.

-  mrc   p15, 4, r0, c15, c0, 0

-  add   r0, r0, #A9_SCU_CONTROL_OFFSET

-  ldr   r0, [r0]

-  cmp   r0, #1

-  bne   ArmWaitScuEnabled

-  bx    lr

-

   END

diff --git a/ArmPkg/Drivers/ArmCpuLib/ArmCortexA9Lib/ArmCortexA9Lib.c b/ArmPkg/Drivers/ArmCpuLib/ArmCortexA9Lib/ArmCortexA9Lib.c
index 7c5c3ee6a9..324ddb5850 100644
--- a/ArmPkg/Drivers/ArmCpuLib/ArmCortexA9Lib/ArmCortexA9Lib.c
+++ b/ArmPkg/Drivers/ArmCpuLib/ArmCortexA9Lib/ArmCortexA9Lib.c
@@ -1,6 +1,6 @@
 /** @file

 

-  Copyright (c) 2011, ARM Limited. All rights reserved.

+  Copyright (c) 2011-2012, ARM Limited. All rights reserved.

 

   This program and the accompanying materials

   are licensed and made available under the terms and conditions of the BSD License

@@ -15,40 +15,12 @@
 #include <Base.h>

 #include <Library/ArmLib.h>

 #include <Library/ArmCpuLib.h>

-#include <Library/ArmGicLib.h>

 #include <Library/IoLib.h>

 #include <Library/PcdLib.h>

 

 #include <Chipset/ArmCortexA9.h>

 

 VOID

-ArmCpuSynchronizeSignal (

-  IN ARM_CPU_SYNCHRONIZE_EVENT   Event

-  )

-{

-  if (Event == ARM_CPU_EVENT_BOOT_MEM_INIT) {

-    // Do nothing, Cortex A9 secondary cores are waiting for the SCU to be

-    // enabled (done by ArmCpuSetup()) as a way to know when the Init Boot

-    // Mem as been initialized

-  } else {

-    // Send SGI to all Secondary core to wake them up from WFI state.

-    ArmGicSendSgiTo (PcdGet32(PcdGicDistributorBase), ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E);

-  }

-}

-

-VOID

-CArmCpuSynchronizeWait (

-  IN ARM_CPU_SYNCHRONIZE_EVENT   Event

-  )

-{

-  // Waiting for the SGI from the primary core

-  ArmCallWFI ();

-

-  // Acknowledge the interrupt and send End of Interrupt signal.

-  ArmGicAcknowledgeSgiFrom (PcdGet32(PcdGicInterruptInterfaceBase), PRIMARY_CORE_ID);

-}

-

-VOID

 ArmEnableScu (

   VOID

   )

diff --git a/ArmPkg/Drivers/ArmCpuLib/ArmCortexA9Lib/ArmCortexA9Lib.inf b/ArmPkg/Drivers/ArmCpuLib/ArmCortexA9Lib/ArmCortexA9Lib.inf
index a03efd237b..866736f6ff 100644
--- a/ArmPkg/Drivers/ArmCpuLib/ArmCortexA9Lib/ArmCortexA9Lib.inf
+++ b/ArmPkg/Drivers/ArmCpuLib/ArmCortexA9Lib/ArmCortexA9Lib.inf
@@ -1,5 +1,5 @@
 #/* @file

-#  Copyright (c) 2011, ARM Limited. All rights reserved.

+#  Copyright (c) 2011-2012, ARM Limited. All rights reserved.

 #  

 #  This program and the accompanying materials                          

 #  are licensed and made available under the terms and conditions of the BSD License         

@@ -25,7 +25,6 @@
 

 [LibraryClasses]

   ArmLib

-  ArmGicSecLib

   IoLib

   PcdLib

 

@@ -39,6 +38,3 @@
 [FixedPcd]

   gArmTokenSpaceGuid.PcdArmPrimaryCoreMask

   gArmTokenSpaceGuid.PcdArmPrimaryCore

-

-  gArmTokenSpaceGuid.PcdGicDistributorBase

-  gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase