ArmPkg/ArmGic: Added GicV3 support to ArmGicLib

Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16233 6f19259b-4bc3-4df7-8a09-765794883524
author: Olivier Martin <olivier.martin@arm.com> 2014-10-27 10:29:50 +0000
committer: oliviermartin <oliviermartin@Edk2> 2014-10-27 10:29:50 +0000
commit: d71338597e75002d5e2b63701834b07dae1af3a0 (patch)
tree: c2c7b777a3251c055c9ee63377885afc7e1bb4da /ArmPkg/Drivers
parent: 5f525769b9254bebea76512cfd348d8637e898e5 (diff)
download: edk2-platforms-d71338597e75002d5e2b63701834b07dae1af3a0.tar.xz
7 files changed, 375 insertions, 0 deletions
diff --git a/ArmPkg/Drivers/ArmGic/ArmGicLib.c b/ArmPkg/Drivers/ArmGic/ArmGicLib.c
index 7d99f9f98a..1e5924f5a4 100644
--- a/ArmPkg/Drivers/ArmGic/ArmGicLib.c
+++ b/ArmPkg/Drivers/ArmGic/ArmGicLib.c
@@ -18,6 +18,7 @@
 #include <Library/IoLib.h>
 
 #include "GicV2/ArmGicV2Lib.h"
+#include "GicV3/ArmGicV3Lib.h"
 
 UINTN
 EFIAPI
@@ -82,6 +83,8 @@ ArmGicAcknowledgeInterrupt (
     if (InterruptId != NULL) {
       *InterruptId = Value & ARM_GIC_ICCIAR_ACKINTID;
     }
+  } else if (Revision == ARM_GIC_ARCH_REVISION_3) {
+    Value = ArmGicV3AcknowledgeInterrupt ();
   } else {
     ASSERT_EFI_ERROR (EFI_UNSUPPORTED);
     // Report Spurious interrupt which is what the above controllers would
@@ -104,6 +107,8 @@ ArmGicEndOfInterrupt (
   Revision = ArmGicGetSupportedArchRevision ();
   if (Revision == ARM_GIC_ARCH_REVISION_2) {
     ArmGicV2EndOfInterrupt (GicInterruptInterfaceBase, Source);
+  } else if (Revision == ARM_GIC_ARCH_REVISION_3) {
+    ArmGicV3EndOfInterrupt (Source);
   } else {
     ASSERT_EFI_ERROR (EFI_UNSUPPORTED);
   }
@@ -183,6 +188,8 @@ ArmGicEnableInterruptInterface (
   Revision = ArmGicGetSupportedArchRevision ();
   if (Revision == ARM_GIC_ARCH_REVISION_2) {
     ArmGicV2EnableInterruptInterface (GicInterruptInterfaceBase);
+  } else if (Revision == ARM_GIC_ARCH_REVISION_3) {
+    ArmGicV3EnableInterruptInterface ();
   } else {
     ASSERT_EFI_ERROR (EFI_UNSUPPORTED);
   }
@@ -199,6 +206,8 @@ ArmGicDisableInterruptInterface (
   Revision = ArmGicGetSupportedArchRevision ();
   if (Revision == ARM_GIC_ARCH_REVISION_2) {
     ArmGicV2DisableInterruptInterface (GicInterruptInterfaceBase);
+  } else if (Revision == ARM_GIC_ARCH_REVISION_3) {
+    ArmGicV3DisableInterruptInterface ();
   } else {
     ASSERT_EFI_ERROR (EFI_UNSUPPORTED);
   }
diff --git a/ArmPkg/Drivers/ArmGic/ArmGicLib.inf b/ArmPkg/Drivers/ArmGic/ArmGicLib.inf
index ca5cd1942b..81282b9b82 100644
--- a/ArmPkg/Drivers/ArmGic/ArmGicLib.inf
+++ b/ArmPkg/Drivers/ArmGic/ArmGicLib.inf
@@ -28,9 +28,12 @@
 
 [Sources.ARM]
   Arm/ArmGicArchLib.c
+  GicV3/Arm/ArmGicV3.S     | GCC
+  GicV3/Arm/ArmGicV3.asm   | RVCT
 
 [Sources.AARCH64]
   AArch64/ArmGicArchLib.c
+  GicV3/AArch64/ArmGicV3.S | GCC
 
 [LibraryClasses]
   ArmLib
diff --git a/ArmPkg/Drivers/ArmGic/ArmGicSecLib.inf b/ArmPkg/Drivers/ArmGic/ArmGicSecLib.inf
index 45382998f0..573e5e7e50 100644
--- a/ArmPkg/Drivers/ArmGic/ArmGicSecLib.inf
+++ b/ArmPkg/Drivers/ArmGic/ArmGicSecLib.inf
@@ -28,9 +28,12 @@
 
 [Sources.ARM]
   Arm/ArmGicArchLib.c
+  GicV3/Arm/ArmGicV3.S     | GCC
+  GicV3/Arm/ArmGicV3.asm   | RVCT
 
 [Sources.AARCH64]
   AArch64/ArmGicArchLib.c
+  GicV3/AArch64/ArmGicV3.S | GCC
 
 [Packages]
   ArmPkg/ArmPkg.dec
diff --git a/ArmPkg/Drivers/ArmGic/GicV3/AArch64/ArmGicV3.S b/ArmPkg/Drivers/ArmGic/GicV3/AArch64/ArmGicV3.S
new file mode 100644
index 0000000000..793e8aa5b3
--- /dev/null
+++ b/ArmPkg/Drivers/ArmGic/GicV3/AArch64/ArmGicV3.S
@@ -0,0 +1,114 @@
+#
+#  Copyright (c) 2014, ARM Limited. All rights reserved.
+#
+#  This program and the accompanying materials are licensed and made available
+#  under the terms and conditions of the BSD License which accompanies this
+#  distribution. The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+
+#include <AsmMacroIoLibV8.h>
+
+#define ICC_SRE_EL1             S3_0_C12_C12_5
+#define ICC_SRE_EL2             S3_4_C12_C9_5
+#define ICC_SRE_EL3             S3_6_C12_C12_5
+#define ICC_IGRPEN1_EL1         S3_0_C12_C12_7
+#define ICC_EOIR1_EL1           S3_0_C12_C12_1
+#define ICC_IAR1_EL1            S3_0_C12_C12_0
+#define ICC_PMR_EL1             S3_0_C4_C6_0
+#define ICC_BPR1_EL1            S3_0_C12_C12_3
+
+.text
+.align 2
+
+GCC_ASM_EXPORT(ArmGicGetControlSystemRegisterEnable)
+GCC_ASM_EXPORT(ArmGicSetControlSystemRegisterEnable)
+GCC_ASM_EXPORT(ArmGicV3EnableInterruptInterface)
+GCC_ASM_EXPORT(ArmGicV3DisableInterruptInterface)
+GCC_ASM_EXPORT(ArmGicV3EndOfInterrupt)
+GCC_ASM_EXPORT(ArmGicV3AcknowledgeInterrupt)
+GCC_ASM_EXPORT(ArmGicV3SetPriorityMask)
+GCC_ASM_EXPORT(ArmGicV3SetBinaryPointer)
+
+//UINT32
+//EFIAPI
+//ArmGicGetControlSystemRegisterEnable (
+//  VOID
+//  );
+ASM_PFX(ArmGicGetControlSystemRegisterEnable):
+        EL1_OR_EL2_OR_EL3(x1)
+1:  mrs x0, ICC_SRE_EL1
+        b       4f
+2:  mrs x0, ICC_SRE_EL2
+        b       4f
+3:  mrs x0, ICC_SRE_EL3
+4:  ret
+
+//VOID
+//EFIAPI
+//ArmGicSetControlSystemRegisterEnable (
+//  IN UINT32         ControlSystemRegisterEnable
+//  );
+ASM_PFX(ArmGicSetControlSystemRegisterEnable):
+        EL1_OR_EL2_OR_EL3(x1)
+1:  msr ICC_SRE_EL1, x0
+        b       4f
+2:  msr ICC_SRE_EL2, x0
+        b       4f
+3:  msr ICC_SRE_EL3, x0
+4:  isb
+        ret
+
+//VOID
+//ArmGicV3EnableInterruptInterface (
+//  VOID
+//  );
+ASM_PFX(ArmGicV3EnableInterruptInterface):
+        mov     x0, #1
+        msr     ICC_IGRPEN1_EL1, x0
+        ret
+
+//VOID
+//ArmGicV3DisableInterruptInterface (
+//  VOID
+//  );
+ASM_PFX(ArmGicV3DisableInterruptInterface):
+        mov     x0, #0
+        msr     ICC_IGRPEN1_EL1, x0
+        ret
+
+//VOID
+//ArmGicV3EndOfInterrupt (
+//  IN UINTN          InterruptId
+//  );
+ASM_PFX(ArmGicV3EndOfInterrupt):
+        msr     ICC_EOIR1_EL1, x0
+        ret
+
+//UINTN
+//ArmGicV3AcknowledgeInterrupt (
+//  VOID
+//  );
+ASM_PFX(ArmGicV3AcknowledgeInterrupt):
+        mrs     x0, ICC_IAR1_EL1
+        ret
+
+//VOID
+//ArmGicV3SetPriorityMask (
+//  IN UINTN          Priority
+//  );
+ASM_PFX(ArmGicV3SetPriorityMask):
+        msr     ICC_PMR_EL1, x0
+        ret
+
+//VOID
+//ArmGicV3SetBinaryPointer (
+//  IN UINTN          BinaryPoint
+//  );
+ASM_PFX(ArmGicV3SetBinaryPointer):
+        msr     ICC_BPR1_EL1, x0
+        ret
diff --git a/ArmPkg/Drivers/ArmGic/GicV3/Arm/ArmGicV3.S b/ArmPkg/Drivers/ArmGic/GicV3/Arm/ArmGicV3.S
new file mode 100644
index 0000000000..5c64ec6cd0
--- /dev/null
+++ b/ArmPkg/Drivers/ArmGic/GicV3/Arm/ArmGicV3.S
@@ -0,0 +1,98 @@
+#
+#  Copyright (c) 2014, ARM Limited. All rights reserved.
+#
+#  This program and the accompanying materials are licensed and made available
+#  under the terms and conditions of the BSD License which accompanies this
+#  distribution. The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+
+#include <AsmMacroIoLib.h>
+#include <Library/ArmLib.h>
+
+// For the moment we assume this will run in SVC mode on ARMv7
+
+.text
+.align 2
+
+GCC_ASM_EXPORT(ArmGicGetControlSystemRegisterEnable)
+GCC_ASM_EXPORT(ArmGicSetControlSystemRegisterEnable)
+GCC_ASM_EXPORT(ArmGicV3EnableInterruptInterface)
+GCC_ASM_EXPORT(ArmGicV3DisableInterruptInterface)
+GCC_ASM_EXPORT(ArmGicV3EndOfInterrupt)
+GCC_ASM_EXPORT(ArmGicV3AcknowledgeInterrupt)
+GCC_ASM_EXPORT(ArmGicV3SetPriorityMask)
+GCC_ASM_EXPORT(ArmGicV3SetBinaryPointer)
+
+//UINT32
+//EFIAPI
+//ArmGicGetControlSystemRegisterEnable (
+//  VOID
+//  );
+ASM_PFX(ArmGicGetControlSystemRegisterEnable):
+        mrc     p15, 0, r0, c12, c12, 5 // ICC_SRE
+        bx      lr
+
+//VOID
+//EFIAPI
+//ArmGicSetControlSystemRegisterEnable (
+//  IN UINT32         ControlSystemRegisterEnable
+//  );
+ASM_PFX(ArmGicSetControlSystemRegisterEnable):
+        mcr     p15, 0, r0, c12, c12, 5 // ICC_SRE
+        isb
+        bx      lr
+
+//VOID
+//ArmGicV3EnableInterruptInterface (
+//  VOID
+//  );
+ASM_PFX(ArmGicV3EnableInterruptInterface):
+        mov     r0, #1
+        mcr     p15, 0, r0, c12, c12, 7 // ICC_IGRPEN1
+        bx      lr
+
+//VOID
+//ArmGicV3DisableInterruptInterface (
+//  VOID
+//  );
+ASM_PFX(ArmGicV3DisableInterruptInterface):
+        mov     r0, #0
+        mcr     p15, 0, r0, c12, c12, 7 // ICC_IGRPEN1
+        bx      lr
+
+//VOID
+//ArmGicV3EndOfInterrupt (
+//  IN UINTN InterruptId
+//  );
+ASM_PFX(ArmGicV3EndOfInterrupt):
+        mcr     p15, 0, r0, c12, c12, 1 //ICC_EOIR1
+        bx      lr
+
+//UINTN
+//ArmGicV3AcknowledgeInterrupt (
+//  VOID
+//  );
+ASM_PFX(ArmGicV3AcknowledgeInterrupt):
+        mrc     p15, 0, r0, c12, c8, 0 //ICC_IAR1
+        bx      lr
+
+//VOID
+//ArmGicV3SetPriorityMask (
+//  IN UINTN                  Priority
+//  );
+ASM_PFX(ArmGicV3SetPriorityMask):
+        mcr     p15, 0, r0, c4, c6, 0 //ICC_PMR
+        bx      lr
+
+//VOID
+//ArmGicV3SetBinaryPointer (
+//  IN UINTN                  BinaryPoint
+//  );
+ASM_PFX(ArmGicV3SetBinaryPointer):
+        mcr     p15, 0, r0, c12, c12, 3 //ICC_BPR1
+        bx      lr
diff --git a/ArmPkg/Drivers/ArmGic/GicV3/Arm/ArmGicV3.asm b/ArmPkg/Drivers/ArmGic/GicV3/Arm/ArmGicV3.asm
new file mode 100644
index 0000000000..08d9d4d9f0
--- /dev/null
+++ b/ArmPkg/Drivers/ArmGic/GicV3/Arm/ArmGicV3.asm
@@ -0,0 +1,96 @@
+//
+//  Copyright (c) 2014, ARM Limited. All rights reserved.
+//
+//  This program and the accompanying materials are licensed and made available
+//  under the terms and conditions of the BSD License which accompanies this
+//  distribution. The full text of the license may be found at
+//  http://opensource.org/licenses/bsd-license.php
+//
+//  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+//  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+//
+
+// For the moment we assume this will run in SVC mode on ARMv7
+
+    EXPORT  ArmGicGetControlSystemRegisterEnable
+    EXPORT  ArmGicSetControlSystemRegisterEnable
+    EXPORT  ArmGicV3EnableInterruptInterface
+    EXPORT  ArmGicV3DisableInterruptInterface
+    EXPORT  ArmGicV3EndOfInterrupt
+    EXPORT  ArmGicV3AcknowledgeInterrupt
+    EXPORT  ArmGicV3SetPriorityMask
+    EXPORT  ArmGicV3SetBinaryPointer
+
+    AREA ArmGicV3, CODE, READONLY
+
+//UINT32
+//EFIAPI
+//ArmGicGetControlSystemRegisterEnable (
+//  VOID
+//  );
+ArmGicGetControlSystemRegisterEnable
+        mrc     p15, 0, r0, c12, c12, 5 // ICC_SRE
+        bx      lr
+
+//VOID
+//EFIAPI
+//ArmGicSetControlSystemRegisterEnable (
+//  IN UINT32         ControlSystemRegisterEnable
+//  );
+ArmGicSetControlSystemRegisterEnable
+        mcr     p15, 0, r0, c12, c12, 5 // ICC_SRE
+        isb
+        bx      lr
+
+//VOID
+//ArmGicV3EnableInterruptInterface (
+//  VOID
+//  );
+ArmGicV3EnableInterruptInterface
+        mov     r0, #1
+        mcr     p15, 0, r0, c12, c12, 7 // ICC_IGRPEN1
+        bx      lr
+
+//VOID
+//ArmGicV3DisableInterruptInterface (
+//  VOID
+//  );
+ArmGicV3DisableInterruptInterface
+        mov     r0, #0
+        mcr     p15, 0, r0, c12, c12, 7 // ICC_IGRPEN1
+        bx      lr
+
+//VOID
+//ArmGicV3EndOfInterrupt (
+//  IN UINTN InterruptId
+//  );
+ArmGicV3EndOfInterrupt
+        mcr     p15, 0, r0, c12, c12, 1 //ICC_EOIR1
+        bx      lr
+
+//UINTN
+//ArmGicV3AcknowledgeInterrupt (
+//  VOID
+//  );
+ArmGicV3AcknowledgeInterrupt
+        mrc     p15, 0, r0, c12, c8, 0 //ICC_IAR1
+        bx      lr
+
+//VOID
+//ArmGicV3SetPriorityMask (
+//  IN UINTN                  Priority
+//  );
+ArmGicV3SetPriorityMask
+        mcr     p15, 0, r0, c4, c6, 0 //ICC_PMR
+        bx      lr
+
+//VOID
+//ArmGicV3SetBinaryPointer (
+//  IN UINTN                  BinaryPoint
+//  );
+ArmGicV3SetBinaryPointer
+        mcr     p15, 0, r0, c12, c12, 3 //ICC_BPR1
+        bx      lr
+
+    END
diff --git a/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Lib.h b/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Lib.h
new file mode 100644
index 0000000000..70731c3483
--- /dev/null
+++ b/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Lib.h
@@ -0,0 +1,52 @@
+/** @file
+*
+*  Copyright (c) 2014, ARM Limited. All rights reserved.
+*
+*  This program and the accompanying materials are licensed and made available
+*  under the terms and conditions of the BSD License which accompanies this
+*  distribution. The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef _ARM_GIC_V3_H_
+#define _ARM_GIC_V3_H_
+
+VOID
+EFIAPI
+ArmGicV3EnableInterruptInterface (
+  VOID
+  );
+
+VOID
+EFIAPI
+ArmGicV3DisableInterruptInterface (
+  VOID
+  );
+
+UINTN
+EFIAPI
+ArmGicV3AcknowledgeInterrupt (
+  VOID
+  );
+
+VOID
+EFIAPI
+ArmGicV3EndOfInterrupt (
+  IN UINTN                  Source
+  );
+
+VOID
+ArmGicV3SetBinaryPointer (
+  IN UINTN                  BinaryPoint
+  );
+
+VOID
+ArmGicV3SetPriorityMask (
+  IN UINTN                  Priority
+  );
+
+#endif
author	Olivier Martin <olivier.martin@arm.com>	2014-10-27 10:29:50 +0000
committer	oliviermartin <oliviermartin@Edk2>	2014-10-27 10:29:50 +0000
commit	d71338597e75002d5e2b63701834b07dae1af3a0 (patch)
tree	c2c7b777a3251c055c9ee63377885afc7e1bb4da /ArmPkg/Drivers
parent	5f525769b9254bebea76512cfd348d8637e898e5 (diff)
download	edk2-platforms-d71338597e75002d5e2b63701834b07dae1af3a0.tar.xz