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| author | Olivier Martin <olivier.martin@arm.com> | 2013-12-10 16:39:04 +0000 |
|---|---|---|
| committer | oliviermartin <oliviermartin@6f19259b-4bc3-4df7-8a09-765794883524> | 2013-12-10 16:39:04 +0000 |
| commit | 62436c2162f2201eb105169b414719705adb7e3e (patch) | |
| tree | 0106c017994a7fc557944df4451d09e152d233fd /ArmPkg/Include/Chipset | |
| parent | 377a32dbed62b66f6d45589d3cae7a8253691422 (diff) | |
| download | edk2-platforms-62436c2162f2201eb105169b414719705adb7e3e.tar.xz | |
ArmPkg/AArch64Mmu.h: Fix 'Shift is >= width of type'
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14956 6f19259b-4bc3-4df7-8a09-765794883524
Diffstat (limited to 'ArmPkg/Include/Chipset')
| -rw-r--r-- | ArmPkg/Include/Chipset/AArch64Mmu.h | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/ArmPkg/Include/Chipset/AArch64Mmu.h b/ArmPkg/Include/Chipset/AArch64Mmu.h index 7c9890331f..77a96ec637 100644 --- a/ArmPkg/Include/Chipset/AArch64Mmu.h +++ b/ArmPkg/Include/Chipset/AArch64Mmu.h @@ -102,12 +102,12 @@ #define TCR_TG0_4KB (0 << 14)
-#define TCR_IPS_4GB (0UL << 32)
-#define TCR_IPS_64GB (1UL << 32)
-#define TCR_IPS_1TB (2UL << 32)
-#define TCR_IPS_4TB (3UL << 32)
-#define TCR_IPS_16TB (4UL << 32)
-#define TCR_IPS_256TB (5UL << 32)
+#define TCR_IPS_4GB (0ULL << 32)
+#define TCR_IPS_64GB (1ULL << 32)
+#define TCR_IPS_1TB (2ULL << 32)
+#define TCR_IPS_4TB (3ULL << 32)
+#define TCR_IPS_16TB (4ULL << 32)
+#define TCR_IPS_256TB (5ULL << 32)
#define TTBR_ASID_FIELD (48)
|