diff options
| author | Garrett Kirkendall <garrett.kirkendall@amd.com> | 2013-10-15 09:25:38 +0000 |
|---|---|---|
| committer | oliviermartin <oliviermartin@6f19259b-4bc3-4df7-8a09-765794883524> | 2013-10-15 09:25:38 +0000 |
| commit | 8833370303d3bf3153760ee42760ef1b9b5c562b (patch) | |
| tree | d70f7506a56570d0585b5771ca587cef8aa09d34 /ArmPkg/Include/Chipset | |
| parent | 74b04490da9dcb90de61e31db51b8e137f9e6e3d (diff) | |
| download | edk2-platforms-8833370303d3bf3153760ee42760ef1b9b5c562b.tar.xz | |
ArmPkg/Include/Chipset: Fix translation table address calculations for AARCH64
TT_ADDRESS_* macros were not casting immediate values to UINTN.
This causes shift operations to be off by 32-bits when calculating
addresses above 4GB. Any address above 4GB was being improperly calculated.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Garrett Kirkendall <garrett.kirkendall@amd.com>
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14777 6f19259b-4bc3-4df7-8a09-765794883524
Diffstat (limited to 'ArmPkg/Include/Chipset')
| -rw-r--r-- | ArmPkg/Include/Chipset/AArch64Mmu.h | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/ArmPkg/Include/Chipset/AArch64Mmu.h b/ArmPkg/Include/Chipset/AArch64Mmu.h index 17c28fa205..7c9890331f 100644 --- a/ArmPkg/Include/Chipset/AArch64Mmu.h +++ b/ArmPkg/Include/Chipset/AArch64Mmu.h @@ -33,15 +33,15 @@ // The first offset starts at 12bit. There are 4 levels of 9-bit address range from level 3 to level 0
#define TT_ADDRESS_OFFSET_AT_LEVEL(TableLevel) (12 + ((3 - (TableLevel)) * 9))
-#define TT_BLOCK_ENTRY_SIZE_AT_LEVEL(Level) (1 << TT_ADDRESS_OFFSET_AT_LEVEL(Level))
+#define TT_BLOCK_ENTRY_SIZE_AT_LEVEL(Level) (1ULL << TT_ADDRESS_OFFSET_AT_LEVEL(Level))
// Get the associated entry in the given Translation Table
#define TT_GET_ENTRY_FOR_ADDRESS(TranslationTable, Level, Address) \
- ((UINTN)(TranslationTable) + ((((Address) >> TT_ADDRESS_OFFSET_AT_LEVEL(Level)) & (BIT9-1)) * sizeof(UINT64)))
+ ((UINTN)(TranslationTable) + ((((UINTN)(Address) >> TT_ADDRESS_OFFSET_AT_LEVEL(Level)) & (BIT9-1)) * sizeof(UINT64)))
// Return the smallest address granularity from the table level.
// The first offset starts at 12bit. There are 4 levels of 9-bit address range from level 3 to level 0
-#define TT_ADDRESS_AT_LEVEL(TableLevel) (1 << TT_ADDRESS_OFFSET_AT_LEVEL(TableLevel))
+#define TT_ADDRESS_AT_LEVEL(TableLevel) (1ULL << TT_ADDRESS_OFFSET_AT_LEVEL(TableLevel))
#define TT_LAST_BLOCK_ADDRESS(TranslationTable, EntryCount) \
((UINT64*)((EFI_PHYSICAL_ADDRESS)(TranslationTable) + (((EntryCount) - 1) * sizeof(UINT64))))
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