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authorOlivier Martin <olivier.martin@arm.com>2014-11-11 00:51:11 +0000
committeroliviermartin <oliviermartin@Edk2>2014-11-11 00:51:11 +0000
commitfb7ea6114a780b2fe0da56156d65fa7659ffe2e2 (patch)
treec6f9f4cf7f6976c602ef0f3dae33e0d9ed70d836 /ArmPkg/Library/ArmLib/AArch64
parent6382e5df4e320b8b7db40bccbeccbd89d368d52f (diff)
downloadedk2-platforms-fb7ea6114a780b2fe0da56156d65fa7659ffe2e2.tar.xz
ArmPkg: Ensured the stack is always quad-word aligned
From the AArch64 Procedure Call Standard (ARM IHI 0055B): 5.2.2.1 Universal stack constraints At all times the following basic constraints must hold: - SP mod 16 = 0. The stack must be quad-word aligned. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16327 6f19259b-4bc3-4df7-8a09-765794883524
Diffstat (limited to 'ArmPkg/Library/ArmLib/AArch64')
-rw-r--r--ArmPkg/Library/ArmLib/AArch64/AArch64Support.S8
1 files changed, 4 insertions, 4 deletions
diff --git a/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S b/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S
index 98eba3cac2..bdede48724 100644
--- a/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S
+++ b/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S
@@ -313,8 +313,8 @@ ASM_PFX(ArmDisableBranchPrediction):
ASM_PFX(AArch64AllDataCachesOperation):
// We can use regs 0-7 and 9-15 without having to save/restore.
-// Save our link register on the stack.
- str x30, [sp, #-0x10]!
+// Save our link register on the stack. - The stack must always be quad-word aligned
+ str x30, [sp, #-16]!
mov x1, x0 // Save Function call in x1
mrs x6, clidr_el1 // Read EL1 CLIDR
and x3, x6, #0x7000000 // Mask out all but Level of Coherency (LoC)
@@ -326,8 +326,8 @@ ASM_PFX(AArch64AllDataCachesOperation):
ASM_PFX(AArch64PerformPoUDataCacheOperation):
// We can use regs 0-7 and 9-15 without having to save/restore.
-// Save our link register on the stack.
- str x30, [sp, #-0x10]!
+// Save our link register on the stack. - The stack must always be quad-word aligned
+ str x30, [sp, #-16]!
mov x1, x0 // Save Function call in x1
mrs x6, clidr_el1 // Read EL1 CLIDR
and x3, x6, #0x38000000 // Mask out all but Point of Unification (PoU)