diff options
| author | Ard Biesheuvel <ard.biesheuvel@linaro.org> | 2015-11-09 13:26:32 +0000 |
|---|---|---|
| committer | abiesheuvel <abiesheuvel@Edk2> | 2015-11-09 13:26:32 +0000 |
| commit | f97ab1bbf4c4512e1aabd149527c1aa4d5b0c03b (patch) | |
| tree | 55a182b6e3cc880ceb2ebdf9c0df3e2a035b3411 /ArmPkg/Library/ArmLib/Common | |
| parent | acdb6dc8b739ccddd8425e609b68871151c5b94e (diff) | |
| download | edk2-platforms-f97ab1bbf4c4512e1aabd149527c1aa4d5b0c03b.tar.xz | |
ArmPkg/ArmLib: remove CCSIDR based cache info routines
The ARM architecture does not allow the actual geometries of the caches
to be inferred from the CCSIDR cache info system register, since the
geometry it reports is intended for performing cache maintenance by
set/way and nothing else. Since the ArmLib cache info routines are
based solely on CCSIDR contents, they should not be used.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18753 6f19259b-4bc3-4df7-8a09-765794883524
Diffstat (limited to 'ArmPkg/Library/ArmLib/Common')
| -rw-r--r-- | ArmPkg/Library/ArmLib/Common/ArmLib.c | 20 |
1 files changed, 0 insertions, 20 deletions
diff --git a/ArmPkg/Library/ArmLib/Common/ArmLib.c b/ArmPkg/Library/ArmLib/Common/ArmLib.c index d7316972b7..4febc45220 100644 --- a/ArmPkg/Library/ArmLib/Common/ArmLib.c +++ b/ArmPkg/Library/ArmLib/Common/ArmLib.c @@ -23,26 +23,6 @@ VOID
EFIAPI
-ArmCacheInformation (
- OUT ARM_CACHE_INFO *CacheInfo
- )
-{
- if (CacheInfo != NULL) {
- CacheInfo->Type = ArmCacheType();
- CacheInfo->Architecture = ArmCacheArchitecture();
- CacheInfo->DataCachePresent = ArmDataCachePresent();
- CacheInfo->DataCacheSize = ArmDataCacheSize();
- CacheInfo->DataCacheAssociativity = ArmDataCacheAssociativity();
- CacheInfo->DataCacheLineLength = ArmDataCacheLineLength();
- CacheInfo->InstructionCachePresent = ArmInstructionCachePresent();
- CacheInfo->InstructionCacheSize = ArmInstructionCacheSize();
- CacheInfo->InstructionCacheAssociativity = ArmInstructionCacheAssociativity();
- CacheInfo->InstructionCacheLineLength = ArmInstructionCacheLineLength();
- }
-}
-
-VOID
-EFIAPI
ArmSetAuxCrBit (
IN UINT32 Bits
)
|