ArmPkg: Introduce ArmSetLowVectors/ArmSetHighVectors functions

These functions set/clear the SCTLR.V bit that controls the location
of the Vector Table.
This commit also forces the SCTLR.V to be clear when the VBAR register
is set.

Note: The original fix has been proposed by Eugene Cohen (HP).




git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@11739 6f19259b-4bc3-4df7-8a09-765794883524

2 files changed, 42 insertions, 0 deletions

diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S
index 5b12d1dee2..b11c19dc59 100644
--- a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S
+++ b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S
@@ -34,6 +34,8 @@ GCC_ASM_EXPORT (ArmDisableInstructionCache)
 GCC_ASM_EXPORT (ArmEnableSWPInstruction)
 GCC_ASM_EXPORT (ArmEnableBranchPrediction)
 GCC_ASM_EXPORT (ArmDisableBranchPrediction)
+GCC_ASM_EXPORT (ArmSetLowVectors)
+GCC_ASM_EXPORT (ArmSetHighVectors)
 GCC_ASM_EXPORT (ArmV7AllDataCachesOperation)
 GCC_ASM_EXPORT (ArmDataMemoryBarrier)
 GCC_ASM_EXPORT (ArmDataSyncronizationBarrier)
@@ -199,6 +201,19 @@ ASM_PFX(ArmDisableBranchPrediction):
   isb
   bx      LR
 
+ASM_PFX(ArmSetLowVectors):
+  mrc     p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data)
+  bic     r0, r0, #0x00002000   @ clear V bit
+  mcr     p15, 0, r0, c1, c0, 0 @ Write R0 into SCTLR (Write control register configuration data)
+  isb
+  bx      LR
+
+ASM_PFX(ArmSetHighVectors):
+  mrc     p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data)
+  orr     r0, r0, #0x00002000   @ clear V bit
+  mcr     p15, 0, r0, c1, c0, 0 @ Write R0 into SCTLR (Write control register configuration data)
+  isb
+  bx      LR
 
 ASM_PFX(ArmV7AllDataCachesOperation):
   stmfd SP!,{r4-r12, LR}
@@ -287,7 +302,13 @@ ASM_PFX(ArmWriteVMBar):
   bx      lr
 
 ASM_PFX(ArmWriteVBar):
+  # Set the Address of the Vector Table in the VBAR register
   mcr     p15, 0, r0, c12, c0, 0 
+  # Ensure the SCTLR.V bit is clear
+  mrc     p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data)
+  bic     r0, r0, #0x00002000   @ clear V bit
+  mcr     p15, 0, r0, c1, c0, 0 @ Write R0 into SCTLR (Write control register configuration data)
+  isb
   bx      lr
 
 ASM_PFX(ArmWriteCPACR):
diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm
index 4c78c54674..75399cb0fc 100644
--- a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm
+++ b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm
@@ -31,6 +31,8 @@
     EXPORT  ArmEnableSWPInstruction
     EXPORT  ArmEnableBranchPrediction
     EXPORT  ArmDisableBranchPrediction
+    EXPORT  ArmSetLowVectors
+    EXPORT  ArmSetHighVectors
     EXPORT  ArmV7AllDataCachesOperation
     EXPORT  ArmDataMemoryBarrier
     EXPORT  ArmDataSyncronizationBarrier
@@ -196,6 +198,19 @@ ArmDisableBranchPrediction
   isb
   bx      LR
 
+ArmSetLowVectors
+  mrc     p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)
+  bic     r0, r0, #0x00002000   ; clear V bit
+  mcr     p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
+  isb
+  bx      LR
+
+ArmSetHighVectors
+  mrc     p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)
+  orr     r0, r0, #0x00002000   ; clear V bit
+  mcr     p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
+  isb
+  bx      LR
 
 ArmV7AllDataCachesOperation
   stmfd SP!,{r4-r12, LR}
@@ -281,7 +296,13 @@ ArmWriteVMBar
   bx      lr
 
 ArmWriteVBar
+  // Set the Address of the Vector Table in the VBAR register
   mcr     p15, 0, r0, c12, c0, 0 
+  // Ensure the SCTLR.V bit is clear
+  mrc     p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)
+  bic     r0, r0, #0x00002000   ; clear V bit
+  mcr     p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
+  isb
   bx      lr
 
 ArmReadVBar