ArmPlatformPkg/TZASC: Allow specifying subregions to be disabled

ARM TZASC-380 IP provides a mechanism to split memory regions being
protected via it into eight equal-sized sub-regions. A bit-setting
allows the corresponding subregion to be disabled.

Several NXP/FSL SoCs support the TZASC-380 IP block and allow
the DDR connected via the TZASC to be partitioned into regions
having different security settings and also allow subregions
to be disabled.

This patch enables this support and can be used for SoCs which
support such a partition of DDR regions.

Details of the 'subregion_disable' register can be viewed here:
http://infocenter.arm.com/help/topic/com.arm.doc.ddi0431c/CHDIGDCI.html

Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@nxp.com>
[bhupesh.linux@gmail.com : Added gmail ID as NXP one is no longer valid]
Signed-off-by: Bhupesh Sharma <bhupesh.linux@gmail.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

1 files changed, 7 insertions, 7 deletions

diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressSecLibCTA9x4/CTA9x4Sec.c b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressSecLibCTA9x4/CTA9x4Sec.c
index 6fa0774f59..42d731ea98 100644
--- a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressSecLibCTA9x4/CTA9x4Sec.c
+++ b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressSecLibCTA9x4/CTA9x4Sec.c
@@ -72,18 +72,18 @@ ArmPlatformSecTrustzoneInit (
   // NOR Flash 0 non secure (BootMon)

   TZASCSetRegion(ARM_VE_TZASC_BASE,1,TZASC_REGION_ENABLED,

       ARM_VE_SMB_NOR0_BASE,0,

-      TZASC_REGION_SIZE_64MB, TZASC_REGION_SECURITY_NSRW);

+      TZASC_REGION_SIZE_64MB, TZASC_REGION_SECURITY_NSRW, 0);

 

   // NOR Flash 1. The first half of the NOR Flash1 must be secure for the secure firmware (sec_uefi.bin)

   if (PcdGetBool (PcdTrustzoneSupport) == TRUE) {

     //Note: Your OS Kernel must be aware of the secure regions before to enable this region

     TZASCSetRegion(ARM_VE_TZASC_BASE,2,TZASC_REGION_ENABLED,

         ARM_VE_SMB_NOR1_BASE + SIZE_32MB,0,

-        TZASC_REGION_SIZE_32MB, TZASC_REGION_SECURITY_NSRW);

+        TZASC_REGION_SIZE_32MB, TZASC_REGION_SECURITY_NSRW, 0);

   } else {

     TZASCSetRegion(ARM_VE_TZASC_BASE,2,TZASC_REGION_ENABLED,

         ARM_VE_SMB_NOR1_BASE,0,

-        TZASC_REGION_SIZE_64MB, TZASC_REGION_SECURITY_NSRW);

+        TZASC_REGION_SIZE_64MB, TZASC_REGION_SECURITY_NSRW, 0);

   }

 

   // Base of SRAM. Only half of SRAM in Non Secure world

@@ -92,22 +92,22 @@ ArmPlatformSecTrustzoneInit (
     //Note: Your OS Kernel must be aware of the secure regions before to enable this region

     TZASCSetRegion(ARM_VE_TZASC_BASE,3,TZASC_REGION_ENABLED,

         ARM_VE_SMB_SRAM_BASE,0,

-        TZASC_REGION_SIZE_16MB, TZASC_REGION_SECURITY_NSRW);

+        TZASC_REGION_SIZE_16MB, TZASC_REGION_SECURITY_NSRW, 0);

   } else {

     TZASCSetRegion(ARM_VE_TZASC_BASE,3,TZASC_REGION_ENABLED,

         ARM_VE_SMB_SRAM_BASE,0,

-        TZASC_REGION_SIZE_32MB, TZASC_REGION_SECURITY_NSRW);

+        TZASC_REGION_SIZE_32MB, TZASC_REGION_SECURITY_NSRW, 0);

   }

 

   // Memory Mapped Peripherals. All in non secure world

   TZASCSetRegion(ARM_VE_TZASC_BASE,4,TZASC_REGION_ENABLED,

       ARM_VE_SMB_PERIPH_BASE,0,

-      TZASC_REGION_SIZE_64MB, TZASC_REGION_SECURITY_NSRW);

+      TZASC_REGION_SIZE_64MB, TZASC_REGION_SECURITY_NSRW, 0);

 

   // MotherBoard Peripherals and On-chip peripherals.

   TZASCSetRegion(ARM_VE_TZASC_BASE,5,TZASC_REGION_ENABLED,

       ARM_VE_SMB_MB_ON_CHIP_PERIPH_BASE,0,

-      TZASC_REGION_SIZE_256MB, TZASC_REGION_SECURITY_NSRW);

+      TZASC_REGION_SIZE_256MB, TZASC_REGION_SECURITY_NSRW, 0);

 }

 

 /**