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| author | Dennis Chen <dennis.chen@arm.com> | 2016-09-05 19:38:20 +0800 |
|---|---|---|
| committer | Ard Biesheuvel <ard.biesheuvel@linaro.org> | 2016-09-08 09:16:01 +0100 |
| commit | 8a1f2378d74390ddfe35c70f68e0c8b03bf84089 (patch) | |
| tree | a14e94339ee014e9680f2629fd80c208eea08bfd /ArmPlatformPkg/Library/DebugSecExtraActionLib/DebugSecExtraActionLib.c | |
| parent | d796d33f1844deb492bc571c7f2e2b6780b92368 (diff) | |
| download | edk2-platforms-8a1f2378d74390ddfe35c70f68e0c8b03bf84089.tar.xz | |
ArmPkg ArmPlatformPkg ArmVirtPkg: ARM GICv2/v3 Base Address width fix-up
According to the ACPI 6.0/6.1 spec, the physical base address of GICC,
GICD, GICR and GIC ITS is 64-bit. So change the type of the various GIC
base address PCDs to 64-bit, and fix up all users.
Contributed-under: TianoCore Contribution Agreement 1.0
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Signed-off-by: Dennis Chen <dennis.chen@arm.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Diffstat (limited to 'ArmPlatformPkg/Library/DebugSecExtraActionLib/DebugSecExtraActionLib.c')
| -rw-r--r-- | ArmPlatformPkg/Library/DebugSecExtraActionLib/DebugSecExtraActionLib.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/ArmPlatformPkg/Library/DebugSecExtraActionLib/DebugSecExtraActionLib.c b/ArmPlatformPkg/Library/DebugSecExtraActionLib/DebugSecExtraActionLib.c index a452e38751..e617bdaa9c 100644 --- a/ArmPlatformPkg/Library/DebugSecExtraActionLib/DebugSecExtraActionLib.c +++ b/ArmPlatformPkg/Library/DebugSecExtraActionLib/DebugSecExtraActionLib.c @@ -40,11 +40,11 @@ NonSecureWaitForFirmware ( ArmCallWFI ();
// Acknowledge the interrupt and send End of Interrupt signal.
- AcknowledgeInterrupt = ArmGicAcknowledgeInterrupt (PcdGet32 (PcdGicInterruptInterfaceBase), &InterruptId);
+ AcknowledgeInterrupt = ArmGicAcknowledgeInterrupt (PcdGet64 (PcdGicInterruptInterfaceBase), &InterruptId);
// Check if it is a valid interrupt ID
- if (InterruptId < ArmGicGetMaxNumInterrupts (PcdGet32 (PcdGicDistributorBase))) {
+ if (InterruptId < ArmGicGetMaxNumInterrupts (PcdGet64 (PcdGicDistributorBase))) {
// Got a valid SGI number hence signal End of Interrupt
- ArmGicEndOfInterrupt (PcdGet32 (PcdGicInterruptInterfaceBase), AcknowledgeInterrupt);
+ ArmGicEndOfInterrupt (PcdGet64 (PcdGicInterruptInterfaceBase), AcknowledgeInterrupt);
}
// Jump to secondary core entry point.
@@ -105,7 +105,7 @@ ArmPlatformSecExtraAction ( if (ArmPlatformIsPrimaryCore (MpId)) {
// Signal the secondary cores they can jump to PEI phase
- ArmGicSendSgiTo (PcdGet32 (PcdGicDistributorBase), ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E, PcdGet32 (PcdGicSgiIntId));
+ ArmGicSendSgiTo (PcdGet64 (PcdGicDistributorBase), ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E, PcdGet32 (PcdGicSgiIntId));
// To enter into Non Secure state, we need to make a return from exception
*JumpAddress = PcdGet64 (PcdFvBaseAddress);
|