diff options
| author | oliviermartin <oliviermartin@6f19259b-4bc3-4df7-8a09-765794883524> | 2011-08-18 10:06:38 +0000 |
|---|---|---|
| committer | oliviermartin <oliviermartin@6f19259b-4bc3-4df7-8a09-765794883524> | 2011-08-18 10:06:38 +0000 |
| commit | 9e4a626c06f506475b1852ca38f1d03c120b4803 (patch) | |
| tree | c69575bf124d0d5bd79066c33645d0c390c9adac /ArmPlatformPkg/Library | |
| parent | 5ec65e96b29b96074b40fb093e8c3cdf65b78a8a (diff) | |
| download | edk2-platforms-9e4a626c06f506475b1852ca38f1d03c120b4803.tar.xz | |
ArmPlatformPkg/SP804TimerLib: Fixed macro timer base addresses
The base address for the Metronome and Performance timer were reverted.
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@12162 6f19259b-4bc3-4df7-8a09-765794883524
Diffstat (limited to 'ArmPlatformPkg/Library')
| -rw-r--r-- | ArmPlatformPkg/Library/SP804TimerLib/SP804TimerLib.c | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/ArmPlatformPkg/Library/SP804TimerLib/SP804TimerLib.c b/ArmPlatformPkg/Library/SP804TimerLib/SP804TimerLib.c index f3bb177c74..da37dfabfd 100644 --- a/ArmPlatformPkg/Library/SP804TimerLib/SP804TimerLib.c +++ b/ArmPlatformPkg/Library/SP804TimerLib/SP804TimerLib.c @@ -21,8 +21,8 @@ #include <Library/IoLib.h> #include <Drivers/SP804Timer.h> -#define SP804_TIMER_METRONOME_BASE (UINTN)PcdGet32 (PcdSP804TimerPerformanceBase) -#define SP804_TIMER_PERFORMANCE_BASE (UINTN)PcdGet32 (PcdSP804TimerMetronomeBase) +#define SP804_TIMER_METRONOME_BASE ((UINTN)PcdGet32 (PcdSP804TimerMetronomeBase)) +#define SP804_TIMER_PERFORMANCE_BASE ((UINTN)PcdGet32 (PcdSP804TimerPerformanceBase)) // Setup SP810's Timer2 for managing delay functions. And Timer3 for Performance counter // Note: ArmVE's Timer0 and Timer1 are used by TimerDxe. @@ -32,11 +32,11 @@ TimerConstructor ( VOID ) { - // Check if Timer 2 is already initialized + // Check if the Metronome Timer is already initialized if (MmioRead32(SP804_TIMER_METRONOME_BASE + SP804_TIMER_CONTROL_REG) & SP804_TIMER_CTRL_ENABLE) { return RETURN_SUCCESS; } else { - // Configure timer 2 for one shot operation, 32 bits, no prescaler, and interrupt disabled + // Configure the Metronome Timer for one shot operation, 32 bits, no prescaler, and interrupt disabled MmioOr32 (SP804_TIMER_METRONOME_BASE + SP804_TIMER_CONTROL_REG, SP804_TIMER_CTRL_ONESHOT | SP804_TIMER_CTRL_32BIT | SP804_PRESCALE_DIV_1); // Preload the timer count register @@ -46,14 +46,14 @@ TimerConstructor ( MmioOr32 (SP804_TIMER_METRONOME_BASE + SP804_TIMER_CONTROL_REG, SP804_TIMER_CTRL_ENABLE); } - // Check if Timer 3 is already initialized + // Check if the Performance Timer is already initialized if (MmioRead32(SP804_TIMER_PERFORMANCE_BASE + SP804_TIMER_CONTROL_REG) & SP804_TIMER_CTRL_ENABLE) { return RETURN_SUCCESS; } else { - // Configure timer 3 for free running operation, 32 bits, no prescaler, interrupt disabled + // Configure the Performance timer for free running operation, 32 bits, no prescaler, interrupt disabled MmioOr32 (SP804_TIMER_PERFORMANCE_BASE + SP804_TIMER_CONTROL_REG, SP804_TIMER_CTRL_32BIT | SP804_PRESCALE_DIV_1); - // Enable the timer + // Start the Performance Timer ticking MmioOr32 (SP804_TIMER_PERFORMANCE_BASE + SP804_TIMER_CONTROL_REG, SP804_TIMER_CTRL_ENABLE); } |