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| author | Ard Biesheuvel <ard.biesheuvel@linaro.org> | 2015-11-09 13:26:52 +0000 |
|---|---|---|
| committer | abiesheuvel <abiesheuvel@Edk2> | 2015-11-09 13:26:52 +0000 |
| commit | fbf658ebc8e2e9340b036b16f2c94403696df1c0 (patch) | |
| tree | 9f977ab11e8de671715a0ac3e429a28be7f2c315 /BaseTools/Source/Python/AutoGen/BuildEngine.py | |
| parent | f97ab1bbf4c4512e1aabd149527c1aa4d5b0c03b (diff) | |
| download | edk2-platforms-fbf658ebc8e2e9340b036b16f2c94403696df1c0.tar.xz | |
ArmPkg/ArmLib: retrieve cache line length from CTR not CCSIDR
The stride used by the cache maintenance by MVA instructions should
be retrieved from CTR_EL0.DminLine and CTR_EL0.IminLine, whose values
reflect the actual geometry of the caches. Using CCSIDR for this purpose
violates the architecture.
Also, move the line length accessors to common code, since there is no
need to keep them separate between ARMv7 and AArch64.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Mark Rutland <mark.rutland@arm.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18754 6f19259b-4bc3-4df7-8a09-765794883524
Diffstat (limited to 'BaseTools/Source/Python/AutoGen/BuildEngine.py')
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