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| author | Hao Wu <hao.a.wu@intel.com> | 2016-12-08 16:35:56 +0800 |
|---|---|---|
| committer | Hao Wu <hao.a.wu@intel.com> | 2016-12-16 11:48:12 +0800 |
| commit | 37cea63f171260cf5283bbfa63b9be4a14941914 (patch) | |
| tree | 72b2a5ed066b1d35df66bccaa6923b51dbee249a /BaseTools/Source/Python/AutoGen/InfSectionParser.py | |
| parent | 0f16be6d9eef371d6ed1e45422748ae0fb49652f (diff) | |
| download | edk2-platforms-37cea63f171260cf5283bbfa63b9be4a14941914.tar.xz | |
UefiCpuPkg/Include: Update Skylake MSR header file with SDM (Sep.2016)
https://bugzilla.tianocore.org/show_bug.cgi?id=176
Update the MSR header file of Skylake processor according to Intel(R) 64
and IA-32 Architectures Software Developer's Manual, Volume 3, September
2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.15.
Summary of incompatible changes:
1. MSR (address 38EH) IA32_PERF_GLOBAL_STAUS has been renamed to
IA32_PERF_GLOBAL_STATUS
Typo 'STAUS' has been fixed in SDM.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Hao Wu <hao.a.wu@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Diffstat (limited to 'BaseTools/Source/Python/AutoGen/InfSectionParser.py')
0 files changed, 0 insertions, 0 deletions