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| author | Maurice Ma <maurice.ma@intel.com> | 2016-05-26 15:13:23 -0700 |
|---|---|---|
| committer | Maurice Ma <maurice.ma@intel.com> | 2016-05-27 14:28:37 -0700 |
| commit | 8a3a97814e5402840164cb53ad6bb12ed851c54e (patch) | |
| tree | 5fc73e06d9e218cd3cff50bd72d7f8b6b052ca98 /BaseTools/Source/Python/CommonDataClass/ModuleClass.py | |
| parent | ee70e58bd28a1bd6decf173a98b85c6e7066b486 (diff) | |
| download | edk2-platforms-8a3a97814e5402840164cb53ad6bb12ed851c54e.tar.xz | |
CorebootModulePkg/PciHostBridgeLib: Fix PCI 64bit memory BAR size issue
The current PCI 64bit memory BAR size calculation in PciHostBridgeLib
assumes all 32 bits in the upper BAR are fully writable. However,
platform might only support partial address programming, such as 40bit
PCI BAR address. In this case the complement cannot be used for size
calculation. Instead, the lowest non-zero bit should be used for BAR
size calculation.
Cc: Prince Agyeman <prince.agyeman@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Reviewed-by: Prince Agyeman <prince.agyeman@intel.com>
Diffstat (limited to 'BaseTools/Source/Python/CommonDataClass/ModuleClass.py')
0 files changed, 0 insertions, 0 deletions