diff options
| author | Guo Mang <mang.guo@intel.com> | 2016-08-03 10:05:36 +0800 |
|---|---|---|
| committer | Guo Mang <mang.guo@intel.com> | 2016-08-04 10:30:31 +0800 |
| commit | 1ba4ff338446b5db2a0b41b4c84a03a431b0cb33 (patch) | |
| tree | 61cd2606269623a3bb916ecec5c7ff241daf077c /BraswellPlatformPkg/Common | |
| parent | 6c4214e6890ab7f1adc8a8c43b74dcba88a673e5 (diff) | |
| download | edk2-platforms-1ba4ff338446b5db2a0b41b4c84a03a431b0cb33.tar.xz | |
BraswellPlatformPkg: Move Include to Common/Include
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Guo Mang <mang.guo@intel.com>
Reviewed-by: David Wei <david.wei@intel.com>
Diffstat (limited to 'BraswellPlatformPkg/Common')
38 files changed, 6359 insertions, 0 deletions
diff --git a/BraswellPlatformPkg/Common/Include/BuildVariables.h b/BraswellPlatformPkg/Common/Include/BuildVariables.h new file mode 100644 index 0000000000..299b4515ed --- /dev/null +++ b/BraswellPlatformPkg/Common/Include/BuildVariables.h @@ -0,0 +1,301 @@ +#define A16_INV_BLOCK_ADDR 0xfffe0000 // 4294836224
+#define A16_INV_CHK_AREA_BASE_ADDR 0xfffefff0 // 4294901744
+#define A16_INV_CHK_AREA_BINARY "C:\\Haswell_labeled\\R8VlvDevicePkg\\Platform\\Features\\Flash\\A16InvCheckBin\\A16InvCheck.bin"
+#define L_A16_INV_CHK_AREA_BINARY L"C:\\Haswell_labeled\\R8VlvDevicePkg\\Platform\\Features\\Flash\\A16InvCheckBin\\A16InvCheck.bin"
+#define A16_INV_CHK_AREA_SIZE 0x10 // 16
+#define ALWAYS_DISABLE_ONBOARD_VIDEO 0x0 // 0
+#define AMT 0x0 // 0
+#define AMT_VERSION 0x30000 // 196608
+#define ASCII_TO_UNICODE "C:\\Haswell_labeled\\R8VlvDevicePkg\\Tools\\Bin\\Python\\Ia32\\python.exe C:\\Haswell_labeled\\R8VlvDevicePkg\\Tools\\Dpsd\\AsciiToUnicode.py"
+#define L_ASCII_TO_UNICODE L"C:\\Haswell_labeled\\R8VlvDevicePkg\\Tools\\Bin\\Python\\Ia32\\python.exe C:\\Haswell_labeled\\R8VlvDevicePkg\\Tools\\Dpsd\\AsciiToUnicode.py"
+#define AUXILIARYBLOCK_BINARY "C:\\Haswell_labeled\\R8VlvDevicePkg\\Build\\Fv\\AuxiliaryCompact.fv"
+#define L_AUXILIARYBLOCK_BINARY L"C:\\Haswell_labeled\\R8VlvDevicePkg\\Build\\Fv\\AuxiliaryCompact.fv"
+#define BACKUPBLOCK_BINARY "C:\\Haswell_labeled\\R8VlvDevicePkg\\Build\\X64\\BackupBlock.bin"
+#define L_BACKUPBLOCK_BINARY L"C:\\Haswell_labeled\\R8VlvDevicePkg\\Build\\X64\\BackupBlock.bin"
+#define BACKUPBLOCK_BUILDER "C:\\Haswell_labeled\\R8VlvDevicePkg\\Tools\\Bin\\Python\\Ia32\\python.exe C:\\Haswell_labeled\\R8VlvDevicePkg\\Tools\\Dpsd\\BackupBlockBuilder.py"
+#define L_BACKUPBLOCK_BUILDER L"C:\\Haswell_labeled\\R8VlvDevicePkg\\Tools\\Bin\\Python\\Ia32\\python.exe C:\\Haswell_labeled\\R8VlvDevicePkg\\Tools\\Dpsd\\BackupBlockBuilder.py"
+#define BACKUP_FT_STATE_BASE_ADDR 0xfff24000 // 4293935104
+#define BEARLAKE_TYPE ""
+#define L_BEARLAKE_TYPE L""
+#define BIOS_PRODUCT_BUILD 0x1 // 1
+#define BOOTBLOCK2_BACKUP_BASE_ADDR 0xfff90000 // 4294508544
+#define BOOTBLOCK2_BASE_ADDR 0xfff10000 // 4293984256
+#define BOOTBLOCK2_BINARY "C:\\Haswell_labeled\\R8VlvDevicePkg\\Build\\Fv\\BootBlock2.fv"
+#define L_BOOTBLOCK2_BINARY L"C:\\Haswell_labeled\\R8VlvDevicePkg\\Build\\Fv\\BootBlock2.fv"
+#define BOOTBLOCK2_SIZE 0x20000 // 131072
+#define BOOTBLOCK_BASE_ADDR 0xffff0000 // 4294901760
+#define BOOTBLOCK_BINARY "C:\\Haswell_labeled\\R8VlvDevicePkg\\Build\\Fv\\FvRecovery.fv"
+#define L_BOOTBLOCK_BINARY L"C:\\Haswell_labeled\\R8VlvDevicePkg\\Build\\Fv\\FvRecovery.fv"
+#define BOOTBLOCK_SIZE 0x10000 // 65536
+#define BUILD_CVT 0x0 // 0
+#define BUILD_DIR "C:\\Haswell_labeled\\R8VlvDevicePkg\\Build"
+#define L_BUILD_DIR L"C:\\Haswell_labeled\\R8VlvDevicePkg\\Build"
+#define BUILD_INTERMEDIATE_DEBUG_FILE "True"
+#define L_BUILD_INTERMEDIATE_DEBUG_FILE L"True"
+#define BUILD_MAKE_FILE "C:\\Haswell_labeled\\R8VlvDevicePkg\\Tools\\Dpsd\\Build.mak"
+#define L_BUILD_MAKE_FILE L"C:\\Haswell_labeled\\R8VlvDevicePkg\\Tools\\Dpsd\\Build.mak"
+#define BUILD_OUTPUT_DIR "C:\\Haswell_labeled\\R8VlvDevicePkg\\Build\\X64"
+#define L_BUILD_OUTPUT_DIR L"C:\\Haswell_labeled\\R8VlvDevicePkg\\Build\\X64"
+#define BUILD_QUALITY_DIGIT "C"
+#define L_BUILD_QUALITY_DIGIT L"C"
+#define BUILD_RST 0x0 // 0
+#define BUILD_TARGET_PROCESSOR "X64"
+#define L_BUILD_TARGET_PROCESSOR L"X64"
+#define BUILD_THREAD_NUMBER "8"
+#define L_BUILD_THREAD_NUMBER L"8"
+#define BURN_IN_MODE_SUPPORTED 0x0 // 0
+#define CAPSULE_MICROCODES_BINARY "C:\\Haswell_labeled\\R8VlvDevicePkg\\Build\\X64\\CapsuleMicrocodes.bin"
+#define L_CAPSULE_MICROCODES_BINARY L"C:\\Haswell_labeled\\R8VlvDevicePkg\\Build\\X64\\CapsuleMicrocodes.bin"
+#define CAPSULE_SIGNATURE_PACKAGING "Crc32SignedFv"
+#define L_CAPSULE_SIGNATURE_PACKAGING L"Crc32SignedFv"
+#define CAPSULE_SIGNING_METHOD "CRC32"
+#define L_CAPSULE_SIGNING_METHOD L"CRC32"
+#define CDVMICROCODEBLOCK_BASE_ADDR 0xfffe0000 // 4294836224
+#define CDVMICROCODEBLOCK_BINARY "C:\\Haswell_labeled\\R8VlvDevicePkg\\Chipset\\CherryView\\CDVMicrocode\\CDVMicrocode.bin"
+#define L_CDVMICROCODEBLOCK_BINARY L"C:\\Haswell_labeled\\R8VlvDevicePkg\\Chipset\\CherryView\\CDVMicrocode\\CDVMicrocode.bin"
+#define CDVMICROCODEBLOCK_SIZE 0xfff0 // 65520
+#define CHIPSET_IO_CONTROLLER "SouthCluster"
+#define L_CHIPSET_IO_CONTROLLER L"SouthCluster"
+#define CHIPSET_IO_CONTROLLER_DIR "C:\\Haswell_labeled\\R8VlvDevicePkg\\Chipset\\SouthCluster"
+#define L_CHIPSET_IO_CONTROLLER_DIR L"C:\\Haswell_labeled\\R8VlvDevicePkg\\Chipset\\SouthCluster"
+#define CHIPSET_LAN_DEVICE "Lan"
+#define L_CHIPSET_LAN_DEVICE L"Lan"
+#define CHIPSET_MEMORY_CONTROLLER "CherryView"
+#define L_CHIPSET_MEMORY_CONTROLLER L"CherryView"
+#define CHIPSET_MEMORY_CONTROLLER_DIR "C:\\Haswell_labeled\\R8VlvDevicePkg\\Chipset\\CherryView"
+#define L_CHIPSET_MEMORY_CONTROLLER_DIR L"C:\\Haswell_labeled\\R8VlvDevicePkg\\Chipset\\CherryView"
+#define CHIPSET_SIO_CONTROLLER "WPCE791"
+#define L_CHIPSET_SIO_CONTROLLER L"WPCE791"
+#define COM1_PORT_PRESENT 0x1 // 1
+#define COM2_PORT_PRESENT 0x1 // 1
+#define CPU_ARCH "CherryView"
+#define L_CPU_ARCH L"CherryView"
+#define CREATE_ATE_INFO "C:\\Haswell_labeled\\R8VlvDevicePkg\\Tools\\Bin\\Python\\Ia32\\python.exe C:\\Haswell_labeled\\R8VlvDevicePkg\\Tools\\Dpsd\\CreateAteInfo.py"
+#define L_CREATE_ATE_INFO L"C:\\Haswell_labeled\\R8VlvDevicePkg\\Tools\\Bin\\Python\\Ia32\\python.exe C:\\Haswell_labeled\\R8VlvDevicePkg\\Tools\\Dpsd\\CreateAteInfo.py"
+#define CREATE_BDFINFO "C:\\Haswell_labeled\\R8VlvDevicePkg\\Tools\\Bin\\Python\\Ia32\\python.exe C:\\Haswell_labeled\\R8VlvDevicePkg\\Tools\\Dpsd\\CreateBdfInfo.py"
+#define L_CREATE_BDFINFO L"C:\\Haswell_labeled\\R8VlvDevicePkg\\Tools\\Bin\\Python\\Ia32\\python.exe C:\\Haswell_labeled\\R8VlvDevicePkg\\Tools\\Dpsd\\CreateBdfInfo.py"
+#define CREATE_DPSD_CAPSULE "C:\\Haswell_labeled\\R8VlvDevicePkg\\Tools\\Bin\\Python\\Ia32\\python.exe C:\\Haswell_labeled\\R8VlvDevicePkg\\Tools\\Dpsd\\CreateDpsdCapsule.py"
+#define L_CREATE_DPSD_CAPSULE L"C:\\Haswell_labeled\\R8VlvDevicePkg\\Tools\\Bin\\Python\\Ia32\\python.exe C:\\Haswell_labeled\\R8VlvDevicePkg\\Tools\\Dpsd\\CreateDpsdCapsule.py"
+#define CREATE_ITK_MAP_FILE "C:\\Haswell_labeled\\R8VlvDevicePkg\\Tools\\Bin\\Python\\Ia32\\python.exe C:\\Haswell_labeled\\R8VlvDevicePkg\\Tools\\Dpsd\\CreateItkMapFile.py"
+#define L_CREATE_ITK_MAP_FILE L"C:\\Haswell_labeled\\R8VlvDevicePkg\\Tools\\Bin\\Python\\Ia32\\python.exe C:\\Haswell_labeled\\R8VlvDevicePkg\\Tools\\Dpsd\\CreateItkMapFile.py"
+#define CREATE_MICROCODE_BIN_FILE "C:\\Haswell_labeled\\R8VlvDevicePkg\\Tools\\Bin\\Python\\Ia32\\python.exe C:\\Haswell_labeled\\R8VlvDevicePkg\\Tools\\Dpsd\\CreateMicrocodeBinFile.py"
+#define L_CREATE_MICROCODE_BIN_FILE L"C:\\Haswell_labeled\\R8VlvDevicePkg\\Tools\\Bin\\Python\\Ia32\\python.exe C:\\Haswell_labeled\\R8VlvDevicePkg\\Tools\\Dpsd\\CreateMicrocodeBinFile.py"
+#define CVT_RST_BUILDER "C:\\Haswell_labeled\\R8VlvDevicePkg\\Tools\\Bin\\Python\\Ia32\\python.exe C:\\Haswell_labeled\\R8VlvDevicePkg\\Tools\\Dpsd\\CvtRst.py"
+#define L_CVT_RST_BUILDER L"C:\\Haswell_labeled\\R8VlvDevicePkg\\Tools\\Bin\\Python\\Ia32\\python.exe C:\\Haswell_labeled\\R8VlvDevicePkg\\Tools\\Dpsd\\CvtRst.py"
+#define DISPLAY_ROM_USAGE "C:\\Haswell_labeled\\R8VlvDevicePkg\\Tools\\Bin\\Python\\Ia32\\python.exe C:\\Haswell_labeled\\R8VlvDevicePkg\\Tools\\Dpsd\\RomSpaceUsage.py"
+#define L_DISPLAY_ROM_USAGE L"C:\\Haswell_labeled\\R8VlvDevicePkg\\Tools\\Bin\\Python\\Ia32\\python.exe C:\\Haswell_labeled\\R8VlvDevicePkg\\Tools\\Dpsd\\RomSpaceUsage.py"
+#define DPSD_FEATURES_DIR "C:\\Haswell_labeled\\R8VlvDevicePkg\\Platform\\Features"
+#define L_DPSD_FEATURES_DIR L"C:\\Haswell_labeled\\R8VlvDevicePkg\\Platform\\Features"
+#define DPSD_FLASH_DIR "C:\\Haswell_labeled\\R8VlvDevicePkg\\Platform\\Features\\Flash"
+#define L_DPSD_FLASH_DIR L"C:\\Haswell_labeled\\R8VlvDevicePkg\\Platform\\Features\\Flash"
+#define DPSD_MICROCODE_DIR "C:\\Haswell_labeled\\R8VlvDevicePkg\\Platform\\Features\\Microcode"
+#define L_DPSD_MICROCODE_DIR L"C:\\Haswell_labeled\\R8VlvDevicePkg\\Platform\\Features\\Microcode"
+#define DPSD_TOOLS_DIR "C:\\Haswell_labeled\\R8VlvDevicePkg\\Tools\\Dpsd"
+#define L_DPSD_TOOLS_DIR L"C:\\Haswell_labeled\\R8VlvDevicePkg\\Tools\\Dpsd"
+#define DRIVER_FAILING_X64_BUILD "#X64 BUILD FAILURE#"
+#define L_DRIVER_FAILING_X64_BUILD L"#X64 BUILD FAILURE#"
+#define DSDT_OEM_ID "INTEL "
+#define L_DSDT_OEM_ID L"INTEL "
+#define DSDT_OEM_TABLE_ID "INTEL "
+#define L_DSDT_OEM_TABLE_ID L"INTEL "
+#define DT_PLAT 0x1 // 1
+#define EBU_BUILD_DIR "C:\\Haswell_labeled\\R8VlvDevicePkg\\Build\\EbuBuild"
+#define L_EBU_BUILD_DIR L"C:\\Haswell_labeled\\R8VlvDevicePkg\\Build\\EbuBuild"
+#define EDK_SOURCE "C:\\Haswell_labeled\\R8VlvDevicePkg\\Edk"
+#define L_EDK_SOURCE L"C:\\Haswell_labeled\\R8VlvDevicePkg\\Edk"
+//#define EFI_ACPI_OEM_ID 0x204c45544e49 // 35511952756297
+//#define EFI_ACPI_OEM_TABLE_ID 0x2020574d35323544 // 2314946197585016132
+#define EFI_ACPI_OEM_TABLE_ID_KT 0x2020544b35323444 // 2314942890460197956
+#define EFI_DEBUG_FLAG "YES"
+#define L_EFI_DEBUG_FLAG L"YES"
+#define EFI_GENERATE_HII_EXPORT "YES"
+#define L_EFI_GENERATE_HII_EXPORT L"YES"
+//#define EFI_MEMORY_INIT 0x1 // 1
+#define EFI_SOURCE "C:\\Haswell_labeled\\R8VlvDevicePkg"
+#define L_EFI_SOURCE L"C:\\Haswell_labeled\\R8VlvDevicePkg"
+#define EFI_UNLOCK_FWH 0x1 // 1
+#define EFI_USB_NATIVE_START_PROTOCOL_SUPPORT 0x1 // 1
+#define EMBEDDED_CONTROLLER_SUPPORT 0x0 // 0
+#define ERASE_TO_FORCE_RECOVERY_BASE_ADDR 0xfff30000 // 4294115328
+#define ERASE_TO_FORCE_RECOVERY_SIZE 0x1000 // 4096
+#define FINAL_OUTPUT_DIR "C:\\Haswell_labeled\\R8VlvDevicePkg\\Build"
+#define L_FINAL_OUTPUT_DIR L"C:\\Haswell_labeled\\R8VlvDevicePkg\\Build"
+#define FIRMWARE_ID_BASE 0xffffffe4 // 4294967268
+#define FLASH_BASE_ADDRESS 0xffe00000 // 4292870144
+#define FLASH_BLOCK_SIZE 0x10000 // 65536
+#define FLASH_CONFIG "16M-8"
+#define L_FLASH_CONFIG L"16M-8"
+#define FLASH_CONFIGURATION_LIST "RESERVED1,VPDBLOCK,VPD_BACKUP,MICROCODEBLOCK,BOOTBLOCK2,MAINBLOCK,CDVMICROCODEBLOCK,A16_INV_CHK_AREA,BOOTBLOCK"
+#define L_FLASH_CONFIGURATION_LIST L"RESERVED1,VPDBLOCK,VPD_BACKUP,MICROCODEBLOCK,BOOTBLOCK2,MAINBLOCK,CDVMICROCODEBLOCK,A16_INV_CHK_AREA,BOOTBLOCK"
+#define FLASH_CONFIG_DIR "C:\\Haswell_labeled\\R8VlvDevicePkg\\Platform\\Features\\Flash\\Config\\16M-8"
+#define L_FLASH_CONFIG_DIR L"C:\\Haswell_labeled\\R8VlvDevicePkg\\Platform\\Features\\Flash\\Config\\16M-8"
+#define FLASH_END_ADDRESS 0x100000000 // 4294967296
+#define FLASH_NO_REBOOT_METHOD_SUPPORTED 0x0 // 0
+#define FLASH_SIZE 0x200000 // 2097152
+#define FLASH_SIZE_LOG2 0x15 // 21
+#define FLEX_CAPSULE "C:\\Haswell_labeled\\R8VlvDevicePkg\\Tools\\Bin\\Python\\Ia32\\python.exe C:\\Haswell_labeled\\R8VlvDevicePkg\\Tools\\Dpsd\\FlexCapsule.py"
+#define L_FLEX_CAPSULE L"C:\\Haswell_labeled\\R8VlvDevicePkg\\Tools\\Bin\\Python\\Ia32\\python.exe C:\\Haswell_labeled\\R8VlvDevicePkg\\Tools\\Dpsd\\FlexCapsule.py"
+#define FLEX_PAYLOAD "C:\\Haswell_labeled\\R8VlvDevicePkg\\Tools\\Bin\\Python\\Ia32\\python.exe C:\\Haswell_labeled\\R8VlvDevicePkg\\Tools\\Dpsd\\FlexPayload.py"
+#define L_FLEX_PAYLOAD L"C:\\Haswell_labeled\\R8VlvDevicePkg\\Tools\\Bin\\Python\\Ia32\\python.exe C:\\Haswell_labeled\\R8VlvDevicePkg\\Tools\\Dpsd\\FlexPayload.py"
+#define FLEX_PLAIN_UPDATE_CODE "C:\\Haswell_labeled\\R8VlvDevicePkg\\Tools\\Dpsd\\FlexPlainImageUpdateCode.rex"
+#define L_FLEX_PLAIN_UPDATE_CODE L"C:\\Haswell_labeled\\R8VlvDevicePkg\\Tools\\Dpsd\\FlexPlainImageUpdateCode.rex"
+#define FLOPPY_PRESENT 0x0 // 0
+#define FV_OUTPUT_DIR "C:\\Haswell_labeled\\R8VlvDevicePkg\\Build\\Fv"
+#define L_FV_OUTPUT_DIR L"C:\\Haswell_labeled\\R8VlvDevicePkg\\Build\\Fv"
+#define GPIO_BOARD_ID_SUPPORT 0x1 // 1
+#define HECETA_SUPPORT 0x0 // 0
+#define HF_BIOS_DEBUG_MODE 0x0 // 0
+#define HIIPACK "C:\\Haswell_labeled\\R8VlvDevicePkg\\Build\\Tools\\HiiPack"
+#define L_HIIPACK L"C:\\Haswell_labeled\\R8VlvDevicePkg\\Build\\Tools\\HiiPack"
+#define HW_WATCHDOG_TIMER_SUPPORT 0x0 // 0
+#define IA32_ONLY_MODULE "#IA32 ONLY MODULE#"
+#define L_IA32_ONLY_MODULE L"#IA32 ONLY MODULE#"
+#define ICH_RAID_SKU "IBX"
+#define L_ICH_RAID_SKU L"IBX"
+#define IDCC2_SUPPORTED 0x0 // 0
+#define LANG_DEFAULT "eng,uqi"
+#define L_LANG_DEFAULT L"eng,uqi"
+#define LPT_PORT_PRESENT 0x1 // 1
+#define LT_SUPPORT 0x0 // 0
+#define MAINBLOCK_BASE_ADDR 0xffe00000 // 4294115328
+#define MAINBLOCK_BINARY "C:\\Haswell_labeled\\R8VlvDevicePkg\\Build\\Fv\\FvMainCompact.fv"
+#define L_MAINBLOCK_BINARY L"C:\\Haswell_labeled\\R8VlvDevicePkg\\Build\\Fv\\FvMainCompact.fv"
+#define MAINBLOCK_SIZE 0x120000 // 720896
+#define MANAGEABILITY_ENGINE_BIN_DIR "C:\\Haswell_labeled\\R8VlvDevicePkg\\Chipset\\CherryView\\ManageabilityEngine\\Afsc"
+#define L_MANAGEABILITY_ENGINE_BIN_DIR L"C:\\Haswell_labeled\\R8VlvDevicePkg\\Chipset\\CherryView\\ManageabilityEngine\\Afsc"
+#define MANAGEABILITY_ENGINE_DIR "C:\\Haswell_labeled\\R8VlvDevicePkg\\Chipset\\CherryView\\ManageabilityEngine"
+#define L_MANAGEABILITY_ENGINE_DIR L"C:\\Haswell_labeled\\R8VlvDevicePkg\\Chipset\\CherryView\\ManageabilityEngine"
+#define MB_PLAT 0x1 // 1
+#define MERGED_DSC_OUTPUT "C:\\Haswell_labeled\\R8VlvDevicePkg\\Build\\X64\\MergedOutput.dsc"
+#define L_MERGED_DSC_OUTPUT L"C:\\Haswell_labeled\\R8VlvDevicePkg\\Build\\X64\\MergedOutput.dsc"
+#define MERGE_DSC_FILES "C:\\Haswell_labeled\\R8VlvDevicePkg\\Tools\\Bin\\Python\\Ia32\\python.exe C:\\Haswell_labeled\\R8VlvDevicePkg\\Tools\\Dpsd\\MergeDscFiles.py"
+#define L_MERGE_DSC_FILES L"C:\\Haswell_labeled\\R8VlvDevicePkg\\Tools\\Bin\\Python\\Ia32\\python.exe C:\\Haswell_labeled\\R8VlvDevicePkg\\Tools\\Dpsd\\MergeDscFiles.py"
+#define ME_FW_BLOCK_BINARY "C:\\Haswell_labeled\\R8VlvDevicePkg\\Chipset\\CherryView\\ManageabilityEngine\\Afsc\\Recovery\\ME.bin"
+#define L_ME_FW_BLOCK_BINARY L"C:\\Haswell_labeled\\R8VlvDevicePkg\\Chipset\\CherryView\\ManageabilityEngine\\Afsc\\Recovery\\ME.bin"
+#define ME_LOCAL_FW_UPDATE 0x0 // 0
+#define ME_NOT_PRESENT 0x1 // 1
+#define ME_SUPPORT 0x0 // 0
+
+#define MICROCODEBLOCK_BASE_ADDR 0xFFF60000 // 4293951488
+#define MICROCODEBLOCK_BINARY "C:\\Haswell_labeled\\R8VlvDevicePkg\\Build\\X64\\RomMicrocodes.bin"
+#define L_MICROCODEBLOCK_BINARY L"C:\\Haswell_labeled\\R8VlvDevicePkg\\Build\\X64\\RomMicrocodes.bin"
+#define MICROCODEBLOCK_SIZE 0x10000 // 32768
+
+#define MINIMIZE_FV "C:\\Haswell_labeled\\R8VlvDevicePkg\\Build\\Tools\\MinimizeFv.exe"
+#define L_MINIMIZE_FV L"C:\\Haswell_labeled\\R8VlvDevicePkg\\Build\\Tools\\MinimizeFv.exe"
+#define MOBILE_BIOS 0x0 // 0
+#define MODULE_INFORMATION_OUTPUT_FILE "C:\\Haswell_labeled\\R8VlvDevicePkg\\Build\\BdfInfo.txt"
+#define L_MODULE_INFORMATION_OUTPUT_FILE L"C:\\Haswell_labeled\\R8VlvDevicePkg\\Build\\BdfInfo.txt"
+#define NIMAKBIO_SPOOF "C:\\Haswell_labeled\\R8VlvDevicePkg\\Tools\\Bin\\Python\\Ia32\\python.exe C:\\Haswell_labeled\\R8VlvDevicePkg\\Tools\\Dpsd\\NimakbioSpoof.py"
+#define L_NIMAKBIO_SPOOF L"C:\\Haswell_labeled\\R8VlvDevicePkg\\Tools\\Bin\\Python\\Ia32\\python.exe C:\\Haswell_labeled\\R8VlvDevicePkg\\Tools\\Dpsd\\NimakbioSpoof.py"
+#define OC_SUPPORT 0x0 // 0
+#define OPTIONAL_DSC_FILES 'C:\Haswell_labeled\R8VlvDevicePkg\Platform\Prod\ChipsetFamily.dsc','C:\Haswell_labeled\R8VlvDevicePkg\Platform\Prod\Drivers.dsc','C:\Haswell_labeled\R8VlvDevicePkg\Platform\Prod\ProductFamily.dsc','C:\Haswell_labeled\R8VlvDevicePkg\Platform\Prod\Product.dsc'
+#define PCIE_PORT_MAX 0x4 // 4
+#define PLATFORM_BUILD_FLAGS 0x1 // 1
+#define PLATFORM_BUILD_PARAMETER "/D DT_CONFIG /D CONFIG_UP /D CONFIG_MS /D LFD_HOST /D TSEG_SIZE=0x800000"
+#define L_PLATFORM_BUILD_PARAMETER L"/D DT_CONFIG /D CONFIG_UP /D CONFIG_MS /D LFD_HOST /D TSEG_SIZE=0x800000"
+#define PLATFORM_DIR "C:\\Haswell_labeled\\R8VlvDevicePkg\\Platform"
+#define L_PLATFORM_DIR L"C:\\Haswell_labeled\\R8VlvDevicePkg\\Platform"
+#define PLATFORM_LOCAL_STACK_SIZE 0x61a8 // 25000
+#define PLATFORM_MAX_BUS_NUM 0x3f // 63
+#define PLATFORM_OVERRIDE_MAX_BUS 0x1 // 1
+#define PLATFORM_PCIE_BASE 0xe0000000 // 3758096384
+#define PLATFORM_PCIE_BASE_SIZE 0x40 // 64
+#define PLATFORM_SUPPORTED_CPU_SOCKET_NUMBER 0x1 // 1
+#define PRE_PRODUCTION_WA_SUPPORT 0x1 // 1
+#define PROJECT_VLV_ROOT "Chipset\\CherryView"
+#define L_PROJECT_VLV_ROOT L"Chipset\\CherryView"
+#define PROJECT_SC_FAMILY "IntelPch"
+#define L_PROJECT_SC_FAMILY L"IntelPch"
+#define PROJECT_SC_ROOT "Chipset\\SouthCluster"
+#define L_PROJECT_SC_ROOT L"Chipset\\SouthCluster"
+#define PS2_PORT_PRESENT 0x1 // 1
+#define PYTHON "C:\\Haswell_labeled\\R8VlvDevicePkg\\Tools\\Bin\\Python\\Ia32\\python.exe"
+#define L_PYTHON L"C:\\Haswell_labeled\\R8VlvDevicePkg\\Tools\\Bin\\Python\\Ia32\\python.exe"
+#define R86_ONLY_MODULE ""
+#define L_R86_ONLY_MODULE L""
+#define R86_OR_NEWER_BUILD 0x1 // 1
+#define RAW_CARD_F 0x1 // 1
+#define REQUIRED_DSC_FILES 'C:\Haswell_labeled\R8VlvDevicePkg\Tools\Dpsd\Common.dsc','C:\Haswell_labeled\R8VlvDevicePkg\Platform\Common.dsc','C:\Haswell_labeled\R8VlvDevicePkg\Tools\Dpsd\Libraries.ia32.dsc','C:\Haswell_labeled\R8VlvDevicePkg\Edk\Sample\Platform\CommonX64.dsc','C:\Haswell_labeled\R8VlvDevicePkg\Tools\Dpsd\Libraries.x64.dsc'
+#define REQUIRED_PLATFROM_PROTOCOL_LIB "ProtocolLib"
+#define L_REQUIRED_PLATFROM_PROTOCOL_LIB L"ProtocolLib"
+#define RESERVED1_BASE_ADDR 0xffe00000 // 4292870144
+#define RESERVED1_SIZE 0x100000 // 1048576
+#define RESTORE_CLOCK_ON_S3_RESUME 0x1 // 1
+#define ROBSON_SUPPORT 0x0 // 0
+#define ROM_BUILDER "C:\\Haswell_labeled\\R8VlvDevicePkg\\Tools\\Bin\\Python\\Ia32\\python.exe C:\\Haswell_labeled\\R8VlvDevicePkg\\Tools\\Dpsd\\RomBuilder.py"
+#define L_ROM_BUILDER L"C:\\Haswell_labeled\\R8VlvDevicePkg\\Tools\\Bin\\Python\\Ia32\\python.exe C:\\Haswell_labeled\\R8VlvDevicePkg\\Tools\\Dpsd\\RomBuilder.py"
+#define ROM_MICROCODES_BINARY "C:\\Haswell_labeled\\R8VlvDevicePkg\\Build\\X64\\RomMicrocodes.bin"
+#define L_ROM_MICROCODES_BINARY L"C:\\Haswell_labeled\\R8VlvDevicePkg\\Build\\X64\\RomMicrocodes.bin"
+#define SECURITY_DRIVER "Edk\\Sample\\Universal\\Security\\SecurityStub\\Dxe\\SecurityStub.inf"
+#define L_SECURITY_DRIVER L"Edk\\Sample\\Universal\\Security\\SecurityStub\\Dxe\\SecurityStub.inf"
+#define SENSOR_INFO_VAR_SUPPORT 0x0 // 0
+#define SHOW_F10_BOOT_MENU 0x1 // 1
+#define SHOW_F12_NETWORK_BOOT 0x1 // 1
+#define SHOW_F7_UPDATE_BIOS 0x1 // 1
+#define SIGNBIOS_EXEC "\\\\OpsdSign\\SignClnt\\SignBios"
+#define L_SIGNBIOS_EXEC L"\\\\OpsdSign\\SignClnt\\SignBios"
+#define SIGNED_CAPSULE_SECTION_EXTRACTION_DRIVER "Edk\\Sample\\Universal\\FirmwareVolume\\GuidedSectionExtraction\\Crc32SectionExtract\\Dxe\\Crc32SectionExtract.inf"
+#define L_SIGNED_CAPSULE_SECTION_EXTRACTION_DRIVER L"Edk\\Sample\\Universal\\FirmwareVolume\\GuidedSectionExtraction\\Crc32SectionExtract\\Dxe\\Crc32SectionExtract.inf"
+#define SIO_PRESENT 0x1 // 1
+#define SMM_SUPPORT 0x1 // 1
+#define SOFTSDV_FLAG_PY "NO"
+#define L_SOFTSDV_FLAG_PY L"NO"
+#define SO_DIMM 0x1 // 1
+#define SUPPORT_DISPLAY_PORT80_IN_SCREEN 0x1 // 1
+#define SUPPORT_DISPLAY_SCROLL_BAR 0x0 // 0
+#define SUPPORT_FAST_BOOT_WITH_NO_CONFIGURATION_CHANGES 0x0 // 0
+#define SUPPORT_FORCE_RECOVERY_WITH_JUMPER 0x1 // 1
+#define SUPPORT_LEGACY_FLOPPY_FEATURE 0x1 // 1
+#define SUPPORT_LVDS_DISPLAY 0x1 // 1
+#define SUPPORT_PROCESSOR_FREQUENCY_PROGRAMMING 0x1 // 1
+#define TE_PEIM "BUILD_TYPE=TE_PEIM PACKAGE=TePeimStripped"
+#define L_TE_PEIM L"BUILD_TYPE=TE_PEIM PACKAGE=TePeimStripped"
+#define TIANO_FLEX_ITK_MAPFILE 0x1 // 1
+#define TIANO_TOOLS_OUTPUT "C:\\Haswell_labeled\\R8VlvDevicePkg\\Build\\Tools"
+#define L_TIANO_TOOLS_OUTPUT L"C:\\Haswell_labeled\\R8VlvDevicePkg\\Build\\Tools"
+#define TOKENGEN "C:\\Haswell_labeled\\R8VlvDevicePkg\\Tools\\Dpsd\\tokengen.exe"
+#define L_TOKENGEN L"C:\\Haswell_labeled\\R8VlvDevicePkg\\Tools\\Dpsd\\tokengen.exe"
+#define TOOLS_DIR "C:\\Haswell_labeled\\R8VlvDevicePkg\\Tools"
+#define L_TOOLS_DIR L"C:\\Haswell_labeled\\R8VlvDevicePkg\\Tools"
+#define TOOLS_OUTPUT_DIR "C:\\Haswell_labeled\\R8VlvDevicePkg\\Build\\Tools"
+#define L_TOOLS_OUTPUT_DIR L"C:\\Haswell_labeled\\R8VlvDevicePkg\\Build\\Tools"
+#define TOP_BLOCK_ADDR 0xffff0000 // 4294901760
+#define TURN_OFF_AA_NUMBER_CHECK 0x1 // 1
+#define TURN_OFF_BIOS_WP 0x0 // 0
+#define TURN_ON_AHCI_RAID_SUPPORT 0x0 // 0
+#define UB_DIMM 0x1 // 1
+#define USE_GLUE_LIB "SOURCE_OVERRIDE_PATH=$(EFI_SOURCE)\\Edk\\Foundation\\Library\\EdkIIGlueLib\\EntryPoints"
+#define L_USE_GLUE_LIB L"SOURCE_OVERRIDE_PATH=$(EFI_SOURCE)\\Edk\\Foundation\\Library\\EdkIIGlueLib\\EntryPoints"
+#define VARIABLE_BACKUP_BASE_ADDR 0xfff24048 // 4293935176
+#define VARIABLE_BACKUP_SIZE 0x3fb8 // 16312
+#define VARIABLE_BLOCK_BASE_ADDR 0xfff20048 // 4293918792
+#define VARIABLE_BLOCK_SIZE 0x3fb8 // 16312
+#define VPDBLOCK_BASE_ADDR 0xfff20000 // 4293918720
+#define VPDBLOCK_BINARY "C:\\Haswell_labeled\\R8VlvDevicePkg\\Build\\X64\\VpdBlock.bin"
+#define L_VPDBLOCK_BINARY L"C:\\Haswell_labeled\\R8VlvDevicePkg\\Build\\X64\\VpdBlock.bin"
+#define VPDBLOCK_SIZE 0x4000 // 16384
+#define VPD_AREAS_LIST "VPD_FV_VOL_HEADER,VARIABLE_BLOCK"
+#define L_VPD_AREAS_LIST L"VPD_FV_VOL_HEADER,VARIABLE_BLOCK"
+#define VPD_BACKUP_AREAS_LIST "VPD_BACKUP_FV_VOL_HEADER,VARIABLE_BACKUP"
+#define L_VPD_BACKUP_AREAS_LIST L"VPD_BACKUP_FV_VOL_HEADER,VARIABLE_BACKUP"
+#define VPD_BACKUP_BASE_ADDR 0xfff24000 // 4293935104
+#define VPD_BACKUP_FV_VOL_HEADER_BASE_ADDR 0xfff24000 // 4293935104
+#define VPD_BACKUP_FV_VOL_HEADER_SIZE 0x48 // 72
+#define VPD_BACKUP_SIZE 0x4000 // 16384
+#define VPD_BUILDER "C:\\Haswell_labeled\\R8VlvDevicePkg\\Tools\\Bin\\Python\\Ia32\\python.exe C:\\Haswell_labeled\\R8VlvDevicePkg\\Tools\\Dpsd\\VpdBuilder.py"
+#define L_VPD_BUILDER L"C:\\Haswell_labeled\\R8VlvDevicePkg\\Tools\\Bin\\Python\\Ia32\\python.exe C:\\Haswell_labeled\\R8VlvDevicePkg\\Tools\\Dpsd\\VpdBuilder.py"
+#define VPD_FT_STATE_BASE_ADDR 0xfff20000 // 4293918720
+#define VPD_FT_STATE_SIZE 0x4 // 4
+#define VPD_FV_VOL_HEADER_BASE_ADDR 0xfff20000 // 4293918720
+#define VPD_FV_VOL_HEADER_SIZE 0x48 // 72
+#define VPD_VARIABLE_CHECKSUM_SUPPORT 0x0 // 0
+#define V_DEFAULT_SUBSYSTEM_DEVICE_ID 0x574d // 22349
+#define V_DEFAULT_SUBSYSTEM_DEVICE_ID_KT 0x544b // 21579
+#define V_DEFAULT_SUBSYSTEM_VENDOR_ID 0x8086 // 32902
+#define X64_ONLY_MODULE ""
+#define L_X64_ONLY_MODULE L""
+#define X_AXIS_OFFSET 0x235 // 565
+#define YELLOW_FOR_STANDBY 0x1 // 1
+#define Y_AXIS_OFFSET 0x154 // 340
+
diff --git a/BraswellPlatformPkg/Common/Include/ChipsetAccess.h b/BraswellPlatformPkg/Common/Include/ChipsetAccess.h new file mode 100644 index 0000000000..0658e5dc14 --- /dev/null +++ b/BraswellPlatformPkg/Common/Include/ChipsetAccess.h @@ -0,0 +1,24 @@ +/** @file
+ Common Include file for Platform Drivers to access the Chipset registers.
+
+ Copyright (c) 2004 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _CHIPSET_ACCESS_H_
+#define _CHIPSET_ACCESS_H_
+
+#include "PchAccess.h"
+#include "Cherryview.h"
+#include "ChvAccess.h"
+#include "ChvCommonDefinitions.h"
+
+#endif
diff --git a/BraswellPlatformPkg/Common/Include/CommonIncludes.h b/BraswellPlatformPkg/Common/Include/CommonIncludes.h new file mode 100644 index 0000000000..0a2c3c5c95 --- /dev/null +++ b/BraswellPlatformPkg/Common/Include/CommonIncludes.h @@ -0,0 +1,115 @@ +/** @file
+ This file defines common equates.
+
+ Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _COMMON_INCLUDES_H_
+#define _COMMON_INCLUDES_H_
+
+#define V_INTEL_VID 0x8086
+
+#ifndef STALL_ONE_MICRO_SECOND
+#define STALL_ONE_MICRO_SECOND 1
+#endif
+#ifndef STALL_ONE_MILLI_SECOND
+#define STALL_ONE_MILLI_SECOND 1000
+#endif
+///
+/// Min Max
+///
+#define V_MIN(a, b) (((a) < (b)) ? (a) : (b))
+#define V_MAX(a, b) (((a) > (b)) ? (a) : (b))
+
+///
+/// Bit map macro
+///
+#ifndef BIT0
+
+#define BIT63 0x8000000000000000
+#define BIT62 0x4000000000000000
+#define BIT61 0x2000000000000000
+#define BIT60 0x1000000000000000
+#define BIT59 0x0800000000000000
+#define BIT58 0x0400000000000000
+#define BIT57 0x0200000000000000
+#define BIT56 0x0100000000000000
+#define BIT55 0x0080000000000000
+#define BIT54 0x0040000000000000
+#define BIT53 0x0020000000000000
+#define BIT52 0x0010000000000000
+#define BIT51 0x0008000000000000
+#define BIT50 0x0004000000000000
+#define BIT49 0x0002000000000000
+#define BIT48 0x0001000000000000
+#define BIT47 0x0000800000000000
+#define BIT46 0x0000400000000000
+#define BIT45 0x0000200000000000
+#define BIT44 0x0000100000000000
+#define BIT43 0x0000080000000000
+#define BIT42 0x0000040000000000
+#define BIT41 0x0000020000000000
+#define BIT40 0x0000010000000000
+#define BIT39 0x0000008000000000
+#define BIT38 0x0000004000000000
+#define BIT37 0x0000002000000000
+#define BIT36 0x0000001000000000
+#define BIT35 0x0000000800000000
+#define BIT34 0x0000000400000000
+#define BIT33 0x0000000200000000
+#define BIT32 0x0000000100000000
+
+#define BIT31 0x80000000
+#define BIT30 0x40000000
+#define BIT29 0x20000000
+#define BIT28 0x10000000
+#define BIT27 0x08000000
+#define BIT26 0x04000000
+#define BIT25 0x02000000
+#define BIT24 0x01000000
+#define BIT23 0x00800000
+#define BIT22 0x00400000
+#define BIT21 0x00200000
+#define BIT20 0x00100000
+#define BIT19 0x00080000
+#define BIT18 0x00040000
+#define BIT17 0x00020000
+#define BIT16 0x00010000
+#define BIT15 0x00008000
+#define BIT14 0x00004000
+#define BIT13 0x00002000
+#define BIT12 0x00001000
+#define BIT11 0x00000800
+#define BIT10 0x00000400
+#define BIT9 0x00000200
+#define BIT8 0x00000100
+#define BIT7 0x00000080
+#define BIT6 0x00000040
+#define BIT5 0x00000020
+#define BIT4 0x00000010
+#define BIT3 0x00000008
+#define BIT2 0x00000004
+#define BIT1 0x00000002
+#define BIT0 0x00000001
+#endif
+
+#define BITS(x) (1 << (x))
+
+//
+// Notes :
+// 1. Bit position always starts at 0.
+// 2. Following macros are applicable only for Word alligned integers.
+//
+#define BIT(Pos, Value) (1 << (Pos) & (Value))
+#define BITRANGE(From, Width, Value) (((Value) >> (From)) & ((1 << (Width)) - 1))
+
+#endif
diff --git a/BraswellPlatformPkg/Common/Include/CpuBaseLib.h b/BraswellPlatformPkg/Common/Include/CpuBaseLib.h new file mode 100644 index 0000000000..663e926efe --- /dev/null +++ b/BraswellPlatformPkg/Common/Include/CpuBaseLib.h @@ -0,0 +1,244 @@ +/** @file
+ The Lib of CPU Base.
+
+ Copyright (c) 2004 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _CPU_BASE_LIB_H
+#define _CPU_BASE_LIB_H
+
+#include "CpuRegs.h"
+#include "CpuDataStruct.h"
+#include "Protocol/MpService.h"
+
+//
+// Combine f(FamilyId), m(Model), s(SteppingId) to a single 32 bit number
+//
+#define EfiMakeCpuVersion(f, m, s) \
+ (((UINT32) (f) << 16) | ((UINT32) (m) << 8) | ((UINT32) (s)))
+
+#define IA32API __cdecl
+
+typedef struct {
+ UINT32 RegEax;
+ UINT32 RegEbx;
+ UINT32 RegEcx;
+ UINT32 RegEdx;
+} EFI_CPUID_REGISTER;
+
+/**
+ Halt the Cpu.
+
+ @param[in] None
+ @retval None
+
+**/
+VOID
+IA32API
+EfiHalt (
+ VOID
+ );
+
+/**
+ Write back and invalidate the Cpu cache.
+
+ @param[in] None
+ @retval None
+
+**/
+VOID
+IA32API
+EfiWbinvd (
+ VOID
+ );
+
+/**
+ Invalidate the Cpu cache
+
+ @param[in] None
+ @retval None
+
+**/
+VOID
+IA32API
+EfiInvd (
+ VOID
+ );
+
+/**
+ Get the Cpu info by excute the CPUID instruction.
+
+ @param[in] RegisterInEax The input value to put into register EAX
+ @param[in] Regs The Output value
+
+ @retval None
+
+**/
+VOID
+IA32API
+EfiCpuid (
+ IN UINT32 RegisterInEax,
+ OUT EFI_CPUID_REGISTER *Regs
+ );
+
+/**
+ When RegisterInEax != 4, the functionality is the same as EfiCpuid.
+ When RegisterInEax == 4, the function return the deterministic cache
+ parameters by excuting the CPUID instruction
+
+ @param[in] RegisterInEax The input value to put into register EAX
+ @param[in] CacheLevel The deterministic cache level
+ @param[in] Regs The Output value
+
+ @retval None
+
+**/
+VOID
+IA32API
+EfiCpuidExt (
+ IN UINT32 RegisterInEax,
+ IN UINT32 CacheLevel,
+ OUT EFI_CPUID_REGISTER *Regs
+ );
+
+/**
+ Read Cpu MSR.
+
+ @param[in] Index The index value to select the register
+
+ @retval Return the read data
+
+**/
+UINT64
+IA32API
+EfiReadMsr (
+ IN UINT32 Index
+ );
+
+/**
+ Write Cpu MSR.
+
+ @param[in] Index The index value to select the register
+ @param[in] Value The value to write to the selected register
+
+ @retval None
+
+**/
+VOID
+IA32API
+EfiWriteMsr (
+ IN UINT32 Index,
+ IN UINT64 Value
+ );
+
+/**
+ Read Time stamp.
+
+ @param[in] None
+
+ @retval Return the read data
+
+**/
+UINT64
+IA32API
+EfiReadTsc (
+ VOID
+ );
+
+/**
+ Writing back and invalidate the cache,then diable it.
+
+ @param[in] None
+
+ @retval None
+
+**/
+VOID
+IA32API
+EfiDisableCache (
+ VOID
+ );
+
+/**
+ Invalidate the cache,then Enable it.
+
+ @param[in] None
+
+ @retval None
+
+**/
+VOID
+IA32API
+EfiEnableCache (
+ VOID
+ );
+
+/**
+ Get Eflags
+
+ @param[in] None
+ @retval Return the Eflags value
+
+**/
+UINT32
+IA32API
+EfiGetEflags (
+ VOID
+ );
+
+/**
+ Disable Interrupts
+
+ @param[in] None
+
+ @retval None
+
+**/
+VOID
+IA32API
+EfiDisableInterrupts (
+ VOID
+ );
+
+/**
+ Enable Interrupts
+
+ @param[in] None
+
+ @retval None
+
+**/
+VOID
+IA32API
+EfiEnableInterrupts (
+ VOID
+ );
+
+/**
+ Extract CPU detail version infomation
+
+ @param[in] FamilyId FamilyId, including ExtendedFamilyId
+ @param[in] Model Model, including ExtendedModel
+ @param[in] SteppingId SteppingId
+ @param[in] Processor Processor
+
+**/
+VOID
+IA32API
+EfiCpuVersion (
+ IN UINT16 *FamilyId, OPTIONAL
+ IN UINT8 *Model, OPTIONAL
+ IN UINT8 *SteppingId, OPTIONAL
+ IN UINT8 *Processor OPTIONAL
+ );
+
+#endif
diff --git a/BraswellPlatformPkg/Common/Include/CpuDataStruct.h b/BraswellPlatformPkg/Common/Include/CpuDataStruct.h new file mode 100644 index 0000000000..aab91d41cd --- /dev/null +++ b/BraswellPlatformPkg/Common/Include/CpuDataStruct.h @@ -0,0 +1,114 @@ +/** @file
+ The definition of CPU data structure.
+
+ Copyright (c) 2004 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _CPU_DATA_STRUCT_H
+#define _CPU_DATA_STRUCT_H
+
+//
+// The data saved in SMRAM.
+// In S3 path, CPUS3 runs before SMMS3. SMRAM is open at that time.
+//
+
+#define EFI_SMRAM_CPU_NVS_HEADER_GUID \
+ { \
+ 0x429501d9, 0xe447, 0x40f4, 0x86, 0x7b, 0x75, 0xc9, 0x3a, 0x1d, 0xb5, 0x4e \
+ }
+
+typedef struct {
+ //
+ // Guid as Signature.
+ //
+ EFI_GUID HeaderGuid;
+ EFI_PHYSICAL_ADDRESS AcpiCpuPointer;
+ ACPI_CPU_DATA_COMPATIBILITY AcpiCpuData;
+
+ //
+ // It points the data defined below.
+ //
+ EFI_PHYSICAL_ADDRESS GdtrProfileOffset;
+ EFI_PHYSICAL_ADDRESS GdtOffset;
+ EFI_PHYSICAL_ADDRESS IdtrProfileOffset;
+ EFI_PHYSICAL_ADDRESS IdtOffset;
+ EFI_PHYSICAL_ADDRESS CpuPrivateDataOffset;
+ EFI_PHYSICAL_ADDRESS S3BootScriptTableOffset;
+ EFI_PHYSICAL_ADDRESS S3BspMtrrTableOffset;
+ EFI_PHYSICAL_ADDRESS MicrocodePointerBufferOffset; // It is pointer to pointer array.
+ EFI_PHYSICAL_ADDRESS MicrocodeDataBufferOffset; // It is pointer to the data.
+
+ //
+ // We need put all the data buffer here as well.
+ // These data will be copied to original location in S3.
+ //
+
+ //
+ // DataBuffer size
+ //
+ UINT32 GdtrProfileSize;
+ UINT32 GdtSize;
+ UINT32 IdtrProfileSize;
+ UINT32 IdtSize;
+ UINT32 CpuPrivateDataSize;
+ UINT32 S3BootScriptTableSize;
+ UINT32 S3BspMtrrTableSize;
+ UINT32 MicrocodePointerBufferSize;
+ UINT32 MicrocodeDataBufferSize;
+} SMRAM_CPU_DATA;
+
+typedef struct {
+ UINT32 HeaderVersion;
+ UINT32 UpdateRevision;
+ UINT32 Date;
+ UINT32 ProcessorId;
+ UINT32 Checksum;
+ UINT32 LoaderRevision;
+ UINT32 ProcessorFlags;
+ UINT32 DataSize;
+ UINT32 TotalSize;
+ UINT8 Reserved[12];
+} EFI_CPU_MICROCODE_HEADER;
+
+typedef struct {
+ UINT32 ExtSigCount;
+ UINT32 ExtChecksum;
+ UINT8 Reserved[12];
+ UINT32 ProcessorId;
+ UINT32 ProcessorFlags;
+ UINT32 Checksum;
+} EFI_CPU_MICROCODE_EXT_HEADER;
+
+typedef struct {
+ UINT32 ExtendedSignatureCount;
+ UINT32 ExtendedTableChecksum;
+ UINT8 Reserved[12];
+} EFI_CPU_MICROCODE_EXTENDED_TABLE_HEADER;
+
+typedef struct {
+ UINT32 ProcessorSignature;
+ UINT32 ProcessorFlag;
+ UINT32 ProcessorChecksum;
+} EFI_CPU_MICROCODE_EXTENDED_TABLE;
+
+typedef struct {
+ UINT32 Stepping : 4;
+ UINT32 Model : 4;
+ UINT32 Family : 4;
+ UINT32 Type : 2;
+ UINT32 Reserved1 : 2;
+ UINT32 ExtendedModel : 4;
+ UINT32 ExtendedFamily : 8;
+ UINT32 Reserved2 : 4;
+} EFI_CPU_VERSION;
+
+#endif
diff --git a/BraswellPlatformPkg/Common/Include/GpioAttributes.h b/BraswellPlatformPkg/Common/Include/GpioAttributes.h new file mode 100644 index 0000000000..2fdbc9310a --- /dev/null +++ b/BraswellPlatformPkg/Common/Include/GpioAttributes.h @@ -0,0 +1,121 @@ +/** @file
+ This file provides the definitions of GPIO attributes
+
+Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _GPIO_ATTRIBUTES_H_
+#define _GPIO_ATTRIBUTES_H_
+
+#define GPIO_ATTRIBUTE_HIGH 1
+#define GPIO_ATTRIBUTE_LOW 0
+#define GPIO_ATTRIBUTE_NA 0xFF
+//
+// Attribute: GPIO_USAGE
+//
+typedef enum {
+ USAGE_GPIO = 0,
+ USAGE_GPO = 1,
+ USAGE_GPI = 2,
+ USAGE_HIZ = 3,
+ USAGE_Native = 4,
+ USAGE_None = 0xFF
+} GPIO_ATTRIBUTE_USAGE;
+
+//
+// Attribute: INT_TRIGGER_TYPE
+//
+typedef enum {
+ TRIGGER_Edge_High = 0,
+ TRIGGER_Edge_Low = 1,
+ TRIGGER_Edge_Both = 2,
+ TRIGGER_Level_High = 3,
+ TRIGGER_Level_Low = 4,
+ TRIGGER_None = 0xFF
+} GPIO_ATTRIBUTE_TRIGGER_TYPE;
+
+//
+// Attribute: DRIVE_TYPE
+//
+typedef enum {
+ DRIVE_Open_Drain = 0,
+ DRIVE_Push_Pull = 1,
+ DRIVE_None = 0xFF
+} GPIO_ATTRIBUTE_DRIVE_TYPE;
+
+//
+// Attribute: PULL_DIRECTION
+//
+typedef enum {
+ DIRECTION_Pull_Up = 0,
+ DIRECTION_Pull_Down = 1,
+ DIRECTION_None = 0xFF
+} GPIO_ATTRIBUTE_PULL_DIRECTION;
+
+//
+// Attribute: PULL_STRENGTH
+//
+typedef enum {
+ STRENGTH_1K = 0,
+ STRENGTH_2K = 1,
+ STRENGTH_5K = 2,
+ STRENGTH_10K = 3,
+ STRENGTH_20K = 4,
+ STRENGTH_40K = 5,
+ STRENGTH_None = 0xFF
+} GPIO_ATTRIBUTE_PULL_STRENGTH;
+
+//
+// Attribute: INT_TYPE
+//
+typedef enum {
+ INT_Direct = 0,
+ INT_Shared = 1,
+ INT_SMI = 2,
+ INT_SCI = 3,
+ INT_None = 0xFF
+} GPIO_ATTRIBUTE_INT_TYPE;
+
+//
+// Attribute: SHARE_MODE
+//
+typedef enum {
+ MODE_Shared = 0,
+ MODE_Exclusive = 1,
+ MODE_SharedAndWake = 2,
+ MODE_ExclusiveAndWake = 3
+} GPIO_ATTRIBUTE_SHARE_MODE;
+
+//
+// Attribute: INVERT_RX_TX
+//
+typedef enum
+{
+ GLITCH_DISABLE = 0,
+ GLITCH_EN_EdgeDetect,
+ GLITCH_EN_RX_Data,
+ GLITCH_EN_Edge_RX_Data,
+} GPIO_ATTRIBUTE_GLITCH_CFG;
+
+//
+// Attribute: INVERT_RX_TX
+//
+typedef enum
+{
+ GPIO_No_Inversion = 0,
+ GPIO_Inv_RX_Enable = 0x1,
+ GPIO_Inv_TX_Enable = 0x2,
+ GPIO_Inv_RX_TX_Enable = 0x3,
+ GPIO_Inv_RX_Data = 0x4,
+ GPIO_Inv_RX_Data_TX_Enable = 0x6,
+ GPIO_Inv_TX_Data = 0x8,
+} GPIO_ATTRIBUTE_INVERT_RX_TX;
+#endif
diff --git a/BraswellPlatformPkg/Common/Include/Guid/BiosId.h b/BraswellPlatformPkg/Common/Include/Guid/BiosId.h new file mode 100644 index 0000000000..e045f75d51 --- /dev/null +++ b/BraswellPlatformPkg/Common/Include/Guid/BiosId.h @@ -0,0 +1,24 @@ +/** @file
+ GUIDs used for Bios ID.
+
+ Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _BIOS_ID_H_
+#define _BIOS_ID_H_
+
+#define EFI_BIOS_ID_GUID \
+{ 0xC3E36D09, 0x8294, 0x4b97, 0xA8, 0x57, 0xD5, 0x28, 0x8F, 0xE3, 0x3E, 0x28 }
+
+extern EFI_GUID gEfiBiosIdGuid;
+
+#endif
diff --git a/BraswellPlatformPkg/Common/Include/Guid/FtpmInstance.h b/BraswellPlatformPkg/Common/Include/Guid/FtpmInstance.h new file mode 100644 index 0000000000..5deee24183 --- /dev/null +++ b/BraswellPlatformPkg/Common/Include/Guid/FtpmInstance.h @@ -0,0 +1,24 @@ +/** @file
+ TPM instance guid, used for PcdTpmInstanceGuid.
+
+ Copyright (c) 2013 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __FTPM_INSTANCE_GUID_H__
+#define __FTPM_INSTANCE_GUID_H__
+
+#define TPM_DEVICE_INTERFACE_TPM20_FTPM \
+ { 0x1dd8a521, 0x7de9, 0x47c2, { 0x8e, 0x6, 0x29, 0xf0, 0xd5, 0x70, 0x24, 0xc6 } }
+
+extern EFI_GUID gEfiTpmDeviceInstanceTpm20FtpmGuid;
+#endif
+
diff --git a/BraswellPlatformPkg/Common/Include/Guid/GraphicsInfoHob.h b/BraswellPlatformPkg/Common/Include/Guid/GraphicsInfoHob.h new file mode 100644 index 0000000000..51e2369072 --- /dev/null +++ b/BraswellPlatformPkg/Common/Include/Guid/GraphicsInfoHob.h @@ -0,0 +1,34 @@ +/** @file
+ Hob guid for Information about the graphics mode.
+
+ Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _GRAPHICS_INFO_HOB_GUID_H_
+#define _GRAPHICS_INFO_HOB_GUID_H_
+
+#include <Protocol/GraphicsOutput.h>
+
+#define EFI_PEI_GRAPHICS_INFO_HOB_GUID \
+ { \
+ 0x39f62cce, 0x6825, 0x4669, { 0xbb, 0x56, 0x54, 0x1a, 0xba, 0x75, 0x3a, 0x07 } \
+ }
+
+typedef struct {
+ EFI_PHYSICAL_ADDRESS FrameBufferBase;
+ UINT32 FrameBufferSize;
+ EFI_GRAPHICS_OUTPUT_MODE_INFORMATION GraphicsMode;
+} EFI_PEI_GRAPHICS_INFO_HOB;
+
+extern EFI_GUID gEfiGraphicsInfoHobGuid;
+
+#endif
diff --git a/BraswellPlatformPkg/Common/Include/Guid/HiiFrontPageFormset.h b/BraswellPlatformPkg/Common/Include/Guid/HiiFrontPageFormset.h new file mode 100644 index 0000000000..e91c7391cb --- /dev/null +++ b/BraswellPlatformPkg/Common/Include/Guid/HiiFrontPageFormset.h @@ -0,0 +1,33 @@ +//
+// This file contains 'Framework Code' and is licensed as such
+// under the terms of your license agreement with Intel or your
+// vendor. This file may not be modified, except as allowed by
+// additional terms of your license agreement.
+//
+/**@file
+Constants and declarations that are common accross PEI and DXE.
+
+Copyright (c) 2010, Intel Corporation. All rights reserved.<BR>
+This software and associated documentation (if any) is furnished
+under a license and may only be used or copied in accordance
+with the terms of the license. Except as permitted by such
+license, no part of this software or documentation may be
+reproduced, stored in a retrieval system, or transmitted in any
+form or by any means without the express written consent of
+Intel Corporation.
+
+**/
+
+#ifndef __HII_FRONT_PAGE_FORMSET_H__
+#define __HII_FRONT_PAGE_FORMSET_H__
+
+///
+/// Guid define to group the item show on the front page.
+///
+//#define EFI_IFR_FRONT_PAGE_GUID
+// { 0xe58809f8, 0xfbc1, 0x48e2, { 0x88, 0x3a, 0xa3, 0xf, 0xdc, 0x4b, 0x44, 0x1e } }
+
+
+extern EFI_GUID gEfiIfrFrontPageGuid;
+
+#endif
diff --git a/BraswellPlatformPkg/Common/Include/Guid/MemoryConfigData.h b/BraswellPlatformPkg/Common/Include/Guid/MemoryConfigData.h new file mode 100644 index 0000000000..cd4177e1d7 --- /dev/null +++ b/BraswellPlatformPkg/Common/Include/Guid/MemoryConfigData.h @@ -0,0 +1,27 @@ +/** @file
+ GUID used for Memory Configuration Data entries in the HOB list.
+
+ Copyright (c) 2004 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _MEMORY_CONFIG_DATA_GUID_H_
+#define _MEMORY_CONFIG_DATA_GUID_H_
+
+#define EFI_MEMORY_CONFIG_DATA_GUID \
+ { \
+ 0x80dbd530, 0xb74c, 0x4f11, 0x8c, 0x03, 0x41, 0x86, 0x65, 0x53, 0x28, 0x31 \
+ }
+
+extern EFI_GUID gEfiMemoryConfigDataGuid;
+extern CHAR16 EfiMemoryConfigVariable[];
+
+#endif
diff --git a/BraswellPlatformPkg/Common/Include/Guid/PlatformInfo.h b/BraswellPlatformPkg/Common/Include/Guid/PlatformInfo.h new file mode 100644 index 0000000000..2f33bc6528 --- /dev/null +++ b/BraswellPlatformPkg/Common/Include/Guid/PlatformInfo.h @@ -0,0 +1,316 @@ +/** @file
+ GUID used for Platform Info Data entries in the HOB list.
+
+ Copyright (c) 2004 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _PLATFORM_INFO_GUID_H_
+#define _PLATFORM_INFO_GUID_H_
+#include <PiPei.h>
+
+#include <Library/HobLib.h>
+#include <Library/IoLib.h>
+#include <Library/DebugLib.h>
+#include <Library/SmbusLib.h>
+#ifndef FSP_FLAG
+#include <IndustryStandard/Smbus.h>
+#endif
+#define PLATFORM_INFO_REVISION 1 // revision id for current platform information struct
+
+#define BOARD_REVISION_DEFAULT 0xFF
+#define UNKNOWN_FABID 0x0F
+#define FAB_ID_MASK 0x0F
+
+#define BSW_CR_PMIC_I2C_BUSNO 1
+#define BSW_CR_PMIC_I2C_SLAVE_ADDR 0x5E
+//
+// Definitions required for panel initialization code for CherryTrail
+//
+
+#define MIPI_I2C_BUSNO 5
+#define FFD_MIPI_I2C_BUSNO 1
+#define MIPI_I2C_SLAVE_DEVICE_ADDR 0x2C
+#define MIPI_I2C_BACKLIGHT_BOOST_REG_OFFSET 0x01
+#define MIPI_I2C_UNUSEED_CHANNEL_DISABLE_OFFSET 0x16
+#define MIPI_BACKLIGHT_BOOST_VALUE 0x01
+#define MIPI_DISABLE_UNUSED_CHANNELS_VALUE 0x07
+#define PANEL_CONFIG_MIPI 0x00
+#define PANEL_CONFIG_EDP 0x01
+#define PANEL_VENDOR_LG 0x00
+#define PANEL_VENDOR_PANASONIC 0x01
+#define PANEL_VENDOR_INNOLUX 0x02
+#define WIFI_PCI_BUS_NUMBER 0x01
+#define WIFI_PCI_DEVICE_NUMBER 0x00
+#define WIFI_PCI_FUNCTION_NUMBER 0x00
+#define STP_WIFI_DEVICE_VENDOR_ID 0x095A8086
+
+#define POST_CODE_I2C_BUS_NO 0x01
+#define POST_CODE_I2C_SLAVE_ADDR 0x38
+
+#define IO_EXPANDER_I2C_BUS_NO 6 // GPIO expander
+#define IO_EXPANDER_SLAVE_ADDR 0x20
+
+#define PSS_CHIP_I2C_BUS_NO 0 // PSS Chip
+#define PSS_CHIP_SLAVE_ADDR 0x6E
+#define PSS_CHIP_IPN_LENGTH 12
+#define PSS_CHIP_IPN_OFFSET 160
+
+#define I2C_EXPANDER_I2C_BUS_NO 6 // I2C expander
+#define I2C_EXPANDER_SLAVE_ADDR 0x23
+
+#define IO_EXP_REG0 0
+#define IO_EXP_REG1 1
+#define IO_EXP_REG2 2
+#define IO_EXP_REG3 3
+
+#define I2C_EXP_REG0 0
+#define I2C_EXP_REG1 1
+#define I2C_EXP_REG2 2
+#define I2C_EXP_REG3 3
+#define I2C_EXP_REG4 0x4
+#define I2C_EXP_REGC 0xC
+
+#define CHG_SMB349_I2C_CHANNEL_NUMBER 0x0
+#define CHG_SMB349_I2C_SLAVE_ADDRESS 0x35
+#define CHG_SMB349_STATUS_REG_B 0x3C
+#define CHG_SMB349_STATUS_REG_D 0x3E
+
+#define MAX_FAB_ID_RETRY_COUNT 100
+#define MAX_FAB_ID_CHECK_COUNT 3
+
+#define PLATFORM_INFO_HOB_REVISION 0x1
+
+#define CR_USB_MUX_EN 0xfed9d448
+#define COPOP_USB_MUX_EN 0xFED8D460
+
+#define EFI_PLATFORM_INFO_GUID \
+ { \
+ 0x1e2acc41, 0xe26a, 0x483d, 0xaf, 0xc7, 0xa0, 0x56, 0xc3, 0x4e, 0x8, 0x7b \
+ }
+
+extern EFI_GUID gEfiPlatformInfoGuid;
+
+typedef enum {
+ FlavorUnknown = 0,
+ //
+ // Mobile
+ //
+ FlavorMobile = 1,
+ //
+ // Desktop
+ //
+ FlavorDesktop = 2,
+ //
+ // Tablet
+ //
+ FlavorTablet = 3
+} PLATFORM_FLAVOR;
+
+typedef enum {
+ BOARD_ID_AV_SVP = 0x0, // Alpine Valley Board
+ BOARD_ID_CHT_CR = 0x1, // Cherry Trail CR
+ BOARD_ID_CHT_COPOP = 0x2, // Cherry Trail COPOP
+ BOARD_ID_CHV_T = 0x3, // Cherry Trail Tablet
+ BOARD_ID_CHT_SONY = 0x4, // Cherry Trail Sony
+ BOARD_ID_BL_RVP_DDR3L = 0x5, // BayLake Board (RVP DDR3L)
+ BOARD_ID_BL_STHI = 0x7, // PPV- STHI Board
+ BOARD_ID_CHT_FFD = 0x8, // Cherry Trail FFD
+ BOARD_ID_CHT_HR15_RVP = 0x9, // Cherry Trail Holiday Refresh RVP
+ BOARD_ID_CHT_HR15_FFD = 0xA, // Cherry Trail Holiday Refresh FFD
+ BOARD_ID_DUMMY = 0xf, // For Usage incase of no Board identified
+ BOARD_ID_BB_RVP = 0x20, // Bayley Bay Board
+ BOARD_ID_BS_RVP = 0x30, // Bakersport Board
+ BOARD_ID_BSW = 0x44, // Braswell ID
+ BOARD_ID_BSW_CR = 0x55, // Braswell CR
+ BOARD_ID_BSW_RVP_ECC = 0x60, // Braswell RVP ECC
+ BOARD_ID_BSW_CH = 0x80, // Braswell Cherry Hill
+ BOARD_ID_BSW_CI = 0x82, // Braswell Cherry Island
+ BOARD_ID_BSW_WD = 0x83, // Braswell Western Digital
+ BOARD_ID_SVP = 0xee, // SV Board
+ BOARD_ID_BL_FFRD = 0xF1, // BayLake FFRD
+ BOARD_ID_BL_RVP = 0xF2, // BayLake RVP
+ BOARD_ID_CL_ERB = 0xF3, // CherryTrail ERB
+ BOARD_ID_CL_CRB = 0xF4, // CherryTrail CRB
+ BOARD_ID_BL_FFRD8 = 0xF5 // Baytrail FFRD8
+} BOARD_ID_LIST;
+
+typedef enum {
+ FAB1 = 0,
+ FAB2 = 1,
+ FAB3 = 2
+} FAB_ID_LIST;
+
+//
+// Hardware_ID table for Product_Line_ID == INTEL_CHT_TABLET
+//
+typedef enum {
+ CHT_TABLET_RVP1 = 0, /* Cherry Trail RVP Fab 1 */
+ CHT_TABLET_RVP2 = 1, /* Cherry Trail RVP Fab 2 */
+ CHT_TABLET_RVP3 = 2, /* Cherry Trail RVP Fab 3 */
+ CHT_TABLET_FFD_PR0 = 3, /* Cherry Trail FFRD PR0 */
+ CHT_TABLET_FFD_PR1 = 4, /* Cherry Trail FFRD PR1 */
+ CHT_TABLET_FFD_PR2 = 5, /* Cherry Trail FFRD PR2 */
+ CHT_TABLET_UNKNOWN = 0xFF
+}INTEL_CHT;
+
+typedef enum {
+ PR0 = 0, // FFRD PR0
+ PR05 = 1, // FFRD PR0.3 and PR 0.5
+ PR1 = 2, // FFRD PR1
+ PR11 = 3 // FFRD PR1.1
+} FFRD_ID_LIST;
+
+typedef enum {
+ FFD_8_PR0 = 1, // FFRD8 PR0
+ FFD_8_PR1 = 2, // FFRD8 PR1
+ FFD_8_PR2 = 3 // FFRD8 PR1
+} FFD_ID_LIST;
+
+//
+// PMIC ID
+//
+typedef enum {
+ PMIC_TYPE_CRC_PLUS = 0,
+ PMIC_TYPE_DC_TI = 1,
+ PMIC_TYPE_DC_XPOWERS = 2,
+ PMIC_TYPE_WC = 3,
+ PMIC_TYPE_MTV_PLUS = 4,
+ PMIC_TYPE_DUMMY = 0xFE,
+ PMIC_TYPE_NONE = 0xff,
+}PMIC_TYPE;
+#pragma pack(1)
+
+typedef struct {
+ UINT16 PciResourceIoBase;
+ UINT16 PciResourceIoLimit;
+ UINT32 PciResourceMem32Base;
+ UINT32 PciResourceMem32Limit;
+ UINT64 PciResourceMem64Base;
+ UINT64 PciResourceMem64Limit;
+ UINT64 PciExpressBase;
+ UINT32 PciExpressSize;
+ UINT8 PciHostAddressWidth;
+ UINT8 PciResourceMinSecBus;
+} EFI_PLATFORM_PCI_DATA;
+
+typedef struct {
+ UINT8 CpuAddressWidth;
+ UINT32 CpuFamilyStepping;
+} EFI_PLATFORM_CPU_DATA;
+
+typedef struct {
+ UINT8 SysIoApicEnable;
+ UINT8 SysSioExist;
+} EFI_PLATFORM_SYS_DATA;
+
+typedef struct {
+ UINT32 MemTolm;
+ UINT32 MemMaxTolm;
+ UINT32 MemTsegSize;
+ UINT32 MemTsegBase;
+ UINT32 MemIedSize;
+ UINT32 MemIgdSize;
+ UINT32 MemIgdBase;
+ UINT32 MemIgdGttSize;
+ UINT32 MemIgdGttBase;
+ UINT64 MemMir0;
+ UINT64 MemMir1;
+ UINT32 MemConfigSize;
+ UINT16 MmioSize;
+} EFI_PLATFORM_MEM_DATA;
+
+typedef struct {
+ UINT32 IgdOpRegionAddress; // IGD OpRegion Starting Address
+ UINT8 IgdBootType; // IGD Boot Display Device
+ UINT8 IgdPanelType; // IGD Panel Type CMOs option
+ UINT8 IgdTvFormat; // IGD TV Format CMOS option
+ UINT8 IgdTvMinor; // IGD TV Minor Format CMOS option
+ UINT8 IgdPanelScaling; // IGD Panel Scaling
+ UINT8 IgdBlcConfig; // IGD BLC Configuration
+ UINT8 IgdBiaConfig; // IGD BIA Configuration
+ UINT8 IgdSscConfig; // IGD SSC Configuration
+ UINT8 IgdDvmtMemSize; // IGD DVMT Memory Size
+ UINT8 IgdFunc1Enable; // IGD Function 1 Enable
+ UINT8 IgdHpllVco; // HPLL VCO
+ UINT8 IgdSciSmiMode; // GMCH SMI/SCI mode (0=SCI)
+ UINT8 IgdPAVP; // IGD PAVP data
+} EFI_PLATFORM_IGD_DATA;
+
+/*
+ ****************************************************************************
+ ****************************************************************************
+ ****************************************************************************
+ ****************************************************************************
+ ****************************************************************************
+ * CherryView GPIOs Configuration *
+ ****************************************************************************
+ ****************************************************************************
+ ****************************************************************************
+ ****************************************************************************
+ ****************************************************************************
+ */
+
+#define NA 0xFF
+
+//
+// Security SAI for GPIO
+//
+
+#define IA_UNTRUUSTED 0x00000001
+#define IA_UCODE 0x00000002
+#define IA_SMM 0x00000004
+#define UCODE_NPP 0x00000008
+#define IA_BOOT 0x00000010
+#define IA_XUCODE 0x00000080
+#define PUNIT_TRUSTED 0x00000100
+#define SEC_TRUSTED 0x00000200
+#define DRM 0x00000400
+#define FUSESTRAP_PULLER 0x00000800
+#define FUSE_PROVIDER 0x00001000
+#define STRAP_PROVIDER 0x00002000
+#define DFX_UNTRUSTED 0x00004000
+#define DFX_TRUSTED 0x00008000
+#define PMC_TRUSTED 0x00010000
+#define DRANG 0x00020000
+#define ISH_T 0x00040000
+
+typedef struct _EFI_PLATFORM_INFO_HOB {
+ UINT16 PlatformType; // Platform Type
+ UINT8 BoardId; // Board ID
+ PLATFORM_FLAVOR PlatformFlavor; // Platform Flavor
+ UINT8 ECSupport;
+ UINT8 FanSupport;
+ UINT8 BatterySupport;
+ UINT8 DDRDaughterCardCh0Id;// DDR daughter card channel 0 id
+ UINT8 DDRDaughterCardCh1Id;// DDR daughter card channel 1 id
+ EFI_PLATFORM_PCI_DATA PciData;
+ EFI_PLATFORM_CPU_DATA CpuData;
+ EFI_PLATFORM_MEM_DATA MemData;
+ EFI_PLATFORM_SYS_DATA SysData;
+ EFI_PLATFORM_IGD_DATA IgdData;
+ UINT8 RevisonId; // Structure Revision ID
+ UINT32 SsidSvid;
+ UINT8 WarmResetOccured;
+ UINT16 MemCfgID;
+ UINT16 FABID;
+ PMIC_TYPE PmicId;
+ UINT8 BoardSvidConfig;
+} EFI_PLATFORM_INFO_HOB;
+
+#pragma pack()
+
+EFI_STATUS
+InstallPlatformSysCtrlGPIONotify (
+ IN CONST EFI_PEI_SERVICES **PeiServices
+ );
+
+#endif
diff --git a/BraswellPlatformPkg/Common/Include/Guid/SetupVariable.h b/BraswellPlatformPkg/Common/Include/Guid/SetupVariable.h new file mode 100644 index 0000000000..f2e754071e --- /dev/null +++ b/BraswellPlatformPkg/Common/Include/Guid/SetupVariable.h @@ -0,0 +1,1312 @@ +/** @file
+ Driver configuration include file.
+
+ Copyright (c) 2012 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _SETUP_VARIABLE_H
+#define _SETUP_VARIABLE_H
+
+//
+// ---------------------------------------------------------------------------
+//
+// Driver Configuration
+//
+// ---------------------------------------------------------------------------
+//
+
+//
+// {EC87D643-EBA4-4bb5-A1E5-3F3E36B20DA9}
+//
+#define SYSTEM_CONFIGURATION_GUID\
+ { \
+ 0xec87d643, 0xeba4, 0x4bb5, 0xa1, 0xe5, 0x3f, 0x3e, 0x36, 0xb2, 0xd, 0xa9 \
+ }
+
+#define ROOT_SECURITY_GUID\
+ { \
+ 0xd387d688, 0xeba4, 0x45b5, 0xa1, 0xe5, 0x3f, 0x3e, 0x36, 0xb2, 0xd, 0x37 \
+ }
+
+//
+// {6936B3BD-4350-46d9-8940-1FA20961AEB1}
+//
+#define SYSTEM_ROOT_MAIN_GUID\
+ { \
+ 0x6936b3bd, 0x4350, 0x46d9, 0x89, 0x40, 0x1f, 0xa2, 0x9, 0x61, 0xae, 0xb1 \
+ }
+
+//
+// {21FEE8DB-0D29-477e-B5A9-96EB343BA99C}
+//
+#define ADDITIONAL_SYSTEM_INFO_GUID\
+ { \
+ 0x21fee8db, 0xd29, 0x477e, 0xb5, 0xa9, 0x96, 0xeb, 0x34, 0x3b, 0xa9, 0x9c \
+ }
+
+#define SETUP_GUID { 0xEC87D643, 0xEBA4, 0x4BB5, 0xA1, 0xE5, 0x3F, 0x3E, 0x36, 0xB2, 0x0D, 0xA9 }
+
+#define MAX_CUSTOM_VID_TABLE_STATES 6
+//
+// Overclocking Source Defines
+//
+#define OVERCLOCK_SOURCE_BIOS 0
+#define OVERCLOCK_SOURCE_OS 1
+
+#define PCH_PCIE_MAX_ROOT_PORTS 4
+#define PCH_HSIC_MAX_PORTS 2
+#define PCH_SSIC_MAX_PORTS 2
+
+#define EFI_CSM_CONTROL_ALWAYS_ON 0x1
+#define EFI_CSM_CONTROL_ALWAYS_OFF 0x0
+
+#pragma pack(1)
+
+// NOTE: When you add anything to this structure,
+// you MUST add it to the very bottom!!!!
+// You must make sure the structure size is able to divide by 32!
+typedef struct {
+ //
+ // System ports
+ //
+ UINT8 Serial;
+ UINT8 SerialLockHide;
+
+ UINT8 Serial2;
+ UINT8 Serial2LockHide;
+
+ UINT8 Parallel;
+ UINT8 ParallelLockHide;
+
+ UINT8 ParallelMode;
+ UINT8 ParallelModeLockHide;
+
+ UINT8 AllUsb;
+ UINT8 UsbPortsLockHide;
+
+ UINT8 Usb2;
+ UINT8 Usb2LockHide;
+
+ UINT8 UsbLegacy;
+ UINT8 UsbLegacyLockHide;
+
+ //
+ // Keyboard
+ //
+ UINT8 Numlock;
+ UINT8 NumlockLockHide;
+
+ //
+ // ECIR
+ //
+ UINT8 ECIR;
+ UINT8 ECIRLockHide;
+
+ //
+ // Power State
+ //
+ UINT8 PowerState;
+ UINT8 PowerStateLockHide;
+
+ //
+ // Wake on RTC variables
+ //
+ UINT8 WakeOnRtcS5;
+ UINT8 WakeOnRtcS5LockHide;
+ UINT8 RTCWakeupDate;
+ UINT8 RTCWakeupDateLockHide;
+ UINT8 RTCWakeupTimeHour;
+ UINT8 RTCWakeupHourLockHide;
+ UINT8 RTCWakeupTimeMinute;
+ UINT8 RTCWakeupMinuteLockHide;
+ UINT8 RTCWakeupTimeSecond;
+ UINT8 RTCWakeupSecondLockHide;
+
+ //
+ // Video Adaptor
+ //
+ UINT8 PrimaryVideoAdaptor;
+ UINT8 PrimaryVideoAdaptorLockHide;
+
+ //
+ // Hybrid Graphics
+ //
+ UINT16 DelayAfterPwrEn;
+ UINT16 DelayAfterHoldReset;
+ //
+ // Chassis intrusion
+ //
+ UINT8 IntruderDetection;
+ UINT8 IntruderDetectionLockHide;
+
+ //
+ // Maximum FSB Automatic/Disable
+ //
+ UINT8 MaxFsb;
+ UINT8 MaxFsbLockHide;
+
+ //
+ // Hard Disk Pre-delay
+ //
+ UINT8 HddPredelay;
+ UINT8 HddPredelayLockHide;
+
+ //
+ // S.M.A.R.T. Mode
+ //
+ UINT8 SmartMode;
+ UINT8 SmartModeLockHide;
+
+ //
+ // ACPI Suspend State
+ //
+ UINT8 AcpiSuspendState;
+ UINT8 AcpiSuspendStateLockHide;
+
+ //
+ // PCI Latency Timer
+ //
+ UINT8 PciLatency;
+ UINT8 PciLatencyLockHide;
+
+ //
+ // Fan Control
+ //
+ UINT8 FanControl;
+ UINT8 FanControlLockHide;
+
+ //
+ // CPU Fan Control
+ //
+ UINT8 CpuFanControl;
+ UINT8 CpuFanControlLockHide;
+
+ //
+ // Lowest Fan Speed
+ //
+ UINT8 LowestFanSpeed;
+ UINT8 LowestFanSpeedLockHide;
+
+ //
+ // Processor (CPU)
+ //
+ UINT8 CpuFlavor;
+
+ UINT8 CpuidMaxValue;
+ UINT8 CpuidMaxValueLockHide;
+
+ UINT8 ExecuteDisableBit;
+ UINT8 ExecuteDisableBitLockHide;
+
+ //
+ // EIST or GV3 setup option
+ //
+ UINT8 ProcessorEistEnable;
+ UINT8 ProcessorEistEnableLockHide;
+
+ //
+ // C1E Enable
+ //
+ UINT8 ProcessorC1eEnable;
+ UINT8 ProcessorC1eEnableLockHide;
+
+ //
+ // Enabling CPU C-States of processor
+ //
+ UINT8 ProcessorCcxEnable;
+ UINT8 ProcessorCcxEnableLockHide;
+
+ //
+ // Package C-State Limit
+ //
+ UINT8 PackageCState;
+ UINT8 PackageCStateLockHide;
+
+ //
+ // Enable/Disable NHM C3(ACPI C2) report to OS
+ //
+ UINT8 OSC2Report;
+ UINT8 OSC2ReportLockHide;
+
+ //
+ // Enable/Disable NHM C6(ACPI C3) report to OS
+ //
+ UINT8 C6Enable;
+ UINT8 C6EnableLockHide;
+
+ //
+ // Enable/Disable NHM C7(ACPI C3) report to OS
+ //
+ UINT8 C7Enable;
+ UINT8 C7EnableLockHide;
+
+ //
+ // EIST/PSD Function select option
+ //
+ UINT8 ProcessorEistPsdFunc;
+ UINT8 ProcessorEistPsdFuncLockHide;
+
+ //
+ // CPU Active Cores and SMT
+ //
+ UINT8 ActiveProcessorCores;
+ UINT8 ActiveProcessorCoresLockHide;
+
+ //
+ // Hyper Threading
+ //
+ UINT8 ProcessorHyperThreadingDisable;
+ UINT8 ProcessorHyperThreadingDisableLockHide;
+
+ //
+ // Enabling VMX
+ //
+ UINT8 ProcessorVmxEnable;
+ UINT8 ProcessorVmxEnableLockHide;
+
+ //
+ // Enabling BIST
+ //
+ UINT8 ProcessorBistEnable;
+ UINT8 ProcessorBistEnableLockHide;
+
+ //
+ // Disabling XTPR
+ //
+ UINT8 ProcessorxTPRDisable;
+ UINT8 ProcessorxTPRDisableLockHide;
+
+ //
+ // Enabling XE
+ //
+ UINT8 ProcessorXEEnable;
+ UINT8 ProcessorXEEnableLockHide;
+
+ //
+ // Fast String
+ //
+ UINT8 FastStringEnable;
+ UINT8 FastStringEnableLockHide;
+
+ //
+ // Monitor/Mwait
+ //
+ UINT8 MonitorMwaitEnable;
+ UINT8 MonitorMwaitEnableLockHide;
+
+ //
+ // Machine Check
+ //
+ UINT8 MachineCheckEnable;
+ UINT8 MachineCheckEnableLockHide;
+
+ //
+ // Turbo mode
+ //
+ UINT8 TurboModeEnable;
+ UINT8 TurboModeEnableLockHide;
+
+ //
+ // DCA setup option
+ //
+ UINT8 DcaEnable;
+ UINT8 DcaEnableLockHide;
+
+ //
+ // DCA Prefetch Delay Value
+ //
+ UINT8 DcaPrefetchDelayValue;
+ UINT8 DcaPrefetchDelayValueLockHide;
+
+ //
+ // Hardware Prefetch
+ //
+ UINT8 MlcStreamerPrefetcherEnable;
+ UINT8 MlcStreamerPrefetcherEnableLockHide;
+
+ //
+ // Adjacent Cache Line Prefetch
+ //
+ UINT8 MlcSpatialPrefetcherEnable;
+ UINT8 MlcSpatialPrefetcherEnableLockHide;
+
+ //
+ // DCU Streamer Prefetcher
+ //
+ UINT8 DCUStreamerPrefetcherEnable;
+ UINT8 DCUStreamerPrefetcherEnableLockHide;
+
+ //
+ // DCU IP Prefetcher
+ //
+ UINT8 DCUIPPrefetcherEnable;
+ UINT8 DCUIPPrefetcherEnableLockHide;
+
+ //
+ // Enable Processor XAPIC
+ //
+ UINT8 ProcessorXapic;
+ UINT8 ProcessorXapicLockHide;
+
+ //
+ // Select BSP
+ //
+ UINT8 BspSelection;
+ UINT8 BspSelectionLockHide;
+
+ //
+ // Non-Turbo Mode Processor Core Ratio Multiplier
+ //
+ UINT8 ProcessorFlexibleRatio;
+ UINT8 ProcessorFlexibleRatioLockHide;
+
+ //
+ // Turbo-XE Mode Processor TDC Limit Override Enable
+ //
+ UINT8 ProcessorTDCLimitOverrideEnable;
+ UINT8 ProcessorTDCLimitOverrideEnableLockHide;
+
+ //
+ // Turbo-XE Mode Processor TDC Limit
+ //
+ UINT16 ProcessorTDCLimit;
+ UINT8 ProcessorTDCLimitLockHide;
+
+ //
+ // Turbo-XE Mode Processor TDP Limit Override Enable
+ //
+ UINT8 ProcessorTDPLimitOverrideEnable;
+ UINT8 ProcessorTDPLimitOverrideEnableLockHide;
+
+ //
+ // Turbo-XE Mode Processor TDP Limit
+ //
+ UINT16 ProcessorTDPLimit;
+ UINT8 ProcessorTDPLimitLockHide;
+
+ //
+ // For changing UC to WB
+ //
+ UINT8 MTRRDefTypeUncachable;
+ UINT8 MTRRDefTypeUncachableLockHide;
+
+ //
+ // Virtual wire A or B
+ //
+ UINT8 ProcessorVirtualWireMode;
+ UINT8 ProcessorVirtualWireModeLockHide;
+
+ //
+ // Ext Burn in
+ //
+ UINT8 ExtBurnInEnable;
+ UINT8 ExtBurnInEnableLockHide;
+
+ //
+ // CPU Burn-in Enable 0/1 No/Yes
+ //
+ UINT8 CpuBurnInEnable;
+ UINT8 CpuBurnInEnableLockHide;
+
+ //
+ // CPU Power selection 0/1 Low/High
+ //
+ UINT8 CPUPow;
+ UINT8 CPUPowLockHide;
+
+ //
+ // VID Value to use (0-63)
+ //
+ UINT8 VIDVal;
+ UINT8 VIDValLockHide;
+
+ //
+ // BSEL Value to use (0-8)
+ //
+ UINT8 BSELVal;
+ UINT8 BSELValLockHide;
+
+ //
+ // VCore Burn-in Mode 0/1/2/3 1.500V/1.550V/1.600V/1.625V
+ //
+ UINT8 VCoreBurnIn;
+ UINT8 VCoreBurnInLockHide;
+
+ //
+ // VTT (Front Side Bus) Voltage Override
+ //
+ UINT8 VTtBurnIn;
+ UINT8 VTtBurnInLockHide;
+
+ //
+ // PCI E Burn In
+ //
+ UINT8 PCIeBurnIn;
+ UINT8 PCIeBurnInLockHide;
+
+ //
+ // FSB Override Automatic/Manual
+ //
+ UINT8 FsbOverride;
+ UINT8 FsbOverrideLockHide;
+
+ //
+ // FSB Frequency Override in MHz
+ //
+ UINT16 FsbFrequency;
+ UINT8 FsbFrequencyLockHide;
+
+ //
+ // Mailbox variables to store default, CPU Multiplier and FSB Frequency.
+ //
+ UINT16 DefFsbFrequency;
+
+ //
+ // Used as a CPU Voltage Status.
+ //
+ UINT8 VIDValStatus;
+
+ //
+ // Ecc 0/1 Disable/Enable if supported
+ //
+ UINT8 EccEnable;
+ UINT8 EccEnableLockHide;
+
+ //
+ // Memory
+ //
+ UINT8 MemoryMode;
+ UINT8 MemoryModeLockHide;
+
+ UINT16 MemorySpeed;
+ UINT8 MemorySpeedLockHide;
+
+ UINT8 UclkRatio;
+ UINT8 UclkRatioLockHide;
+
+ UINT8 MemoryRatio;
+ UINT8 MemoryRatioLockHide;
+
+ UINT8 MemoryTcl;
+ UINT8 MemoryTclLockHide;
+
+ UINT8 MemoryTrcd;
+ UINT8 MemoryTrcdLockHide;
+
+ UINT8 MemoryTrp;
+ UINT8 MemoryTrpLockHide;
+
+ UINT8 MemoryTras;
+ UINT8 MemoryTrasLockHide;
+
+ UINT16 MemoryTrfc;
+ UINT8 MemoryTrfcLockHide;
+
+ UINT8 MemoryTrrd;
+ UINT8 MemoryTrrdLockHide;
+
+ UINT8 MemoryTwr;
+ UINT8 MemoryTwrLockHide;
+
+ UINT8 MemoryTwtr;
+ UINT8 MemoryTwtrLockHide;
+
+ UINT8 MemoryTrtp;
+ UINT8 MemoryTrtpLockHide;
+
+ UINT8 MemoryTrc;
+ UINT8 MemoryTrcLockHide;
+
+ UINT8 MemoryTfaw;
+ UINT8 MemoryTfawLockHide;
+
+ UINT8 MemoryTcwl;
+ UINT8 MemoryTcwlLockHide;
+
+ UINT8 MemoryVoltage;
+ UINT8 MemoryVoltageLockHide;
+
+ //
+ // Reference Voltage Override
+ //
+ UINT8 DimmDqRef;
+ UINT8 DimmDqRefLockHide;
+ UINT8 DimmCaRef;
+ UINT8 DimmCaRefLockHide;
+
+ //
+ // Ratio Limit options for Turbo-Mode
+ //
+ UINT8 RatioLimit4C;
+ UINT8 RatioLimit4CLockHide;
+ UINT8 RatioLimit3C;
+ UINT8 RatioLimit3CLockHide;
+ UINT8 RatioLimit2C;
+ UINT8 RatioLimit2CLockHide;
+ UINT8 RatioLimit1C;
+ UINT8 RatioLimit1CLockHide;
+
+ //
+ // Port 80 decode 0/1 - PCI/LPC
+ UINT8 Port80Route;
+ UINT8 Port80RouteLockHide;
+
+ //
+ // ECC Event Logging
+ //
+ UINT8 EccEventLogging;
+ UINT8 EccEventLoggingLockHide;
+
+ //
+ // LT Technology 0/1 -> Disable/Enable
+ //
+ UINT8 LtTechnology;
+ UINT8 LtTechnologyLockHide;
+
+ //
+ // ICH Function Level Reset enable/disable
+ //
+ UINT8 FlrCapability;
+ UINT8 FlrCapabilityLockHide;
+
+ //
+ // VT-d Option
+ //
+ UINT8 VTdSupport;
+ UINT8 VTdSupportLockHide;
+
+ UINT8 InterruptRemap;
+ UINT8 InterruptRemapLockHide;
+
+ UINT8 Isoc;
+ UINT8 IsocLockHide;
+
+ UINT8 CoherencySupport;
+ UINT8 CoherencySupportLockHide;
+
+ UINT8 ATS;
+ UINT8 ATSLockHide;
+
+ UINT8 PassThroughDma;
+ UINT8 PassThroughDmaLockHide;
+
+ //
+ // IGD option
+ //
+ UINT8 GraphicsDriverMemorySize;
+ UINT8 GraphicsDriverMemorySizeLockHide;
+
+ //
+ // Hyper Threading
+ //
+ UINT8 ProcessorHtMode;
+ UINT8 ProcessorHtModeLockHide;
+
+ //
+ // IGD Aperture Size question
+ //
+ UINT8 IgdApertureSize;
+ UINT8 IgdApertureSizeLockHide;
+
+ //
+ // Boot Display Device
+ //
+ UINT8 BootDisplayDevice;
+ UINT8 BootDisplayDeviceLockHide;
+
+ //
+ // System fan speed duty cycle
+ //
+ UINT8 SystemFanDuty;
+ UINT8 SystemFanDutyLockHide;
+
+ //
+ // S3 state LED indicator
+ //
+ UINT8 S3StateIndicator;
+ UINT8 S3StateIndicatorLockHide;
+
+ //
+ // S1 state LED indicator
+ //
+ UINT8 S1StateIndicator;
+ UINT8 S1StateIndicatorLockHide;
+
+ //
+ // PS/2 Wake from S5
+ //
+ UINT8 WakeOnS5Keyboard;
+ UINT8 WakeOnS5KeyboardLockHide;
+
+ //
+ // PS2 port
+ //
+ UINT8 PS2;
+
+ //
+ // No VideoBeep
+ //
+ UINT8 NoVideoBeepEnable;
+
+ //
+ // Integrated Graphics Device
+ //
+ UINT8 Igd;
+
+ //
+ // Video Device select order
+ //
+ UINT8 VideoSelectOrder[8];
+
+ // Flash update sleep delay
+ UINT8 FlashSleepDelay;
+ UINT8 FlashSleepDelayLockHide;
+
+ //
+ // Boot Display Device2
+ //
+ UINT8 BootDisplayDevice2;
+ UINT8 BootDisplayDevice2LockHide;
+
+ //
+ // Flat Panel
+ //
+ UINT8 EdpInterfaceType;
+ UINT8 EdpInterfaceTypeLockHide;
+
+ UINT8 LvdsInterfaceType;
+ UINT8 LvdsInterfaceTypeLockHide;
+
+ UINT8 ColorDepth;
+ UINT8 ColorDepthLockHide;
+
+ UINT8 EdidConfiguration;
+ UINT8 EdidConfigurationLockHide;
+
+ UINT8 MaxInverterPWM;
+ UINT8 MaxInverterPWMLockHide;
+
+ UINT8 PreDefinedEdidConfiguration;
+ UINT8 PreDefinedEdidConfigurationLockHide;
+
+ UINT16 ScreenBrightnessResponseTime;
+ UINT8 ScreenBrightnessResponseTimeLockHide;
+
+ UINT8 CurrentSetupProfile;
+ UINT8 CurrentSetupProfileLockHide;
+
+ //
+ // FSC system Variable
+ //
+ UINT8 CPUFanUsage;
+ UINT8 CPUFanUsageLockHide;
+ UINT16 CPUUnderSpeedthreshold;
+ UINT8 CPUUnderSpeedthresholdLockHide;
+ UINT8 CPUFanControlMode;
+ UINT8 CPUFanControlModeLockHide;
+ UINT16 Voltage12UnderVolts;
+ UINT8 Voltage12UnderVoltsLockHide;
+ UINT16 Voltage12OverVolts;
+ UINT8 Voltage12OverVoltsLockHide;
+ UINT16 Voltage5UnderVolts;
+ UINT8 Voltage5UnderVoltsLockHide;
+ UINT16 Voltage5OverVolts;
+ UINT8 Voltage5OverVoltsLockHide;
+ UINT16 Voltage3p3UnderVolts;
+ UINT8 Voltage3p3UnderVoltsLockHide;
+ UINT16 Voltage3p3OverVolts;
+ UINT8 Voltage3p3OverVoltsLockHide;
+ UINT16 Voltage2p5UnderVolts;
+ UINT8 Voltage2p5UnderVoltsLockHide;
+ UINT16 Voltage2p5OverVolts;
+ UINT8 Voltage2p5OverVoltsLockHide;
+ UINT16 VoltageVccpUnderVolts;
+ UINT8 VoltageVccpUnderVoltsLockHide;
+ UINT16 VoltageVccpOverVolts;
+ UINT8 VoltageVccpOverVoltsLockHide;
+ UINT16 Voltage5BackupUnderVolts;
+ UINT8 Voltage5BackupUnderVoltsLockHide;
+ UINT16 Voltage5BackupOverVolts;
+ UINT8 Voltage5BackupOverVoltsLockHide;
+ UINT16 VS3p3StbyUnderVolt;
+ UINT8 VS3p3StbyUnderVoltLockHide;
+ UINT16 VS3p3StbyOverVolt;
+ UINT8 VS3p3StbyOverVoltLockHide;
+ UINT8 CPUFanMinDutyCycle;
+ UINT8 CPUFanMinDutyCycleLockHide;
+ UINT8 CPUFanMaxDutyCycle;
+ UINT8 CPUFanMaxDutyCycleLockHide;
+ UINT8 CPUFanOnDutyCycle;
+ UINT8 CPUFanOnDutyCycleLockHide;
+ UINT16 CpuOverTemp;
+ UINT8 CpuOverTempLockHide;
+ UINT16 CpuControlTemp;
+ UINT8 CpuControlTempLockHide;
+ UINT16 CpuAllOnTemp;
+ UINT8 CpuAllOnTempLockHide;
+ UINT8 CpuResponsiveness;
+ UINT8 CpuResponsivenessLockHide;
+ UINT8 CpuDamping;
+ UINT8 CpuDampingLockHide;
+ UINT8 PchDamping;
+ UINT8 PchDampingLockHide;
+ UINT16 MemoryOverTemp;
+ UINT8 MemoryOverTempLockHide;
+ UINT16 MemoryControlTemp;
+ UINT8 MemoryControlTempLockHide;
+ UINT16 MemoryAllOnTemp;
+ UINT8 MemoryAllOnTempLockHide;
+ UINT8 MemoryResponsiveness;
+ UINT8 MemoryResponsivenessLockHide;
+ UINT8 MemoryDamping;
+ UINT8 MemoryDampingLockHide;
+ UINT16 VROverTemp;
+ UINT8 VROverTempLockHide;
+ UINT16 VRControlTemp;
+ UINT8 VRControlTempLockHide;
+ UINT16 VRAllOnTemp;
+ UINT8 VRAllOnTempLockHide;
+ UINT8 VRResponsiveness;
+ UINT8 VRResponsivenessLockHide;
+ UINT8 VRDamping;
+ UINT8 VRDampingLockHide;
+
+ UINT8 LvdsBrightnessSteps;
+ UINT8 LvdsBrightnessStepsLockHide;
+ UINT8 EdpDataRate;
+ UINT8 EdpDataRateLockHide;
+ UINT16 LvdsPowerOnToBacklightEnableDelayTime;
+ UINT8 LvdsPowerOnToBacklightEnableDelayTimeLockHide;
+ UINT16 LvdsPowerOnDelayTime;
+ UINT8 LvdsPowerOnDelayTimeLockHide;
+ UINT16 LvdsBacklightOffToPowerDownDelayTime;
+ UINT8 LvdsBacklightOffToPowerDownDelayTimeLockHide;
+ UINT16 LvdsPowerDownDelayTime;
+ UINT8 LvdsPowerDownDelayTimeLockHide;
+ UINT16 LvdsPowerCycleDelayTime;
+ UINT8 LvdsPowerCycleDelayTimeLockHide;
+
+ UINT8 IgdFlatPanel;
+ UINT8 IgdFlatPanelLockHide;
+
+ UINT8 SwapMode;
+ UINT8 SwapModeLockHide;
+
+ UINT8 UsbCharging;
+ UINT8 UsbChargingLockHide;
+
+ UINT8 Cstates;
+ UINT8 EnableC4;
+ UINT8 EnableC6;
+
+ UINT8 FastBoot;
+ UINT8 EfiNetworkSupport;
+ UINT8 PxeRom;
+
+ //
+ // Add for PpmPlatformPolicy
+ //
+ UINT8 EnableGv;
+ UINT8 EnableCx;
+ UINT8 EnableCxe;
+ UINT8 EnableTm;
+ UINT8 EnableProcHot;
+ UINT8 TStatesEnable;
+ UINT8 HTD;
+ UINT8 SingleCpu;
+ UINT8 BootPState;
+ UINT8 FlexRatio;
+ UINT8 FlexVid;
+ UINT8 QuietBoot;
+ UINT8 CsmControl;
+ UINT8 BoardId; // Need to detect Board Id during setup option for CR
+
+ UINT8 MinInverterPWM;
+ //
+ // Thermal Policy Values
+ //
+ UINT8 EnableDigitalThermalSensor;
+ UINT8 PassiveThermalTripPoint;
+ UINT8 PassiveTc1Value;
+ UINT8 PassiveTc2Value;
+ UINT8 PassiveTspValue;
+ UINT8 DisableActiveTripPoints;
+ UINT8 CriticalThermalTripPoint;
+ UINT8 DeepStandby;
+ UINT8 AlsEnable;
+ UINT8 IgdLcdIBia;
+ UINT8 LogBootTime;
+ //
+ // EM-1 related
+ //
+ UINT16 IaAppsRun;
+ UINT16 IaAppsRunCR;
+ UINT8 IaAppsCap;
+ UINT8 CapOrVoltFlag;
+ UINT8 BootOnInvalidBatt;
+
+ UINT8 IffsEnable;
+ UINT8 IffsOnS3RtcWake;
+ UINT8 IffsS3WakeTimerMin;
+ UINT8 IffsOnS3CritBattWake;
+ UINT8 IffsCritBattWakeThreshold;
+ UINT8 ScramblerSupport;
+ UINT8 SecureBoot;
+ UINT8 SecureBootCustomMode;
+ UINT8 SecureBootUserPhysicalPresent;
+ UINT8 CoreFreMultipSelect;
+ UINT8 MaxCState;
+ UINT8 PanelScaling;
+ UINT8 IgdLcdIGmchBlc;
+ UINT8 SecEnable;
+ UINT8 SecFlashUpdate;
+ UINT8 SecFirmwareUpdate;
+ UINT8 MeasuredBootEnable;
+ UINT8 UseProductKey;
+ //
+ // Image Signal Processor PCI Device Configuration
+ //
+ UINT8 ISPDevSel;
+ UINT8 ISPEn;
+
+ UINT8 Tdt;
+ UINT8 Recovery;
+ UINT8 Suspend;
+
+ UINT8 TdtState;
+ UINT8 TdtEnrolled;
+ UINT8 PBAEnable;
+ //
+ // ISCT Configuration
+ //
+ UINT8 IsctConfiguration;
+ UINT8 IsctNotificationControl;
+ UINT8 IsctWlanPowerControl;
+ UINT8 IsctWwanPowerControl;
+ UINT8 IsctSleepDurationFormat;
+ UINT8 IsctRFKillSupport;
+ UINT8 WlanNGFFCardPresence;
+ UINT8 WlanUHPAMCardPresence;
+ UINT8 PchFSAOn; //FSA control
+
+ //
+ // South Cluster Area - START
+ //
+ //
+ // Miscellaneous options
+ //
+ UINT8 SmbusEnabled;
+ UINT8 PchSirq;
+ UINT8 PchSirqMode;
+ UINT8 Hpet;
+ UINT8 HpetBootTime;
+ UINT8 EnableClockSpreadSpec;
+ UINT8 EnablePciClockSpreadSpec;
+ UINT8 EnableUsb3ClockSpreadSpec;
+ UINT8 EnableDisplayClockSpreadSpec;
+ UINT8 EnableSataClockSpreadSpec;
+ UINT8 StateAfterG3;
+ UINT8 UartInterface;
+ UINT8 IspLpePltClk;
+ UINT8 UsbDebug;
+ UINT8 ConfigureCfioOnSx;
+ //
+ // Security Config
+ //
+ UINT8 PchRtcLock;
+ UINT8 PchBiosLock;
+
+ //
+ // SCC Configuration
+ //
+ UINT8 ScceMMCEnabled;
+ UINT8 SccSdioEnabled;
+ UINT8 SccSdcardEnabled;
+ //
+ // LPSS Configuration
+ //
+ UINT8 GpioAcpiEnabled;
+ UINT16 Sdcard1p8vSwitchingDelay;
+ UINT16 Sdcard3p3vDischargeDelay;
+ UINT8 LpssDma1Enabled;
+ UINT8 LpssI2C0Enabled;
+ UINT8 LpssI2C1Enabled;
+ UINT8 LpssI2C2Enabled;
+ UINT8 LpssI2C3Enabled;
+ UINT8 LpssI2C4Enabled;
+ UINT8 LpssI2C5Enabled;
+ UINT8 LpssI2C6Enabled;
+ UINT8 LpssDma0Enabled;
+ UINT8 LpssPwm0Enabled;
+ UINT8 LpssPwm1Enabled;
+ UINT8 LpssHsuart0Enabled;
+ UINT8 LpssHsuart1Enabled;
+ UINT8 LpssSpi1Enabled;
+ UINT8 LpssSpi2Enabled;
+ UINT8 LpssSpi3Enabled;
+ UINT8 I2CTouchAd;
+ UINT8 BTModule;
+ UINT8 RvpCameraDevSel;
+ UINT8 EbCameraDevSel;
+ UINT8 SecureNfc;
+ UINT8 Bcm4356;
+ UINT8 GpsEnable;
+
+ //
+ // Usb Config
+ //
+ UINT8 PchUsb30Mode;
+ UINT8 PchSsicEnable;
+ UINT8 PchUsbSsicHsRate;
+ UINT8 PchUsbSsicInitSequence;
+ UINT8 PchUsbSsicPort[PCH_SSIC_MAX_PORTS];
+ UINT8 PchUsbHsicPort[PCH_HSIC_MAX_PORTS];
+ UINT8 PchUsb2PhyPgEnabled;
+ UINT8 PchUsbOtg;
+ UINT8 PchUsbVbusOn; // OTG VBUS control
+
+ //
+ // Ish Config
+ //
+ UINT8 PchIshEnabled;
+ UINT8 IshDebuggerEnabled;
+
+ //
+ // SATA Config
+ //
+ UINT8 PchSata;
+ UINT8 SataInterfaceMode;
+ UINT8 SataInterfaceSpeed;
+ UINT8 SataPort[2];
+ UINT8 SataHotPlug[2];
+ UINT8 SataMechanicalSw[2];
+ UINT8 SataSpinUp[2];
+ UINT8 SataDevSlp[2];
+ UINT8 SataExternal[2];
+ UINT8 SataRaidR0;
+ UINT8 SataRaidR1;
+ UINT8 SataRaidR10;
+ UINT8 SataRaidR5;
+ UINT8 SataRaidIrrt;
+ UINT8 SataRaidOub;
+ UINT8 SataHddlk;
+ UINT8 SataLedl;
+ UINT8 SataRaidIooe;
+ UINT8 SataAlternateId;
+ UINT8 SataSalp;
+ UINT8 SataTestMode;
+
+ //
+ // PCI_EXPRESS_CONFIG, 4 ROOT PORTS
+ //
+ UINT8 PcieRootPortEn[PCH_PCIE_MAX_ROOT_PORTS];
+ UINT8 PcieRootPortAspm[PCH_PCIE_MAX_ROOT_PORTS];
+ UINT8 PcieRootPortURE[PCH_PCIE_MAX_ROOT_PORTS];
+ UINT8 PcieRootPortFEE[PCH_PCIE_MAX_ROOT_PORTS];
+ UINT8 PcieRootPortNFE[PCH_PCIE_MAX_ROOT_PORTS];
+ UINT8 PcieRootPortCEE[PCH_PCIE_MAX_ROOT_PORTS];
+ UINT8 PcieRootPortSFE[PCH_PCIE_MAX_ROOT_PORTS];
+ UINT8 PcieRootPortSNE[PCH_PCIE_MAX_ROOT_PORTS];
+ UINT8 PcieRootPortSCE[PCH_PCIE_MAX_ROOT_PORTS];
+ UINT8 PcieRootPortPMCE[PCH_PCIE_MAX_ROOT_PORTS];
+ UINT8 PcieRootPortESE[PCH_PCIE_MAX_ROOT_PORTS];
+ UINT8 PcieRootPortHPE[PCH_PCIE_MAX_ROOT_PORTS];
+ UINT8 PcieRootPortSpeed[PCH_PCIE_MAX_ROOT_PORTS];
+ UINT8 PcieRootPortTHS[PCH_PCIE_MAX_ROOT_PORTS];
+ UINT8 PcieRootPortL1SubStates[PCH_PCIE_MAX_ROOT_PORTS];
+ UINT8 PcieRootPortNccSsc[PCH_PCIE_MAX_ROOT_PORTS];
+ UINT8 PcieRootPortTxEqDeemphSelection[PCH_PCIE_MAX_ROOT_PORTS];
+
+ //
+ // PCI Bridge Resources
+ //
+ UINT8 PcieExtraBusRsvd[PCH_PCIE_MAX_ROOT_PORTS];
+ UINT8 PcieMemRsvd[PCH_PCIE_MAX_ROOT_PORTS];
+ UINT8 PcieIoRsvd[PCH_PCIE_MAX_ROOT_PORTS];
+
+ //
+ // PCI Express S0ix Config
+ //
+ UINT8 PcieS0iX;
+ UINT8 D0S0IxPolicy;
+ UINT8 ClkReqEnable;
+ UINT8 ClkReq;
+ UINT8 LtrLatencyScale;
+ UINT8 LtrLatencyValue;
+
+ //
+ // Audio Configuration
+ //
+ UINT8 PchLpeEnabled;
+ UINT8 PchAzalia;
+ UINT8 AzaliaVCiEnable;
+ UINT8 AzaliaDs;
+ UINT8 AzaliaPme;
+ UINT8 HdmiCodec;
+ UINT8 HdmiCodecPortB;
+ UINT8 HdmiCodecPortC;
+ UINT8 HdmiCodecPortD;
+ //
+ // South Cluster Area - END
+ //
+
+ UINT8 GTTSize;
+ //
+ // DVMT5.0 Graphic memory setting
+ //
+ UINT8 IgdDvmt50PreAlloc;
+ UINT8 IgdDvmt50TotalAlloc;
+ UINT8 IgdTurboEnabled;
+ UINT8 EnableRenderStandby;
+ UINT8 GOPEnable;
+ UINT8 GOPBrightnessLevel; // Gop Brightness level
+ UINT8 PanelConfig;
+ UINT8 PanelVendor;
+ UINT8 PavpMode;
+ UINT8 EnablePR3;
+ UINT8 Wopcmsz;
+ UINT8 UnsolicitedAttackOverride;
+
+ UINT8 SeCOpEnable;
+ UINT8 SeCModeEnable;
+ UINT8 SeCEOPEnable;
+ UINT8 SeCEOPDone;
+
+ UINT8 LidStatus;
+ UINT8 PowerMeterLock;
+ UINT8 EuControl;
+ UINT8 SdpProfile; // DPTF: an enumeration for Brand Strings.
+ UINT8 CameraSelect;
+ UINT8 F22Rework;
+ UINT8 EnableDptf; // Option to enable/disable DPTF
+ UINT16 ProcCriticalTemp; // Processor critical temperature
+ UINT16 ProcPassiveTemp; // Processor passive temperature
+
+ UINT16 ActiveThermalTripPointSA; // Processor active temperature
+ UINT16 CriticalThermalTripPointSA; // Processor critical temperature
+ UINT16 CR3ThermalTripPointSA; // Processor CR3 temperature
+ UINT16 HotThermalTripPointSA; // Processor Hot temperature
+ UINT16 PassiveThermalTripPointSA; // Processor passive temperature
+
+ UINT16 GenericActiveTemp0; // Active temperature value for generic sensor0 participant
+ UINT16 GenericCriticalTemp0; // Critical temperature value for generic sensor0 participant
+ UINT16 GenericCR3Temp0; // CR3 temperature value for generic sensor0 participant
+ UINT16 GenericHotTemp0; // Hot temperature value for generic sensor0 participant
+ UINT16 GenericPassiveTemp0; // Passive temperature value for generic sensor0 participant
+ UINT16 GenericActiveTemp1; // Active temperature value for generic sensor1 participant
+ UINT16 GenericCriticalTemp1; // Critical temperature value for generic sensor1 participant
+ UINT16 GenericCR3Temp1; // CR3 temperature value for generic sensor1 participant
+ UINT16 GenericHotTemp1; // Hot temperature value for generic sensor1 participant
+ UINT16 GenericPassiveTemp1; // Passive temperature value for generic sensor1 participant
+ UINT16 GenericActiveTemp2; // Active temperature value for generic sensor2 participant
+ UINT16 GenericCriticalTemp2; // Critical temperature value for generic sensor2 participant
+ UINT16 GenericCR3Temp2; // CR3 temperature value for generic sensor2 participant
+ UINT16 GenericHotTemp2; // Hot temperature value for generic sensor2 participant
+ UINT16 GenericPassiveTemp2; // Passive temperature value for generic sensor2 participant
+ UINT16 GenericCriticalTemp3; // Critical temperature value for generic sensor3 participant
+ UINT16 GenericPassiveTemp3; // Passive temperature value for generic sensor3 participant
+ UINT16 GenericCriticalTemp4; // Critical temperature value for generic sensor3 participant
+ UINT16 GenericPassiveTemp4; // Passive temperature value for generic sensor3 participant
+ UINT8 Clpm; // Current low power mode
+ UINT8 SuperDebug; // DPTF Super debug option
+ UINT32 LPOEnable; // DPTF: Instructs the policy to use Active Cores if they are available. If this option is set to 0, then policy does not use any active core controls ?even if they are available
+ UINT32 LPOStartPState; // DPTF: Instructs the policy when to initiate Active Core control if enabled. Returns P state index.
+ UINT32 LPOStepSize; // DPTF: Instructs the policy to take away logical processors in the specified percentage steps
+ UINT32 LPOPowerControlSetting; // DPTF: Instructs the policy whether to use Core offliing or SMT offlining if Active core control is enabled to be used in P0 or when power control is applied. 1 ?SMT Off lining 2- Core Off lining
+ UINT32 LPOPerformanceControlSetting; // DPTF: Instructs the policy whether to use Core offliing or SMT offlining if Active core control is enabled to be used in P1 or when performance control is applied.1 ?SMT Off lining 2- Core Off lining
+ UINT8 EnableDppm; // DPTF: Controls DPPM Policies (enabled/disabled)
+ UINT8 DptfProcessor;
+ UINT8 DptfSysThermal0;
+ UINT8 DptfSysThermal1;
+ UINT8 DptfSysThermal2;
+ UINT8 DptfSysThermal3;
+ UINT8 DptfSysThermal4;
+ UINT8 DptfChargerDevice;
+ UINT8 DptfDisplayDevice;
+ UINT8 DptfSocDevice;
+ UINT8 BidirectionalProchotEnable;
+ UINT8 ThermalMonitoring;
+ UINT8 ThermalMonitoringHot;
+ UINT8 ThermalMonitoringSystherm0Hot;
+ UINT8 ThermalMonitoringSystherm1Hot;
+ UINT8 ThermalMonitoringSystherm2Hot;
+ UINT8 DisplayHighLimit;
+ UINT8 DisplayLowLimit;
+ UINT8 AmbientConstants[6];
+ UINT8 AmbientConstantSign[6];
+ UINT8 AmbientTripPointChange; // DPTF: Controls whether _ATI changes other participant's trip point(enabled/disabled)
+ UINT8 DptfAllowHigherPerformance; // DPTF: Allow higher performance on AC/USB - (Enable/Disable)
+ UINT8 DptfWwanDevice; // DPTF: Presence of WWAN Device
+ UINT32 DptfWwanCrt; // DPTF: WWAN critical temperature
+ UINT32 DptfWwanPsv; // DPTF: WWAN Passive Temperature
+ UINT8 EnablePassivePolicy; // DPTF: Passive Policy enable/disable
+ UINT8 EnableCriticalPolicy; // DPTF: Critical Policy enable/disable
+ UINT8 EnableActivePolicy; // DPTF: Active Policy enable/disable
+ UINT8 PmicEnable;
+ UINT8 S0ix;
+ UINT8 TSEGSizeSel;
+ UINT8 ACPIMemDbg;
+ UINT8 ExISupport;
+ UINT8 BatteryChargingSolution; // 0-non ULPMC 1-ULPMC
+
+ UINT8 PnpSettings;
+ UINT8 MfgMode;
+ UINT8 CRIDSettings;
+ UINT8 ULPMCFWLock;
+ UINT8 PssEnabled;
+ UINT8 PmWeights;
+ UINT8 PdmEnable;
+ UINT8 PDMConfig;
+ UINT16 LmMemSize;
+ UINT8 PunitBIOSConfig;
+ UINT8 LpssSdioMode;
+ UINT8 ENDBG2;
+ UINT8 IshPullUp;
+ UINT8 TristateLpc;
+ UINT8 UsbXhciLpmSupport;
+ UINT8 VirtualKbEnable;
+ UINT8 SlpS0ixN;
+ UINT8 EnableAESNI;
+ UINT8 SecureErase;
+
+ //
+ // Memory Config Tools
+ //
+ UINT8 MrcEvRMT;
+ UINT8 MrcCmdRMT;
+ UINT8 MrcDvfsEnable;
+ UINT8 MrcFreqASel;
+ UINT8 MrcFreqBSel;
+ UINT8 MrcLPDDR3ChipSel;
+ UINT8 MrcChannelSel;
+ UINT8 MrcDynamicSr;
+ UINT8 MrcChannelSel_3_0;
+ UINT8 MrcChannelSel_4;
+ UINT8 MrcAutoDetectDram;
+ UINT8 Sku;
+ UINT8 MrcPm5Enable;
+ UINT8 MrcBankAddressHashingEnable;
+ UINT8 MrcRankSelInterleave;
+ UINT8 MrcConfigChanged;
+ UINT8 MrcDdrType;
+ UINT8 MrcDdr2nMode;
+ UINT8 MrcRxPwrTrainingDisable;
+ UINT8 MrcTxPwrTrainingDisable;
+ UINT8 MrcFastBootDisable;
+ UINT8 MrcScramblerDisable;
+ UINT8 MrcSpeedGrade;
+ UINT8 MrcLPDDR3DeviceDensity;
+ UINT8 MrcDebugMsgLevel;
+ UINT8 DrpLockDisable;
+ UINT8 ReutLockDisable;
+ UINT8 RhPrevention;
+
+ UINT8 MmioSize;
+ UINT8 DroidBoot;
+ UINT8 AndroidBoot;
+ UINT8 Ellensburg;
+ UINT8 CriticalBatteryLimit;
+ UINT8 CriticalBatteryLimitFeature;
+ UINT8 EmmcDriverMode;
+ UINT8 EmmcRxTuningEnable;
+ UINT8 EmmcTxTuningEnable;
+
+ UINT8 SAR1;
+
+ UINT8 DisableCodec262;
+ UINT8 PcieDynamicGating; // Need PMC enable it first from PMC 0x3_12 MCU 318.
+ UINT8 VirtualButtonEnable;
+ UINT8 RotationLock;
+ UINT8 ConvertibleState;
+ UINT8 DockIndicator;
+ UINT8 WIFIModule;
+ UINT8 SvidConfig;
+ UINT8 PciExpNative;
+ UINT8 OsSelection;
+ UINT8 PlatformDirectOsSelect; //If set to 1 (TRUE), platform method (GPI on Cherry Hill) will be used to select OS.
+ //If set to 0 (FALSE), OS selection option in setup menu will be used to select OS.
+
+ UINT8 MipiDsi;
+ UINT8 AndroidSBIntegration;
+ UINT8 AcpiDevNodeDis;
+ UINT8 AcpiModemSel;
+
+ //
+ // SPID config region
+ //
+ UINT8 SPIDAutoDetect;
+ UINT16 SPIDCustomerID;
+ UINT16 SPIDVendorID;
+ UINT16 SPIDDeviceManufacturerID;
+ UINT16 SPIDPlatformFamilyID;
+ UINT16 SPIDProductLineID;
+ UINT16 SPIDHardwareID;
+ UINT8 SPIDFru[20];
+ //
+ // OEM1 table
+ //
+ UINT8 BatIdDbiBase;
+ UINT8 BatIdAnlgBase;
+ UINT16 VBattFreqLimit;
+ UINT8 CapFreqIdx;
+ UINT8 BTHStatus;
+ UINT8 AudioCodecSuppport;
+ UINT8 ChargingEnable;
+ UINT8 ChargingLpmEnable;
+ UINT16 Str2TspValue;
+ UINT8 VBIOS5f35h;
+ UINT8 VBIOS5f40h;
+ UINT8 Backlight;
+ UINT8 PunitPwrConfigDisable;
+ UINT8 FlashLessMdm;
+ UINT8 EnableMSCustomSdbusDriver;
+
+#ifdef PRAM_SUPPORT
+ UINT8 PramSize;
+#endif
+ UINT8 XdbGpioTrst;
+ UINT8 FirstBootIndicator;
+ UINT8 ConnectAllCtrlsFlag;
+ UINT8 EnterDnxFastBoot;
+ UINT8 ToggleSelfClkDisabling;
+ UINT8 GPSHIDSelection;
+ UINT8 HighPerfMode;
+
+} SYSTEM_CONFIGURATION;
+#pragma pack()
+
+#ifndef PLATFORM_SETUP_VARIABLE_NAME
+#define PLATFORM_SETUP_VARIABLE_NAME L"Setup"
+#endif
+
+//
+// #defines for Drive Presence
+//
+#define EFI_HDD_PRESENT 0x01
+#define EFI_HDD_NOT_PRESENT 0x00
+#define EFI_CD_PRESENT 0x02
+#define EFI_CD_NOT_PRESENT 0x00
+
+#define EFI_HDD_WARNING_ON 0x01
+#define EFI_CD_WARNING_ON 0x02
+#define EFI_SMART_WARNING_ON 0x04
+#define EFI_HDD_WARNING_OFF 0x00
+#define EFI_CD_WARNING_OFF 0x00
+#define EFI_SMART_WARNING_OFF 0x00
+
+#ifndef VFRCOMPILE
+extern EFI_GUID gEfiSetupVariableGuid;
+#endif
+
+#define SETUP_DATA SYSTEM_CONFIGURATION
+
+#endif // #ifndef _SETUP_VARIABLE
diff --git a/BraswellPlatformPkg/Common/Include/Hpet.h b/BraswellPlatformPkg/Common/Include/Hpet.h new file mode 100644 index 0000000000..9ee47d9274 --- /dev/null +++ b/BraswellPlatformPkg/Common/Include/Hpet.h @@ -0,0 +1,35 @@ +/** @file
+ This file describes the contents of the ACPI HPET Table.
+
+ Copyright (c) 2004 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _HPET_H
+#define _HPET_H
+
+//
+// Statements that include other files
+//
+#include <IndustryStandard/Acpi10.h>
+#include <IndustryStandard/Acpi20.h>
+#include <IndustryStandard/Acpi30.h>
+#include <IndustryStandard/HighPrecisionEventTimerTable.h>
+
+//
+// HPET Definitions
+//
+#define EFI_ACPI_HPET_TABLE_REVISION 0x1
+#define MAIN_COUNTER_MIN_PERIODIC_CLOCK_TICKS 0x80 //approx 1ms
+
+#define HPET_BASE_ADDRESS 0xFED00000
+#define EFI_ACPI_EVENT_TIMER_BLOCK_ID 0x8086A201
+#endif
diff --git a/BraswellPlatformPkg/Common/Include/KscLib.h b/BraswellPlatformPkg/Common/Include/KscLib.h new file mode 100644 index 0000000000..985c43dcb3 --- /dev/null +++ b/BraswellPlatformPkg/Common/Include/KscLib.h @@ -0,0 +1,282 @@ +/** @file
+ KSC library functions and definitions.
+
+ This library provides basic KSC interface. It is deemed simple enough and uses in
+ so few cases that there is not currently benefit to implementing a protocol.
+ If more consumers are added, it may be benefitial to implement as a protocol.
+
+ There may be different libraries for different environments (PEI, BS, RT, SMM).
+ Make sure you meet the requirements for the library (protocol dependencies, use
+ restrictions, etc).
+
+ Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _KSC_LIB_H_
+#define _KSC_LIB_H_
+
+//
+// Include files
+//
+#include <Library/BaseLib.h>
+
+//
+// Timeout if KSC command/data fails
+//
+#define KSC_TIME_OUT 0x20000
+
+//
+// The Keyboard and System management Controller (KSC) implements a standard 8042 keyboard
+// controller interface at ports 0x60/0x64 and a ACPI compliant system management controller
+// at ports 0x62/0x66. Port 0x66 is the command and status port, port 0x62 is the data port.
+//
+#define KSC_D_PORT 0x62
+#define KSC_C_PORT 0x66
+
+//
+// Status Port 0x62
+//
+#define KSC_S_OVR_TMP 0x80 // Current CPU temperature exceeds the threshold
+#define KSC_S_SMI_EVT 0x40 // SMI event is pending
+#define KSC_S_SCI_EVT 0x20 // SCI event is pending
+#define KSC_S_BURST 0x10 // KSC is in burst mode or normal mode
+#define KSC_S_CMD 0x08 // Byte in data register is command/data
+#define KSC_S_IGN 0x04 // Ignored
+#define KSC_S_IBF 0x02 // Input buffer is full/empty
+#define KSC_S_OBF 0x01 // Output buffer is full/empty
+
+//
+// KSC commands that are issued to the KSC through the command port (0x66).
+// New commands and command parameters should only be written by the host when IBF=0.
+// Data read from the KSC data port is valid only when OBF=1.
+//
+#define KSC_C_SMI_NOTIFY_ENABLE 0x04 // Enable SMI notifications to the host
+#define KSC_C_SMI_NOTIFY_DISABLE 0x05 // SMI notifications are disabled and pending notifications cleared
+#define KSC_C_QUERY_SYS_STATUS 0x06 // Returns 1 byte of information about the system status
+#define KSC_B_SYS_STATUS_FAN 0x40 // Fan status (1 = ON)
+#define KSC_B_SYS_STATUS_DOCK 0x20 // Dock status (1 = Docked)
+#define KSC_B_SYS_STATUS_AC 0x10 // AC power (1 = AC powered)
+#define KSC_B_SYS_STATUS_THERMAL 0x0F // CPU thermal state (0 ~ 9)
+#define KSC_C_QUERY_BOARD_ID_BIT 0x0A // Board Id 8 or 16 bit
+#define KSC_B_BOARD_ID_BIT_16 0x80 // Bit7 =1 means 16 bit implementation
+#define KSC_C_FAB_ID 0x0D // Get the board fab ID in the lower 3 bits
+#define KSC_C_SYSTEM_POWER_OFF 0x22 // Turn off the system power
+#define KSC_C_NIC_PRESENCE 0X27 // WLAN NIC Card presence Information
+#define KSC_C_LAN_ON 0x46 // Turn on the power to LAN through EC/KSC
+#define KSC_C_LAN_OFF 0x47 // Turn off the power to LAN through EC/KSC
+#define KSC_C_GET_TEMP 0x50 // Returns the CPU temperature as read from the SMBus thermal sensor.
+#define KSC_C_SET_CTEMP 0x58 // The next byte written to the data port will be the shutdown temperature
+#define KSC_EC_PCH_SMBUS_EN 0x60 // EC PCH SMBus thermal monitoring Enable cmd
+#define KSC_EC_PCH_SMBUS_DIS 0x61 // EC PCH SMBus thermal monitoring Disable cmd
+#define KSC_TS_ON_DIMM_EN 0x6B // TS-on-DIMM thermal monitoring enable command
+#define KSC_TS_ON_DIMM_DIS 0x6C // TS-on-DIMM thermal monitoring disable command
+#define KSC_C_PCH_SMBUS_MSG_LENGTH 0x6D // PCH SMBus block read buffer length
+#define KSC_C_PCH_SMBUS_PEC_EN 0x6E // PCH SMBus Packet Error Checking (PEC) Enable command.
+#define KSC_C_PCH_SMBUS_PEC_DIS 0x76 // PCH SMBus Packet Error Checking (PEC) Disable command.
+#define KSC_C_GETWAKE_STATUS 0x76 // Get wake Event status command
+#define KSC_C_CLEARWAKE_STATUS 0x77 // Clear wake Event status command
+#define KSC_C_EC_SMBUS_HIGH_SPEED 0x75 // EC SMBus high speed mode command
+#define KSC_EC_PCH_SMBUS_WRITE_EN 0x68 // EC PCH SMBus Write Enable cmd
+#define KSC_EC_PCH_SMBUS_WRITE_DIS 0x69 // EC PCH SMBus Write Disable cmd
+#define KSC_C_SMI_QUERY 0x70 // The host reads the data port to retrieve the notifications
+#define KSC_C_SMI_TIMER 0x71 // Commands the KSC to generate a periodic SMI to the host
+#define KSC_C_SMI_HOTKEY 0x72 // Get the scan code of hotkey pressed (CTRL + ALT + SHIFT + key)
+#define KSC_C_READ_MEM 0x80 // Read the KSC memory
+#define KSC_C_WRITE_MEM 0x81 // Write the KSC memory
+#define KSC_C_DOCK_STATUS 0x8A // Get the dock status
+#define KSC_B_DOCK_STATUS_ATTACH 0x01 // Dock status (1 = Attach)
+#define KSC_C_KSC_REVISION 0x90 // Get the revision for the KSC
+#define KSC_C_SMI_INJECT 0xBA // The next byte written to the data port will generate an immediate SMI
+#define KSC_C_SMI_DISABLE 0xBC // SMI generation by the KSC is disabled
+#define KSC_C_SMI_ENABLE 0xBD // SMI generation by the KSC is enabled
+#define KSC_C_ACPI_ENABLE 0xAA // Enable ACPI mode
+#define KSC_C_ACPI_DISABLE 0xAB // Disable ACPI mode
+
+//
+// KSC commands that are only valid if the EC has ACPI mode enabled.
+// Note that capacity and voltage are 16 bit values, thus you need to read them from
+// ACPI space with two reads (little Endian).
+//
+#define KSC_VIRTUAL_BAT_STATUS 48 // Status of the virtual battery (present)
+#define KSC_VIRTUAL_BAT_PRESENT_MASK 0x10 // Bit 4 is the indicator
+
+#define KSC_REAL_BAT1_STATUS 50 // Status of the first real battery (present, charging)
+#define KSC_REAL_BAT1_REMAINING_CAPACITY 89 // Remaining capacity in mWh
+#define KSC_REAL_BAT1_RESOLUTION_VOLTAGE 93 // Full resolution voltage in mV
+
+#define KSC_REAL_BAT2_STATUS 54 // Status of the second real battery (present, charging)
+#define KSC_REAL_BAT2_REMAINING_CAPACITY 99 // Remaining capacity in mWh
+#define KSC_REAL_BAT2_RESOLUTION_VOLTAGE 103 // Full resolution voltage in mV
+
+#define KSC_REAL_BAT_PRESENT_MASK 0x8 // Bit 3 is the indicator
+#define KSC_REAL_BAT_CHARGING_MASK 0x1 // Bit 1 is the indicator
+
+//
+// SMI notification code table, read through command KSC_C_SMI_QUERY
+//
+#define KSC_N_SMI_NULL 0x00 // Null marks the end of the SMI notification queue
+#define KSC_N_SMI_HOTKEY 0x20 // Hotkey pressed SMI
+#define KSC_N_SMI_ACINSERTION 0x30 // AC insertion SMI
+#define KSC_N_SMI_ACREMOVAL 0x31 // AC removal SMI
+#define KSC_N_SMI_PWRSW 0x32 // Power switch press SMI
+#define KSC_N_SMI_LID 0x33 // Lid switch change SMI
+#define KSC_N_SMI_VB 0x34 // Virtual battery switch change SMI
+#define KSC_N_SMI_THERM_0 0x60 // Thermal state 0 SMI
+#define KSC_N_SMI_THERM_1 0x61 // Thermal state 1 SMI
+#define KSC_N_SMI_THERM_2 0x62 // Thermal state 2 SMI
+#define KSC_N_SMI_THERM_3 0x63 // Thermal state 3 SMI
+#define KSC_N_SMI_THERM_4 0x64 // Thermal state 4 SMI
+#define KSC_N_SMI_THERM_5 0x65 // Thermal state 5 SMI
+#define KSC_N_SMI_THERM_6 0x66 // Thermal state 6 SMI
+#define KSC_N_SMI_THERM_7 0x67 // Thermal state 7 SMI
+#define KSC_N_SMI_THERM_8 0x68 // Thermal state 8 SMI
+#define KSC_N_SMI_DOCKED 0x70 // Dock complete SMI
+#define KSC_N_SMI_UNDOCKED 0x71 // Undock complete SMI
+#define KSC_N_SMI_UNDOCKREQUEST 0x72 // Undocking request SMI
+#define KSC_N_SMI_TIMER 0x80 // Timer wakeup SMI
+
+//
+// Hotkey scan code (CTRL + ALT + SHIFT + key)
+//
+#define KSC_HK_ESC 0x01 // ESC
+#define KSC_HK_1 0x02 // 1 !
+#define KSC_HK_2 0x03 // 2 @
+#define KSC_HK_3 0x04 // 3 #
+#define KSC_HK_4 0x05 // 4 $
+#define KSC_HK_5 0x06 // 5 %
+#define KSC_HK_6 0x07 // 6 ^
+#define KSC_HK_7 0x08 // 7 &
+#define KSC_HK_8 0x09 // 8 *
+#define KSC_HK_9 0x0A // 9 (
+#define KSC_HK_0 0x0B // 0 )
+#define KSC_HK_MINUS 0x0C // - _
+#define KSC_HK_ADD 0x0D // = +
+#define KSC_HK_F1 0x3B // F1
+#define KSC_HK_F2 0x3C // F2
+#define KSC_HK_F3 0x3D // F3
+#define KSC_HK_F4 0x3E // F4
+#define KSC_HK_F5 0x3F // F5
+#define KSC_HK_F6 0x40 // F6
+#define KSC_HK_F7 0x41 // F7
+#define KSC_HK_F8 0x42 // F8
+#define KSC_HK_F9 0x43 // F9
+#define KSC_HK_F10 0x44 // F10
+#define KSC_HK_F11 0x57 // F11
+#define KSC_HK_F12 0x58 // F12
+
+//
+// Function declarations
+//
+/**
+Routine Description:
+
+ This function initializes the KSC library.
+ It must be called before using any of the other KSC library functions.
+
+Arguments:
+
+ None.
+
+Returns:
+
+ EFI_SUCCESS - KscLib is successfully initialized.
+
+**/
+EFI_STATUS
+InitializeKscLib (
+ VOID
+ );
+
+/**
+Routine Description:
+
+ Send a command to the Keyboard System Controller.
+
+Arguments:
+
+ Command - Command byte to send
+
+Returns:
+
+ EFI_SUCCESS - Command success
+ EFI_TIMEOUT - Command timeout
+ Other - Command failed
+
+**/
+EFI_STATUS
+SendKscCommand (
+ UINT8 Command
+ );
+
+/**
+Routine Description:
+
+ Sends data to Keyboard System Controller.
+
+Arguments:
+
+ Data - Data byte to send
+
+Returns:
+
+ EFI_SUCCESS - Success
+ EFI_TIMEOUT - Timeout
+ Other - Failed
+
+**/
+EFI_STATUS
+SendKscData (
+ UINT8 Data
+ );
+
+/**
+Routine Description:
+
+ Receives data from Keyboard System Controller.
+
+Arguments:
+
+ Data - Data byte received
+
+Returns:
+
+ EFI_SUCCESS - Read success
+ EFI_TIMEOUT - Read timeout
+ Other - Read failed
+
+**/
+EFI_STATUS
+ReceiveKscData (
+ UINT8 *Data
+ );
+
+/**
+Routine Description:
+
+ Receives status from Keyboard System Controller.
+
+Arguments:
+
+ Status - Status byte to receive
+
+Returns:
+
+ EFI_SUCCESS - Success
+ Other - Failed
+
+**/
+EFI_STATUS
+ReceiveKscStatus (
+ UINT8 *KscStatus
+ );
+
+#endif
diff --git a/BraswellPlatformPkg/Common/Include/Library/BiosIdLib.h b/BraswellPlatformPkg/Common/Include/Library/BiosIdLib.h new file mode 100644 index 0000000000..b80c57265e --- /dev/null +++ b/BraswellPlatformPkg/Common/Include/Library/BiosIdLib.h @@ -0,0 +1,99 @@ +/** @file
+ BIOS ID library definitions.
+ This library provides functions to get BIOS ID, VERSION, DATE and TIME.
+
+ Copyright (c) 2004 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _BIOS_ID_LIB_H_
+#define _BIOS_ID_LIB_H_
+
+//
+// BIOS ID string format:
+//
+// $(BOARD_ID)$(BOARD_REV).$(OEM_ID).$(VERSION_MAJOR).$(BUILD_TYPE)$(VERSION_MINOR).YYMMDDHHMM
+//
+// Example: "TRFTCRB1.86C.0008.D03.0506081529"
+//
+#pragma pack(1)
+
+typedef struct {
+ CHAR16 BoardId[7]; // "TRFTCRB"
+ CHAR16 BoardRev; // "1"
+ CHAR16 Dot1; // "."
+ CHAR16 OemId[3]; // "86C"
+ CHAR16 Dot2; // "."
+ CHAR16 VersionMajor[4]; // "0008"
+ CHAR16 Dot3; // "."
+ CHAR16 BuildType; // "D"
+ CHAR16 VersionMinor[2]; // "03"
+ CHAR16 Dot4; // "."
+ CHAR16 TimeStamp[10]; // "YYMMDDHHMM"
+ CHAR16 NullTerminator; // 0x0000
+} BIOS_ID_STRING;
+
+#define MEM_IFWIVER_START 0x7E0000
+#define MEM_IFWIVER_LENGTH 0x1000
+
+typedef struct _MANIFEST_OEM_DATA{
+ UINT32 Signature;
+ unsigned char FillNull[0x39];
+ UINT32 IFWIVersionLen;
+ unsigned char IFWIVersion[32];
+}MANIFEST_OEM_DATA;
+
+//
+// A signature precedes the BIOS ID string in the FV to enable search by external tools.
+//
+typedef struct {
+ UINT8 Signature[8]; // "$IBIOSI$"
+ BIOS_ID_STRING BiosIdString; // "TRFTCRB1.86C.0008.D03.0506081529"
+} BIOS_ID_IMAGE;
+
+#pragma pack()
+
+/**
+ This function returns BIOS ID by searching HOB or FV.
+
+ @param[in] BiosIdImage The BIOS ID got from HOB or FV
+
+ @retval EFI_SUCCESS All parameters were valid and BIOS ID has been got.
+ @retval EFI_NOT_FOUND BiosId image is not found, and no parameter will be modified.
+ @retval EFI_INVALID_PARAMETER The parameter is NULL.
+
+**/
+EFI_STATUS
+GetBiosId (
+ OUT BIOS_ID_IMAGE *BiosIdImage
+ );
+
+/**
+ This function returns the Version & Release Date and Time by getting and converting
+ BIOS ID.
+
+ @param[in] BiosVersion The Bios Version out of the conversion.
+ @param[in] BiosReleaseDate The Bios Release Date out of the conversion.
+ @param[in] BiosReleaseTime The Bios Release Time out of the conversion.
+
+ @retval EFI_SUCCESS BIOS Version & Release Date and Time have been got successfully.
+ @retval EFI_NOT_FOUND BiosId image is not found, and no parameter will be modified.
+ @retval EFI_INVALID_PARAMETER All the parameters are NULL.
+
+**/
+EFI_STATUS
+GetBiosVersionDateTime (
+ OUT CHAR16 *BiosVersion, OPTIONAL
+ OUT CHAR16 *BiosReleaseDate, OPTIONAL
+ OUT CHAR16 *BiosReleaseTime OPTIONAL
+ );
+
+#endif
diff --git a/BraswellPlatformPkg/Common/Include/Library/CpuIA32.h b/BraswellPlatformPkg/Common/Include/Library/CpuIA32.h new file mode 100644 index 0000000000..fef98e9c53 --- /dev/null +++ b/BraswellPlatformPkg/Common/Include/Library/CpuIA32.h @@ -0,0 +1,341 @@ +/** @file
+ Copyright (c) 2004 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _CPU_IA32_H
+#define _CPU_IA32_H
+
+typedef struct {
+ UINT32 RegEax;
+ UINT32 RegEbx;
+ UINT32 RegEcx;
+ UINT32 RegEdx;
+} EFI_CPUID_REGISTER;
+
+typedef struct {
+ UINT32 HeaderVersion;
+ UINT32 UpdateRevision;
+ UINT32 Date;
+ UINT32 ProcessorId;
+ UINT32 Checksum;
+ UINT32 LoaderRevision;
+ UINT32 ProcessorFlags;
+ UINT32 DataSize;
+ UINT32 TotalSize;
+ UINT8 Reserved[12];
+} EFI_CPU_MICROCODE_HEADER;
+
+typedef struct {
+ UINT32 ExtendedSignatureCount;
+ UINT32 ExtendedTableChecksum;
+ UINT8 Reserved[12];
+} EFI_CPU_MICROCODE_EXTENDED_TABLE_HEADER;
+
+typedef struct {
+ UINT32 ProcessorSignature;
+ UINT32 ProcessorFlag;
+ UINT32 ProcessorChecksum;
+} EFI_CPU_MICROCODE_EXTENDED_TABLE;
+
+typedef struct {
+ UINT32 Stepping : 4;
+ UINT32 Model : 4;
+ UINT32 Family : 4;
+ UINT32 Type : 2;
+ UINT32 Reserved1 : 2;
+ UINT32 ExtendedModel : 4;
+ UINT32 ExtendedFamily : 8;
+ UINT32 Reserved2 : 4;
+} EFI_CPU_VERSION;
+
+#define EFI_CPUID_SIGNATURE 0x0
+#define EFI_CPUID_VERSION_INFO 0x1
+#define EFI_CPUID_CACHE_INFO 0x2
+#define EFI_CPUID_SERIAL_NUMBER 0x3
+#define EFI_CPUID_EXTENDED_FUNCTION 0x80000000
+#define EFI_CPUID_EXTENDED_CPU_SIG 0x80000001
+#define EFI_CPUID_BRAND_STRING1 0x80000002
+#define EFI_CPUID_BRAND_STRING2 0x80000003
+#define EFI_CPUID_BRAND_STRING3 0x80000004
+
+#define EFI_MSR_IA32_PLATFORM_ID 0x17
+#define EFI_MSR_IA32_APIC_BASE 0x1B
+#define EFI_MSR_EBC_HARD_POWERON 0x2A
+#define EFI_MSR_EBC_SOFT_POWERON 0x2B
+#define BINIT_DRIVER_DISABLE 0x40
+#define INTERNAL_MCERR_DISABLE 0x20
+#define INITIATOR_MCERR_DISABLE 0x10
+#define EFI_MSR_EBC_FREQUENCY_ID 0x2C
+#define EFI_MSR_IA32_BIOS_UPDT_TRIG 0x79
+#define EFI_MSR_IA32_BIOS_SIGN_ID 0x8B
+#define EFI_MSR_PSB_CLOCK_STATUS 0xCD
+#define EFI_APIC_GLOBAL_ENABLE 0x800
+#define EFI_MSR_IA32_MISC_ENABLE 0x1A0
+#define LIMIT_CPUID_MAXVAL_ENABLE_BIT 0x00400000
+#define AUTOMATIC_THERMAL_CONTROL_ENABLE_BIT 0x00000008
+#define COMPATIBLE_FPU_OPCODE_ENABLE_BIT 0x00000004
+#define LOGICAL_PROCESSOR_PRIORITY_ENABLE_BIT 0x00000002
+#define FAST_STRING_ENABLE_BIT 0x00000001
+
+#define EFI_CACHE_VARIABLE_MTRR_BASE 0x200
+#define EFI_CACHE_VARIABLE_MTRR_END 0x20F
+#define EFI_CACHE_IA32_MTRR_DEF_TYPE 0x2FF
+#define EFI_CACHE_MTRR_VALID 0x800
+#define EFI_CACHE_FIXED_MTRR_VALID 0x400
+#define EFI_CACHE_VALID_ADDRESS 0xFFFFFF000
+#define EFI_MSR_VALID_MASK 0xFFFFFFFFF
+#define EFI_CACHE_VALID_EXTENDED_ADDRESS 0xFFFFFFFFFF000
+#define EFI_MSR_VALID_EXTENDED_MASK 0xFFFFFFFFFFFFF
+
+#define EFI_IA32_MTRR_FIX64K_00000 0x250
+#define EFI_IA32_MTRR_FIX16K_80000 0x258
+#define EFI_IA32_MTRR_FIX16K_A0000 0x259
+#define EFI_IA32_MTRR_FIX4K_C0000 0x268
+#define EFI_IA32_MTRR_FIX4K_C8000 0x269
+#define EFI_IA32_MTRR_FIX4K_D0000 0x26A
+#define EFI_IA32_MTRR_FIX4K_D8000 0x26B
+#define EFI_IA32_MTRR_FIX4K_E0000 0x26C
+#define EFI_IA32_MTRR_FIX4K_E8000 0x26D
+#define EFI_IA32_MTRR_FIX4K_F0000 0x26E
+#define EFI_IA32_MTRR_FIX4K_F8000 0x26F
+
+#define EFI_IA32_MCG_CAP 0x179
+#define EFI_IA32_MCG_CTL 0x17B
+#define EFI_IA32_MC0_CTL 0x400
+#define EFI_IA32_MC0_STATUS 0x401
+
+#define EFI_IA32_PERF_STATUS 0x198
+#define EFI_IA32_PERF_CTL 0x199
+
+#define EFI_CACHE_UNCACHEABLE 0
+#define EFI_CACHE_WRITECOMBINING 1
+#define EFI_CACHE_WRITETHROUGH 4
+#define EFI_CACHE_WRITEPROTECTED 5
+#define EFI_CACHE_WRITEBACK 6
+
+//
+// Combine f(FamilyId), m(Model), s(SteppingId) to a single 32 bit number
+//
+#define EfiMakeCpuVersion(f, m, s) \
+ (((UINT32) (f) << 16) | ((UINT32) (m) << 8) | ((UINT32) (s)))
+
+/**
+ Halt the Cpu
+
+ @param[in] None
+
+ @retval None
+
+**/
+VOID
+EFIAPI
+EfiHalt (
+ VOID
+ );
+
+/**
+ Write back and invalidate the Cpu cache
+
+ @param[in] None
+
+ @retval None
+
+**/
+VOID
+EFIAPI
+EfiWbinvd (
+ VOID
+ );
+
+/**
+ Invalidate the Cpu cache
+
+ @param[in] None
+
+ @retval None
+
+**/
+VOID
+EFIAPI
+EfiInvd (
+ VOID
+ );
+
+/**
+ Get the Cpu info by excute the CPUID instruction
+
+ @param[in] RegisterInEax The input value to put into register EAX
+ @param[in] Regs The Output value
+
+ @retval None
+
+**/
+VOID
+EFIAPI
+EfiCpuid (
+ IN UINT32 RegisterInEax,
+ OUT EFI_CPUID_REGISTER *Regs
+ );
+
+/**
+ When RegisterInEax != 4, the functionality is the same as EfiCpuid.
+ When RegisterInEax == 4, the function return the deterministic cache
+ parameters by excuting the CPUID instruction.
+
+ @param[in] RegisterInEax The input value to put into register EAX.
+ @param[in] CacheLevel The deterministic cache level.
+ @param[in] Regs The Output value.
+
+ @retval None
+
+**/
+VOID
+EFIAPI
+EfiCpuidExt (
+ IN UINT32 RegisterInEax,
+ IN UINT32 CacheLevel,
+ OUT EFI_CPUID_REGISTER *Regs
+ );
+
+/**
+ Read Cpu MSR
+
+ @param[in] Index The index value to select the register
+
+ @retval Return the read data
+
+**/
+UINT64
+EFIAPI
+EfiReadMsr (
+ IN UINT32 Index
+ );
+
+/**
+ Write Cpu MSR
+
+ @param[in] Index The index value to select the register
+ @param[in] Value The value to write to the selected register
+
+ @retval None
+
+**/
+VOID
+EFIAPI
+EfiWriteMsr (
+ IN UINT32 Index,
+ IN UINT64 Value
+ );
+
+/**
+ Read Time stamp
+
+ @param[in] None
+
+ @retval Return the read data
+
+**/
+UINT64
+EFIAPI
+EfiReadTsc (
+ VOID
+ );
+
+/**
+ Writing back and invalidate the cache,then diable it
+
+ @param[in] None
+
+ @retval None
+
+**/
+VOID
+EFIAPI
+EfiDisableCache (
+ VOID
+ );
+
+/**
+ Invalidate the cache,then Enable it
+
+ @param[in] None
+
+ @retval None
+
+**/
+VOID
+EFIAPI
+EfiEnableCache (
+ VOID
+ );
+
+/**
+ Get Eflags
+
+ @param[in] None
+
+ @retval Return the Eflags value
+
+**/
+UINT32
+EFIAPI
+EfiGetEflags (
+ VOID
+ );
+
+/**
+ Disable Interrupts
+
+ @param[in] None
+
+ @retval None
+
+**/
+VOID
+EFIAPI
+EfiDisableInterrupts (
+ VOID
+ );
+
+/**
+ Enable Interrupts
+
+ @param[in] None
+
+ @retval None
+
+**/
+VOID
+EFIAPI
+EfiEnableInterrupts (
+ VOID
+ );
+
+/**
+ Extract CPU detail version infomation
+
+ @param[in] FamilyId FamilyId, including ExtendedFamilyId
+ @param[in] Model Model, including ExtendedModel
+ @param[in] SteppingId SteppingId
+ @param[in] Processor Processor
+
+**/
+VOID
+EFIAPI
+EfiCpuVersion (
+ IN UINT16 *FamilyId, OPTIONAL
+ IN UINT8 *Model, OPTIONAL
+ IN UINT8 *SteppingId, OPTIONAL
+ IN UINT8 *Processor OPTIONAL
+ );
+
+#endif
diff --git a/BraswellPlatformPkg/Common/Include/Library/EfiRegTableLib.h b/BraswellPlatformPkg/Common/Include/Library/EfiRegTableLib.h new file mode 100644 index 0000000000..20350b808f --- /dev/null +++ b/BraswellPlatformPkg/Common/Include/Library/EfiRegTableLib.h @@ -0,0 +1,186 @@ +/** @file
+ Definitions and macros for building register tables for chipset
+ initialization.
+
+ Components linking this lib must include CpuIo, PciRootBridgeIo, and
+ BootScriptSave protocols in their DPX.
+
+ Copyright (c) 2004 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED
+
+**/
+
+#ifndef EFI_REG_TABLE_H
+#define EFI_REG_TABLE_H
+
+#include <PiDxe.h>
+#include <Library/BaseLib.h>
+#include <Library/DebugLib.h>
+#include <Library/UefiLib.h>
+#include <Library/UefiDriverEntryPoint.h>
+#include <Protocol/CpuIo.h>
+#include <Protocol/BootScriptSave.h>
+#include <Framework/BootScript.h>
+#include <Protocol/PciRootBridgeIo.h>
+
+#define OPCODE_BASE(OpCode) ((UINT8)((OpCode) & 0xFF))
+#define OPCODE_FLAGS(OpCode) ((UINT8)(((OpCode) >> 8) & 0xFF))
+#define OPCODE_EXTRA_DATA(OpCode) ((UINT16)((OpCode) >> 16))
+
+//
+// RegTable Base OpCodes
+//
+#define OP_TERMINATE_TABLE 0
+#define OP_MEM_WRITE 1
+#define OP_MEM_READ_MODIFY_WRITE 2
+#define OP_IO_WRITE 3
+#define OP_IO_READ_MODIFY_WRITE 4
+#define OP_PCI_WRITE 5
+#define OP_PCI_READ_MODIFY_WRITE 6
+#define OP_STALL 7
+
+//
+// RegTable OpCode Flags
+//
+#define OPCODE_FLAG_S3SAVE 1
+
+#define TERMINATE_TABLE { (UINT32) OP_TERMINATE_TABLE, (UINT32) 0, (UINT32) 0 }
+
+//
+// REG_TABLE_ENTRY_PCI_WRITE encodes the width in the upper bits of the OpCode
+// as one of the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH values
+//
+typedef struct {
+ UINT32 OpCode;
+ UINT32 PciAddress;
+ UINT32 Data;
+} EFI_REG_TABLE_PCI_WRITE;
+
+#define PCI_WRITE(Bus, Dev, Fnc, Reg, Width, Data, S3Flag) \
+ { \
+ (UINT32) (OP_PCI_WRITE | ((S3Flag) << 8) | ((Width) << 16)), \
+ (UINT32) (EFI_PCI_ADDRESS ((Bus), (Dev), (Fnc), (Reg))), \
+ (UINT32) (Data), \
+ (UINT32) (0) \
+ }
+
+typedef struct {
+ UINT32 OpCode;
+ UINT32 MemAddress;
+ UINT32 Data;
+} EFI_REG_TABLE_MEM_WRITE;
+
+typedef struct {
+ UINT32 OpCode;
+ UINT32 PciAddress;
+ UINT32 OrMask;
+ UINT32 AndMask;
+} EFI_REG_TABLE_PCI_READ_MODIFY_WRITE;
+
+#define PCI_READ_MODIFY_WRITE(Bus, Dev, Fnc, Reg, Width, OrMask, AndMask, S3Flag) \
+ { \
+ (UINT32) (OP_PCI_READ_MODIFY_WRITE | ((S3Flag) << 8) | ((Width) << 16)), \
+ (UINT32) (EFI_PCI_ADDRESS ((Bus), (Dev), (Fnc), (Reg))), \
+ (UINT32) (OrMask), \
+ (UINT32) (AndMask) \
+ }
+
+typedef struct {
+ UINT32 OpCode;
+ UINT32 MemAddress;
+ UINT32 OrMask;
+ UINT32 AndMask;
+} EFI_REG_TABLE_MEM_READ_MODIFY_WRITE;
+
+#define MEM_READ_MODIFY_WRITE(Address, Width, OrMask, AndMask, S3Flag) \
+ { \
+ (UINT32) (OP_MEM_READ_MODIFY_WRITE | ((S3Flag) << 8) | ((Width) << 16)), \
+ (UINT32) (Address), \
+ (UINT32) (OrMask), \
+ (UINT32) (AndMask) \
+ }
+
+typedef struct {
+ UINT32 OpCode;
+ UINT32 Field2;
+ UINT32 Field3;
+ UINT32 Field4;
+} EFI_REG_TABLE_GENERIC;
+
+typedef union {
+ EFI_REG_TABLE_GENERIC Generic;
+ EFI_REG_TABLE_PCI_WRITE PciWrite;
+ EFI_REG_TABLE_PCI_READ_MODIFY_WRITE PciReadModifyWrite;
+ EFI_REG_TABLE_MEM_READ_MODIFY_WRITE MemReadModifyWrite;
+} EFI_REG_TABLE;
+
+/**
+ Processes register table assuming which may contain PCI, IO, MEM, and STALL
+ entries.
+
+ No parameter checking is done so the caller must be careful about omitting
+ values for PciRootBridgeIo or CpuIo parameters. If the regtable does
+ not contain any PCI accesses, it is safe to omit the PciRootBridgeIo (supply
+ NULL). If the regtable does not contain any IO or Mem entries, it is safe to
+ omit the CpuIo (supply NULL).
+
+ The RegTableEntry parameter is not checked, but is required.
+
+ gBS is assumed to have been defined and is used when processing stalls.
+
+ The function processes each entry sequentially until an OP_TERMINATE_TABLE
+ entry is encountered.
+
+ @param[in] RegTableEntry A pointer to the register table to process
+
+ @param[in] PciRootBridgeIo A pointer to the instance of PciRootBridgeIo that is used
+ when processing PCI table entries
+
+ @param[in] CpuIo A pointer to the instance of CpuIo that is used when processing IO and
+ MEM table entries
+
+ @retval Nothing.
+
+**/
+VOID
+ProcessRegTablePci (
+ EFI_REG_TABLE * RegTableEntry,
+ EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL * PciRootBridgeIo,
+ EFI_CPU_IO_PROTOCOL * CpuIo
+ );
+
+/**
+ Processes register table assuming which may contain IO, MEM, and STALL
+ entries, but must NOT contain any PCI entries. Any PCI entries cause an
+ ASSERT in a DEBUG build and are skipped in a free build.
+
+ No parameter checking is done. Both RegTableEntry and CpuIo parameters are
+ required.
+
+ gBS is assumed to have been defined and is used when processing stalls.
+
+ The function processes each entry sequentially until an OP_TERMINATE_TABLE
+ entry is encountered.
+
+ @param[in] RegTableEntry - A pointer to the register table to process
+
+ @param[in] CpuIo - A pointer to the instance of CpuIo that is used when processing IO and
+ MEM table entries
+
+ @retval Nothing.
+
+**/
+VOID
+ProcessRegTableCpu (
+ EFI_REG_TABLE * RegTableEntry,
+ EFI_CPU_IO_PROTOCOL * CpuIo
+ );
+
+#endif
diff --git a/BraswellPlatformPkg/Common/Include/Library/FlashDeviceLib.h b/BraswellPlatformPkg/Common/Include/Library/FlashDeviceLib.h new file mode 100644 index 0000000000..58c93bcc04 --- /dev/null +++ b/BraswellPlatformPkg/Common/Include/Library/FlashDeviceLib.h @@ -0,0 +1,116 @@ +/** @file
+ Flash device library class header file.
+
+ Flash Device Library common type, MACRO and API definition. The basic idea for
+ this library is to provide API to abstract the different between flash
+ technology (SPI, FWH etc..), flash controller (SPI host controller on
+ ICH, MMIO type access for FWH), flash chip (programming command, method
+ of status checking). This library class can be consumed by drivers or applications
+ such as Firmware Volume Block driver, Flash Update application. These driver
+ can be written in a generic manner so that they are more easy to be
+ ported to other platforms.
+
+ Copyright (c) 2004 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __FLASHDEVICE_LIB_H__
+#define __FLASHDEVICE_LIB_H__
+
+/**
+ Read NumBytes bytes of data from the address specified by
+ PAddress into Buffer.
+
+ @param[in] PAddress The starting physical address of the read.
+ @param[in,out] NumBytes On input, the number of bytes to read. On output, the number
+ of bytes actually read.
+ @param[out] Buffer The destination data buffer for the read.
+
+ @retval EFI_SUCCESS. Opertion is successful.
+ @retval EFI_DEVICE_ERROR If there is any device errors.
+
+**/
+EFI_STATUS
+EFIAPI
+LibFvbFlashDeviceRead (
+ IN UINTN PAddress,
+ IN OUT UINTN *NumBytes,
+ OUT UINT8 *Buffer
+ );
+
+/**
+ Write NumBytes bytes of data from Buffer to the address specified by
+ PAddresss.
+
+ @param[in] PAddress The starting physical address of the write.
+ @param[in, out] NumBytes On input, the number of bytes to write. On output,
+ the actual number of bytes written.
+ @param[in] Buffer The source data buffer for the write.
+
+ @retval EFI_SUCCESS. Opertion is successful.
+ @retval EFI_DEVICE_ERROR If there is any device errors.
+
+**/
+EFI_STATUS
+EFIAPI
+LibFvbFlashDeviceWrite (
+ IN UINTN PAddress,
+ IN OUT UINTN *NumBytes,
+ IN UINT8 *Buffer
+ );
+
+/**
+ Erase the block staring at PAddress.
+
+ @param[in] PAddress The starting physical address of the region to be erased.
+ @param[in] LbaLength The length of the region to be erased. This parameter is necessary
+ as the physical block size on a flash device could be different than
+ the logical block size of Firmware Volume Block protocol. Erase on
+ flash chip is always performed block by block. Therefore, the ERASE
+ operation to a logical block is converted a number of ERASE operation
+ (or a partial erase) on the hardware.
+
+ @retval EFI_SUCCESS. Opertion is successful.
+ @retval EFI_DEVICE_ERROR If there is any device errors.
+
+**/
+EFI_STATUS
+EFIAPI
+LibFvbFlashDeviceBlockErase (
+ IN UINTN PAddress,
+ IN UINTN LbaLength
+);
+
+/**
+ Lock or unlock the block staring at PAddress.
+
+ @param[in] PAddress The starting physical address of region to be (un)locked.
+ @param[in] LbaLength The length of the region to be (un)locked. This parameter is necessary
+ as the physical block size on a flash device could be different than
+ the logical block size of Firmware Volume Block protocol. (Un)Lock on
+ flash chip is always performed block by block. Therefore, the (Un)Lock
+ operation to a logical block is converted a number of (Un)Lock operation
+ (or a partial erase) on the hardware.
+ @param[in] Lock TRUE to lock. FALSE to unlock.
+
+ @retval EFI_SUCCESS. Opertion is successful.
+
+**/
+EFI_STATUS
+EFIAPI
+LibFvbFlashDeviceBlockLock (
+ IN UINTN PAddress,
+ IN UINTN LbaLength,
+ IN BOOLEAN Lock
+);
+
+#endif
+
diff --git a/BraswellPlatformPkg/Common/Include/Library/PlatformSerialPortLib.h b/BraswellPlatformPkg/Common/Include/Library/PlatformSerialPortLib.h new file mode 100644 index 0000000000..7ff7f4d217 --- /dev/null +++ b/BraswellPlatformPkg/Common/Include/Library/PlatformSerialPortLib.h @@ -0,0 +1,179 @@ +/** @file
+ This library class provides common serial I/O port functions.
+
+Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution. The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __SERIAL_PORT_LIB__
+#define __SERIAL_PORT_LIB__
+
+#include <Uefi/UefiBaseType.h>
+#include <Protocol/SerialIo.h>
+
+/**
+ Initialize the serial device hardware.
+
+ If no initialization is required, then return RETURN_SUCCESS.
+ If the serial device was successfully initialized, then return RETURN_SUCCESS.
+ If the serial device could not be initialized, then return RETURN_DEVICE_ERROR.
+
+ @retval RETURN_SUCCESS The serial device was initialized.
+ @retval RETURN_DEVICE_ERROR The serial device could not be initialized.
+
+**/
+RETURN_STATUS
+EFIAPI
+SerialPortInitialize (
+ VOID
+ );
+
+/**
+ Write data from buffer to serial device.
+
+ Writes NumberOfBytes data bytes from Buffer to the serial device.
+ The number of bytes actually written to the serial device is returned.
+ If the return value is less than NumberOfBytes, then the write operation failed.
+ If Buffer is NULL, then ASSERT().
+ If NumberOfBytes is zero, then return 0.
+
+ @param Buffer Pointer to the data buffer to be written.
+ @param NumberOfBytes Number of bytes to written to the serial device.
+
+ @retval 0 NumberOfBytes is 0.
+ @retval >0 The number of bytes written to the serial device.
+ If this value is less than NumberOfBytes, then the read operation failed.
+
+**/
+UINTN
+EFIAPI
+SerialPortWrite (
+ IN UINT8 *Buffer,
+ IN UINTN NumberOfBytes
+ );
+
+
+/**
+ Read data from serial device and save the datas in buffer.
+
+ Reads NumberOfBytes data bytes from a serial device into the buffer
+ specified by Buffer. The number of bytes actually read is returned.
+ If the return value is less than NumberOfBytes, then the rest operation failed.
+ If Buffer is NULL, then ASSERT().
+ If NumberOfBytes is zero, then return 0.
+
+ @param Buffer Pointer to the data buffer to store the data read from the serial device.
+ @param NumberOfBytes Number of bytes which will be read.
+
+ @retval 0 Read data failed, no data is to be read.
+ @retval >0 Actual number of bytes read from serial device.
+
+**/
+UINTN
+EFIAPI
+SerialPortRead (
+ OUT UINT8 *Buffer,
+ IN UINTN NumberOfBytes
+ );
+
+/**
+ Polls a serial device to see if there is any data waiting to be read.
+
+ Polls a serial device to see if there is any data waiting to be read.
+ If there is data waiting to be read from the serial device, then TRUE is returned.
+ If there is no data waiting to be read from the serial device, then FALSE is returned.
+
+ @retval TRUE Data is waiting to be read from the serial device.
+ @retval FALSE There is no data waiting to be read from the serial device.
+
+**/
+BOOLEAN
+EFIAPI
+SerialPortPoll (
+ VOID
+ );
+
+/**
+ Sets the control bits on a serial device.
+
+ @param Control Sets the bits of Control that are settable.
+
+ @retval RETURN_SUCCESS The new control bits were set on the serial device.
+ @retval RETURN_UNSUPPORTED The serial device does not support this operation.
+ @retval RETURN_DEVICE_ERROR The serial device is not functioning correctly.
+
+**/
+RETURN_STATUS
+EFIAPI
+SerialPortSetControl (
+ IN UINT32 Control
+ );
+
+/**
+ Retrieve the status of the control bits on a serial device.
+
+ @param Control A pointer to return the current control signals from the serial device.
+
+ @retval RETURN_SUCCESS The control bits were read from the serial device.
+ @retval RETURN_UNSUPPORTED The serial device does not support this operation.
+ @retval RETURN_DEVICE_ERROR The serial device is not functioning correctly.
+
+**/
+RETURN_STATUS
+EFIAPI
+SerialPortGetControl (
+ OUT UINT32 *Control
+ );
+
+/**
+ Sets the baud rate, receive FIFO depth, transmit/receice time out, parity,
+ data bits, and stop bits on a serial device.
+
+ @param BaudRate The requested baud rate. A BaudRate value of 0 will use the
+ device's default interface speed.
+ On output, the value actually set.
+ @param ReveiveFifoDepth The requested depth of the FIFO on the receive side of the
+ serial interface. A ReceiveFifoDepth value of 0 will use
+ the device's default FIFO depth.
+ On output, the value actually set.
+ @param Timeout The requested time out for a single character in microseconds.
+ This timeout applies to both the transmit and receive side of the
+ interface. A Timeout value of 0 will use the device's default time
+ out value.
+ On output, the value actually set.
+ @param Parity The type of parity to use on this serial device. A Parity value of
+ DefaultParity will use the device's default parity value.
+ On output, the value actually set.
+ @param DataBits The number of data bits to use on the serial device. A DataBits
+ vaule of 0 will use the device's default data bit setting.
+ On output, the value actually set.
+ @param StopBits The number of stop bits to use on this serial device. A StopBits
+ value of DefaultStopBits will use the device's default number of
+ stop bits.
+ On output, the value actually set.
+
+ @retval RETURN_SUCCESS The new attributes were set on the serial device.
+ @retval RETURN_UNSUPPORTED The serial device does not support this operation.
+ @retval RETURN_INVALID_PARAMETER One or more of the attributes has an unsupported value.
+ @retval RETURN_DEVICE_ERROR The serial device is not functioning correctly.
+
+**/
+RETURN_STATUS
+EFIAPI
+SerialPortSetAttributes (
+ IN OUT UINT64 *BaudRate,
+ IN OUT UINT32 *ReceiveFifoDepth,
+ IN OUT UINT32 *Timeout,
+ IN OUT EFI_PARITY_TYPE *Parity,
+ IN OUT UINT8 *DataBits,
+ IN OUT EFI_STOP_BITS_TYPE *StopBits
+ );
+
+#endif
diff --git a/BraswellPlatformPkg/Common/Include/Library/RecoveryOemHookLib.h b/BraswellPlatformPkg/Common/Include/Library/RecoveryOemHookLib.h new file mode 100644 index 0000000000..efa0ae33aa --- /dev/null +++ b/BraswellPlatformPkg/Common/Include/Library/RecoveryOemHookLib.h @@ -0,0 +1,70 @@ +/** @file
+ This library includes the recovery function that can be customized by OEM,
+ including how to select the recovery capsule if more than one capsule found,
+ and security check.
+
+ Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+
+#ifndef __RECOVERY_OEM_HOOK_LIB_H__
+#define __RECOVERY_OEM_HOOK_LIB_H__
+
+/**
+ The recovery capsule is determined by 2 factors,
+ 1. The device search order, if more than one Device Recovery Module PPI
+ was discovered
+ 2. The individual search order, if the device reported more than one recovery
+ DXE capsule was found generating a search order list.
+
+ The 2 orders are decided by the RecoveryOemHook library function OemRecoveryRankCapsule().
+
+ @param[in, out] DeviceInstance Specifies which EFI_PEI_DEVICE_RECOVERY_MODULE_PPI instance
+ to retrieve when passed out. Specifies which EFI_PEI_DEVICE_RECOVERY_MODULE_PPI
+ instance retrieved last time when passed in, start from zero.
+ @param[in, out] CapsuleInstance Specifies which recovery capsule to retrieve when passed out.
+ Specifies which recovery capsule retrieved last time when passed in, start from zero.
+ @param[out] DeviceRecoveryModule If it's not NULL, it's EFI_PEI_DEVICE_RECOVERY_MODULE_PPI.
+ instance specified by DeviceInstance, caller can use this instance directly. The
+ function will change DeviceRecoveryModule to NULL, if it doesn't return a PPI instance.
+ @param[out] CapsuleBuffer If it's not NULL, it contains loaded capsule, caller can use it directly.
+ The function will change Buffer to NULL, if it doesn't load a capsule.
+
+ @retval TRUE If a recovery capsule is found.
+ @retval FALSE If no recovery capsule found.
+
+**/
+BOOLEAN
+EFIAPI
+OemRecoveryRankCapsule (
+ IN OUT UINTN *DeviceInstance,
+ IN OUT UINTN *CapsuleInstance,
+ OUT EFI_PEI_DEVICE_RECOVERY_MODULE_PPI **DeviceRecoveryModule, OPTIONAL
+ OUT VOID **CapsuleBuffer OPTIONAL
+ );
+
+/**
+ This function performe security check and check failure handling,
+
+ @param Buffer The caller allocated buffer that contains recovery capsule to be checked.
+
+ @retval TRUE If it's secure.
+ @retval FALSE If it's not secure.
+
+**/
+BOOLEAN
+EFIAPI
+OemRecoverySecurityCheck (
+ VOID *Buffer
+ );
+
+#endif
diff --git a/BraswellPlatformPkg/Common/Include/Library/SmmIoLib.h b/BraswellPlatformPkg/Common/Include/Library/SmmIoLib.h new file mode 100644 index 0000000000..acef7e5e14 --- /dev/null +++ b/BraswellPlatformPkg/Common/Include/Library/SmmIoLib.h @@ -0,0 +1,177 @@ +/** @file
+ This library provides SMM functions for IO and PCI IO access.
+ These can be used to save size and simplify code.
+ All contents must be runtime and SMM safe.
+
+ Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _SMM_IO_LIB_H_
+#define _SMM_IO_LIB_H_
+
+#include "PiDxe.h"
+#include <Protocol/SmmCpuIo2.h>
+#include <IndustryStandard/Pci22.h>
+#include <Library/DebugLib.h>
+//
+// Utility consumed protocols
+//
+#include <Protocol/SmmBase2.h>
+
+//
+// Global variables that must be defined and initialized to use this library
+//
+extern EFI_SMM_SYSTEM_TABLE2 *mSmst;
+
+//
+// Pci I/O related data structure deifinition
+//
+typedef enum {
+ SmmPciWidthUint8 = 0,
+ SmmPciWidthUint16 = 1,
+ SmmPciWidthUint32 = 2,
+ SmmPciWidthUint64 = 3,
+ SmmPciWidthMaximum
+} SMM_PCI_IO_WIDTH;
+
+#define SMM_PCI_ADDRESS(bus,dev,func,reg) \
+ ((UINT64) ( (((UINT32)bus) << 24) + \
+ (((UINT32)dev) << 16) + \
+ (((UINT32)func) << 8) + \
+ ( (UINT32)reg)) )
+
+typedef struct {
+ UINT8 Register;
+ UINT8 Function;
+ UINT8 Device;
+ UINT8 Bus;
+ UINT32 ExtendedRegister;
+} SMM_PCI_IO_ADDRESS;
+
+//
+// CPU I/O Access Functions
+//
+
+UINT8
+SmmIoRead8 (
+ IN UINT16 Address
+ );
+
+VOID
+SmmIoWrite8 (
+ IN UINT16 Address,
+ IN UINT8 Data
+ );
+
+UINT16
+SmmIoRead16 (
+ IN UINT16 Address
+ );
+
+VOID
+SmmIoWrite16 (
+ IN UINT16 Address,
+ IN UINT16 Data
+ );
+
+UINT32
+SmmIoRead32 (
+ IN UINT16 Address
+ );
+
+VOID
+SmmIoWrite32 (
+ IN UINT16 Address,
+ IN UINT32 Data
+ );
+
+VOID
+SmmMemWrite8 (
+ IN UINT64 Dest,
+ IN UINT8 Data
+ );
+
+UINT8
+SmmMemRead8 (
+ IN UINT64 Dest
+ );
+
+VOID
+SmmMemWrite16 (
+ IN UINT64 Dest,
+ IN UINT16 Data
+ );
+
+UINT16
+SmmMemRead16 (
+ IN UINT64 Dest
+ );
+
+VOID
+SmmMemWrite32 (
+ IN UINT64 Dest,
+ IN UINT32 Data
+ );
+
+UINT32
+SmmMemRead32 (
+ IN UINT64 Dest
+ );
+
+VOID
+SmmMemAnd32 (
+ IN UINT64 Dest,
+ IN UINT32 Data
+ );
+//
+// Pci Configuration Space access functions definition
+//
+
+/**
+ Read value from the specified PCI config space register
+
+ @param[in] Width The width (8, 16 or 32 bits) of accessed pci config space register
+ @param[in] Address The address of the accessed pci register (bus, dev, func, offset)
+ @param[in, out] Buffer The returned value
+
+ @retval EFI_SUCCESS All operations successfully
+ @retval EFI_INVALID_PARAMETER Width is not valid or dosn't match register address
+ @retval Other error code If any error occured when calling libiary functions
+
+**/
+EFI_STATUS
+SmmPciCfgRead (
+ IN SMM_PCI_IO_WIDTH Width,
+ IN SMM_PCI_IO_ADDRESS *Address,
+ IN OUT VOID *Buffer
+ );
+
+/**
+ Write value into the specified PCI config space register
+
+ @param[in] Width The width (8, 16 or 32 bits) of accessed pci config space register
+ @param[in] Address The address of the accessed pci register (bus, dev, func, offset)
+ @param[in, out] Buffer The returned value
+
+ @retval EFI_SUCCESS All operations successfully
+ @retval EFI_INVALID_PARAMETER Width is not valid or dosn't match register address
+ @retval Other error code If any error occured when calling libiary functions
+
+**/
+EFI_STATUS
+SmmPciCfgWrite (
+ IN SMM_PCI_IO_WIDTH Width,
+ IN SMM_PCI_IO_ADDRESS *Address,
+ IN OUT VOID *Buffer
+ );
+
+#endif
diff --git a/BraswellPlatformPkg/Common/Include/Library/SpiFlash.h b/BraswellPlatformPkg/Common/Include/Library/SpiFlash.h new file mode 100644 index 0000000000..f50924196e --- /dev/null +++ b/BraswellPlatformPkg/Common/Include/Library/SpiFlash.h @@ -0,0 +1,241 @@ +/** @file
+
+ Copyright (c) 2004 - 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _SPIFlash_H_
+#define _SPIFlash_H_
+
+#include <Protocol/Spi.h>
+
+typedef enum {
+ EnumSpiFlashW25Q64,
+ EnumSpiFlashAT25DF321A,
+ EnumSpiFlashAT26DF321,
+ EnumSpiFlashAT25DF641,
+ EnumSpiFlashW25Q16,
+ EnumSpiFlashW25Q32,
+ EnumSpiFlashW25X32,
+ EnumSpiFlashW25X64,
+ EnumSpiFlashW25Q128,
+ EnumSpiFlashMX25L16,
+ EnumSpiFlashMX25L32,
+ EnumSpiFlashMX25L64,
+ EnumSpiFlashMX25L128,
+ EnumSpiFlashMX25U6435F,
+ EnumSpiFlashSST25VF016B,
+ EnumSpiFlashSST25VF064C,
+ EnumSpiFlashN25Q064,
+ EnumSpiFlashM25PX16,
+ EnumSpiFlashN25Q032,
+ EnumSpiFlashM25PX32,
+ EnumSpiFlashM25PX64,
+ EnumSpiFlashN25Q128,
+ EnumSpiFlashEN25Q16,
+ EnumSpiFlashEN25Q32,
+ EnumSpiFlashEN25Q64,
+ EnumSpiFlashEN25Q128,
+ EnumSpiFlashA25L016,
+ EnumSpiFlashMax
+} SPI_FLASH_TYPES_SUPPORTED;
+
+//
+// Serial Flash VendorId and DeviceId
+//
+#define SF_VENDOR_ID_ATMEL 0x1F
+#define SF_DEVICE_ID0_AT26DF321 0x47
+#define SF_DEVICE_ID1_AT26DF321 0x00
+#define SF_DEVICE_ID0_AT25DF321A 0x47
+#define SF_DEVICE_ID1_AT25DF321A 0x01
+#define SF_DEVICE_ID0_AT25DF641 0x48
+#define SF_DEVICE_ID1_AT25DF641 0x00
+
+#define SF_VENDOR_ID_WINBOND 0xEF
+#define SF_DEVICE_ID0_W25XXX 0x30
+#define SF_DEVICE_ID1_W25X32 0x16
+#define SF_DEVICE_ID1_W25X64 0x17
+#define SF_DEVICE_ID0_W25QXX 0x60
+#define SF_DEVICE_ID1_W25Q16 0x15
+#define SF_DEVICE_ID1_W25Q32 0x16
+#define SF_DEVICE_ID1_W25Q64 0x17
+#define SF_DEVICE_ID1_W25Q128 0x18
+
+#define SF_VENDOR_ID_MACRONIX 0xC2
+#define SF_DEVICE_ID0_MX25LXX 0x20
+#define SF_DEVICE_ID1_MX25L16 0x15
+#define SF_DEVICE_ID1_MX25L32 0x16
+#define SF_DEVICE_ID1_MX25L64 0x17
+#define SF_DEVICE_ID1_MX25L128 0x18
+#define SF_DEVICE_ID0_MX25UXX 0x25
+#define SF_DEVICE_ID1_MX25U6435F 0x37
+
+#define SF_VENDOR_ID_NUMONYX 0x20
+#define SF_DEVICE_ID0_N25Q064 0xBB
+#define SF_DEVICE_ID1_N25Q064 0x17
+#define SF_DEVICE_ID0_M25PXXX 0x71
+#define SF_DEVICE_ID0_N25QXXX 0xBA
+#define SF_DEVICE_ID1_M25PX16 0x15
+#define SF_DEVICE_ID1_N25Q032 0x16
+#define SF_DEVICE_ID1_M25PX32 0x16
+#define SF_DEVICE_ID1_M25PX64 0x17
+#define SF_DEVICE_ID1_N25Q128 0x18
+
+#define SF_VENDOR_ID_SST 0xBF
+#define SF_DEVICE_ID0_SST25VF0XXX 0x25
+#define SF_DEVICE_ID1_SST25VF016B 0x41
+#define SF_DEVICE_ID1_SST25VF064C 0x4B
+
+#define SF_VENDOR_ID_EON 0x1C
+#define SF_DEVICE_ID0_EN25QXX 0x30
+#define SF_DEVICE_ID1_EN25Q16 0x15
+#define SF_DEVICE_ID1_EN25Q32 0x16
+#define SF_DEVICE_ID1_EN25Q64 0x17
+#define SF_DEVICE_ID1_EN25Q128 0x18
+
+#define SF_VENDOR_ID_AMIC 0x37
+#define SF_DEVICE_ID0_A25L016 0x30
+#define SF_DEVICE_ID1_A25L016 0x15
+
+#define ATMEL_AT26DF321_SIZE 0x00400000
+#define ATMEL_AT25DF321A_SIZE 0x00400000
+#define ATMEL_AT25DF641_SIZE 0x00800000
+#define WINBOND_W25X32_SIZE 0x00400000
+#define WINBOND_W25X64_SIZE 0x00800000
+#define WINBOND_W25Q16_SIZE 0x00200000
+#define WINBOND_W25Q32_SIZE 0x00400000
+#define WINBOND_W25Q64_SIZE 0x00800000
+#define WINBOND_W25Q128_SIZE 0x01000000
+#define SST_SST25VF016B_SIZE 0x00200000
+#define SST_SST25VF064C_SIZE 0x00800000
+#define MACRONIX_MX25L16_SIZE 0x00200000
+#define MACRONIX_MX25L32_SIZE 0x00400000
+#define MACRONIX_MX25L64_SIZE 0x00800000
+#define MACRONIX_MX25U64_SIZE 0x00800000
+#define MACRONIX_MX25L128_SIZE 0x01000000
+#define NUMONYX_M25PX16_SIZE 0x00400000
+#define NUMONYX_N25Q032_SIZE 0x00400000
+#define NUMONYX_M25PX32_SIZE 0x00400000
+#define NUMONYX_M25PX64_SIZE 0x00800000
+#define NUMONYX_N25Q064_SIZE 0x00800000
+#define NUMONYX_N25Q128_SIZE 0x01000000
+#define EON_EN25Q16_SIZE 0x00200000
+#define EON_EN25Q32_SIZE 0x00400000
+#define EON_EN25Q64_SIZE 0x00800000
+#define EON_EN25Q128_SIZE 0x01000000
+#define AMIC_A25L16_SIZE 0x00200000
+
+#define SF_VENDOR_ID_SST 0xBF
+#define SF_DEVICE_ID0_25LF080A 0x25
+#define SF_DEVICE_ID1_25LF080A 0x8E
+#define SF_DEVICE_ID0_25VF016B 0x25
+#define SF_DEVICE_ID1_25VF016B 0x41
+
+#define SF_VENDOR_ID_ATMEL 0x1F
+#define SF_DEVICE_ID0_AT26DF321 0x47
+#define SF_DEVICE_ID1_AT26DF321 0x00
+
+#define SF_VENDOR_ID_STM 0x20
+#define SF_DEVICE_ID0_M25P32 0x20
+#define SF_DEVICE_ID1_M25P32 0x16
+
+#define SF_VENDOR_ID_WINBOND 0xEF
+#define SF_DEVICE_ID0_W25XXX 0x30
+
+#define SF_DEVICE_ID1_W25X80 0x14
+#define SF_DEVICE_ID1_W25X16 0x15
+#define SF_DEVICE_ID1_W25X32 0x16
+#define SF_DEVICE_ID1_W25X64 0x17
+
+#define SF_VENDOR_ID_MX 0xC2
+#define SF_DEVICE_ID0_25L1605A 0x20
+#define SF_DEVICE_ID1_25L1605A 0x15
+
+#define SF_VENDOR_ID_NUMONYX 0x20
+#define SF_DEVICE_ID0_M25PX16 0x71
+#define SF_DEVICE_ID1_M25PX16 0x15
+
+#define SST_25LF080A_SIZE 0x00100000
+#define SST_25LF016B_SIZE 0x00200000
+#define ATMEL_AT26DF321_SIZE 0x00400000
+#define STM_M25P32_SIZE 0x00400000
+#define WINBOND_W25X80_SIZE 0x00100000
+#define WINBOND_W25X16_SIZE 0x00200000
+#define WINBOND_W25X32_SIZE 0x00400000
+#define WINBOND_W25X64_SIZE 0x00800000
+#define MX_25L1605A_SIZE 0x00200000
+
+//
+// Physical Sector Size on the Serial Flash device
+//
+#define SF_SECTOR_SIZE 0x1000
+#define SF_BLOCK_SIZE 0x8000
+
+//
+// Serial Flash Status Register definitions
+//
+#define SF_SR_BUSY 0x01 // Indicates if internal write operation is in progress
+#define SF_SR_WEL 0x02 // Indicates if device is memory write enabled
+#define SF_SR_BP0 0x04 // Block protection bit 0
+#define SF_SR_BP1 0x08 // Block protection bit 1
+#define SF_SR_BP2 0x10 // Block protection bit 2
+#define SF_SR_BP3 0x20 // Block protection bit 3
+#define SF_SR_WPE 0x3C // Enable write protection on all blocks
+#define SF_SR_AAI 0x40 // Auto Address Increment Programming status
+#define SF_SR_BPL 0x80 // Block protection lock-down
+
+//
+// Operation Instruction definitions for the Serial Flash Device
+//
+#define SF_INST_WRSR 0x01 // Write Status Register
+#define SF_INST_PROG 0x02 // Byte Program
+#define SF_INST_READ 0x03 // Read
+#define SF_INST_WRDI 0x04 // Write Disable
+#define SF_INST_RDSR 0x05 // Read Status Register
+#define SF_INST_WREN 0x06 // Write Enable
+#define SF_INST_HS_READ 0x0B // High-speed Read
+#define SF_INST_SERASE 0x20 // Sector Erase (4KB)
+#define SF_INST_BERASE 0x52 // Block Erase (32KB)
+#define SF_INST_64KB_ERASE 0xD8 // Block Erase (64KB)
+#define SF_INST_EWSR 0x50 // Enable Write Status Register
+#define SF_INST_READ_ID 0xAB // Read ID
+#define SF_INST_JEDEC_READ_ID 0x9F // JEDEC Read ID
+#define SF_INST_DOFR 0x3B // Dual Output Fast Read
+#define SF_INST_SFDP 0x5A // Serial Flash Discovery Parameters
+
+#define SECTOR_SIZE_4KB 0x1000 // Common 4kBytes sector size
+#define SECTOR_SIZE_64KB 0x10000 // Common 64kBytes sector size
+#define BLOCK_SIZE_64KB 0x00010000 // Common 64kBytes block size
+#define MAX_FWH_SIZE 0x00100000 // 8Mbit (Note that this can also be used for the 4Mbit )
+
+//
+// Prefix Opcode Index on the host SPI controller
+//
+typedef enum {
+ SPI_WREN, // Prefix Opcode 0: Write Enable
+ SPI_EWSR, // Prefix Opcode 1: Enable Write Status Register
+} PREFIX_OPCODE_INDEX;
+
+//
+// Opcode Menu Index on the host SPI controller
+//
+typedef enum {
+ SPI_READ_ID, // Opcode 0: READ ID, Read cycle with address
+ SPI_READ, // Opcode 1: READ, Read cycle with address
+ SPI_RDSR, // Opcode 2: Read Status Register, No address
+ SPI_WRDI_SFDP, // Opcode 3: Write Disable or Discovery Parameters, No address
+ SPI_SERASE, // Opcode 4: Sector Erase (4KB), Write cycle with address
+ SPI_BERASE, // Opcode 5: Block Erase (32KB), Write cycle with address
+ SPI_PROG, // Opcode 6: Byte Program, Write cycle with address
+ SPI_WRSR, // Opcode 7: Write Status Register, No address
+} SPI_OPCODE_INDEX;
+
+#endif
diff --git a/BraswellPlatformPkg/Common/Include/Library/StallSmmLib.h b/BraswellPlatformPkg/Common/Include/Library/StallSmmLib.h new file mode 100644 index 0000000000..2772d418f7 --- /dev/null +++ b/BraswellPlatformPkg/Common/Include/Library/StallSmmLib.h @@ -0,0 +1,37 @@ +/** @file
+ This library provides SMM functions for Stall.
+ These can be used to save size and simplify code.
+ All contents must be runtime and SMM safe.
+
+ Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _SMM_STALL_LIB_H_
+#define _SMM_STALL_LIB_H_
+#include "PiDxe.h"
+#include "Pi/PiSmmCis.h"
+extern EFI_SMM_SYSTEM_TABLE2 *mSmst;
+
+/**
+ Delay for at least the request number of microseconds
+
+ @param[in] Microseconds Number of microseconds to delay.
+
+ @retval None
+
+**/
+VOID
+SmmStall (
+ IN UINTN Microseconds
+ );
+
+#endif
diff --git a/BraswellPlatformPkg/Common/Include/Library/UefiBootManagerLib.h b/BraswellPlatformPkg/Common/Include/Library/UefiBootManagerLib.h new file mode 100644 index 0000000000..ff34d6f344 --- /dev/null +++ b/BraswellPlatformPkg/Common/Include/Library/UefiBootManagerLib.h @@ -0,0 +1,798 @@ +/** @file
+ The Library for UEFIBootManager.
+
+ Copyright (c) 2011 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _UEFI_BOOT_MANAGER_LIB_H_
+#define _UEFI_BOOT_MANAGER_LIB_H_
+
+//
+// Boot Manager load option library functions.
+//
+
+//
+// Load Option Type
+//
+typedef enum {
+ LoadOptionTypeBoot,
+ LoadOptionTypeDriver,
+ LoadOptionTypeMax
+} EFI_BOOT_MANAGER_LOAD_OPTION_TYPE;
+
+typedef enum {
+ LoadOptionNumberMax = 0x10000,
+ LoadOptionNumberUnassigned = LoadOptionNumberMax
+} EFI_BOOT_MANAGER_LOAD_OPTION_NUMBER;
+
+//
+// Common structure definition for DriverOption and BootOption
+//
+typedef struct {
+ UINTN OptionNumber; // #### numerical value, could be LoadOptionNumberUnassigned
+ EFI_BOOT_MANAGER_LOAD_OPTION_TYPE OptionType; // LoadOptionTypeBoot or LoadOptionTypeDriver
+ UINT32 Attributes; // Load Option Attributes
+ CHAR16 *Description; // Load Option Description
+ EFI_DEVICE_PATH_PROTOCOL *FilePath; // Load Option Device Path
+ UINT8 *OptionalData; // Load Option optional data to pass into image
+ UINT32 OptionalDataSize; // Load Option size of OptionalData
+ BOOLEAN BootNext; // TRUE if this was a L"BootNext" Variable
+ EFI_STATUS Status; // Status returned from boot attempt gBS->StartImage ()
+ CHAR16 *ExitData; // Exit data returned from gBS->StartImage ()
+ UINTN ExitDataSize; // Size of ExitData
+} EFI_BOOT_MANAGER_LOAD_OPTION;
+
+/**
+ Returns an array of load options based on the EFI variable
+ L"BootOrder"/L"DriverOrder" and the L"Boot####"/L"Driver####" variables impled by it.
+ #### is the hex value of the UINT16 in each BootOrder/DriverOrder entry.
+
+ @param[out] LoadOptionCount Returns number of entries in the array.
+ @param[in] LoadOptionType The type of the load option.
+
+ @retval NULL No load options exist.
+ @retval !NULL Array of load option entries.
+
+**/
+EFI_BOOT_MANAGER_LOAD_OPTION *
+EFIAPI
+EfiBootManagerGetLoadOptions (
+ OUT UINTN *LoadOptionCount,
+ IN EFI_BOOT_MANAGER_LOAD_OPTION_TYPE LoadOptionType
+ );
+
+/**
+ Free an array of load options which return from
+ EfiBootManagerGetLoadOptions().
+
+ @param[in] LoadOptions Pointer to the array of load options to free.
+ @param[in] LoadOptionCount Number of array entries in LoadOptions.
+
+ @retval EFI_SUCCESS LoadOptions was freed.
+ @retval EFI_INVALID_PARAMETER LoadOptions is NULL.
+
+**/
+EFI_STATUS
+EFIAPI
+EfiBootManagerFreeLoadOptions (
+ IN EFI_BOOT_MANAGER_LOAD_OPTION *LoadOptions,
+ IN UINTN LoadOptionCount
+ );
+
+/**
+ Get the option number that wasn't used.
+
+ @param[in] OptionType Type of the load option.
+ @param[out] FreeOptionNumber Returns the minimal free option number.
+
+ @retval EFI_SUCCESS The option number is found.
+ @retval EFI_NOT_FOUND No free option number can be found.
+ It happens when every number between 0000 and FFFF is used.
+ @retval EFI_INVALID_PARAMETER FreeOptionNumber is NULL.
+
+**/
+EFI_STATUS
+EFIAPI
+EfiBootManagerGetFreeOptionNumber (
+ IN EFI_BOOT_MANAGER_LOAD_OPTION_TYPE OptionType,
+ OUT UINT16 *FreeOptionNumber
+ );
+
+/**
+ Initialize a load option.
+
+ @param[in, out] Option Pointer to the load option to be initialized.
+ @param[in] OptionNumber Option number of the load option.
+ @param[in] OptionType Type of the load option.
+ @param[in] Attributes Attributes of the load option.
+ @param[in] Description Description of the load option.
+ @param[in] FilePath Device path of the load option.
+ @param[in] OptionalData Optional data of the load option.
+ @param[in] OptionalDataSize Size of the optional data of the load option.
+
+ @retval EFI_SUCCESS The load option was initialized successfully.
+ @retval EFI_NOT_FOUND Cannot find a free option number to use.
+ @retval EFI_INVALID_PARAMETER Option, Description or FilePath is NULL.
+
+**/
+EFI_STATUS
+EFIAPI
+EfiBootManagerInitializeLoadOption (
+ IN OUT EFI_BOOT_MANAGER_LOAD_OPTION *Option,
+ IN UINTN OptionNumber,
+ IN EFI_BOOT_MANAGER_LOAD_OPTION_TYPE OptionType,
+ IN UINT32 Attributes,
+ IN CHAR16 *Description,
+ IN EFI_DEVICE_PATH_PROTOCOL *FilePath,
+ IN UINT8 *OptionalData,
+ IN UINT32 OptionalDataSize
+ );
+
+/**
+ Free a load option that was created by the library.
+
+ @param[in] LoadOption Pointer to the load option to free.
+ CONCERN: Check Boot#### instead of BootOrder,
+ optimize, spec clarify
+
+ @return EFI_SUCCESS LoadOption was freed.
+ @return EFI_INVALID_PARAMETER LoadOption is NULL.
+
+**/
+EFI_STATUS
+EFIAPI
+EfiBootManagerFreeLoadOption (
+ IN EFI_BOOT_MANAGER_LOAD_OPTION *LoadOption
+ );
+
+/**
+ Initialize the load option from the VariableName.
+
+ @param[in] VariableName EFI Variable name which could be Boot#### or
+ Driver####
+ @param[in, out] LoadOption Pointer to the load option to be initialized
+
+ @retval EFI_SUCCESS The option was created
+ @retval EFI_INVALID_PARAMETER VariableName or LoadOption is NULL.
+ @retval EFI_NOT_FOUND The variable specified by VariableName cannot be found.
+
+**/
+EFI_STATUS
+EFIAPI
+EfiBootManagerVariableToLoadOption (
+ IN CHAR16 *VariableName,
+ IN OUT EFI_BOOT_MANAGER_LOAD_OPTION *LoadOption
+ );
+
+/**
+ Create the Boot#### or Driver#### variable from the load option.
+
+ @param[in] LoadOption Pointer to the load option.
+
+ @retval EFI_SUCCESS The variable was created.
+ @retval Others Error status returned by RT->SetVariable.
+
+**/
+EFI_STATUS
+EFIAPI
+EfiBootManagerLoadOptionToVariable (
+ IN CONST EFI_BOOT_MANAGER_LOAD_OPTION *LoadOption
+ );
+
+/**
+ This function will update the Boot####/Driver#### and the BootOrder/DriverOrder
+ to add a new load option.
+
+ @param[in] Option Pointer to load option to add.
+ @param[in] Position Position of the new load option to put in the BootOrder/DriverOrder.
+
+ @retval EFI_SUCCESS The load option has been successfully added.
+ @retval Others Error status returned by RT->SetVariable.
+
+**/
+EFI_STATUS
+EFIAPI
+EfiBootManagerAddLoadOptionVariable (
+ IN EFI_BOOT_MANAGER_LOAD_OPTION *Option,
+ IN UINTN Position
+ );
+
+/**
+ Delete the load option according to the OptionNumber and OptionType.
+
+ Only the BootOrder/DriverOrder is updated to remove the reference of the OptionNumber.
+
+ @param[in] OptionNumber Option number of the load option.
+ @param[in] OptionType Type of the load option.
+
+ @retval EFI_NOT_FOUND The load option cannot be found.
+ @retval EFI_SUCCESS The load option was deleted.
+
+**/
+EFI_STATUS
+EFIAPI
+EfiBootManagerDeleteLoadOptionVariable (
+ IN UINTN OptionNumber,
+ IN EFI_BOOT_MANAGER_LOAD_OPTION_TYPE OptionType
+ );
+
+/**
+ The comparator to be used by EfiBootManagerSortLoadOption.
+
+ @param Left Point to the EFI_BOOT_MANAGER_LOAD_OPTION.
+ @param Right Point to the EFI_BOOT_MANAGER_LOAD_OPTION.
+
+ @retval TRUE Left load option should be in front of the Right load option.
+ @retval FALSE Right load option should be in front of the Left load option.
+
+**/
+typedef
+BOOLEAN
+(EFIAPI *EFI_BOOT_MANAGER_LOAD_OPTION_COMPARATOR) (
+ CONST EFI_BOOT_MANAGER_LOAD_OPTION *Left,
+ CONST EFI_BOOT_MANAGER_LOAD_OPTION *Right
+ );
+
+/**
+ Sort the load options. The DriverOrder/BootOrder variables will be re-created to
+ reflect the new order.
+
+ @param OptionType The type of the load option.
+ @param Comparator The comparator function pointer.
+
+**/
+VOID
+EFIAPI
+EfiBootManagerSortLoadOptionVariable (
+ EFI_BOOT_MANAGER_LOAD_OPTION_TYPE OptionType,
+ EFI_BOOT_MANAGER_LOAD_OPTION_COMPARATOR Comparator
+ );
+
+/**
+ Return the index of the load option in the load option array.
+
+ The function consider two load options are equal when the
+ OptionType, Attributes, Description, FilePath and OptionalData are equal.
+
+ @param[in] Key Pointer to the load option to be found.
+ @param[in] Array Pointer to the array of load options to be found.
+ @param[in] Count Number of entries in the Array.
+
+ @retval -1 Key wasn't found in the Array.
+ @retval 0 ~ Count-1 The index of the Key in the Array.
+
+**/
+INTN
+EFIAPI
+EfiBootManagerFindLoadOption (
+ IN CONST EFI_BOOT_MANAGER_LOAD_OPTION *Key,
+ IN CONST EFI_BOOT_MANAGER_LOAD_OPTION *Array,
+ IN UINTN Count
+ );
+
+//
+// Boot Manager hot key library functions.
+//
+
+#pragma pack(1)
+///
+/// EFI Key Option.
+///
+typedef struct {
+ ///
+ /// Specifies options about how the key will be processed.
+ ///
+ EFI_BOOT_KEY_DATA KeyData;
+ ///
+ /// The CRC-32 which should match the CRC-32 of the entire EFI_LOAD_OPTION to
+ /// which BootOption refers. If the CRC-32s do not match this value, then this key
+ /// option is ignored.
+ ///
+ UINT32 BootOptionCrc;
+ ///
+ /// The Boot#### option which will be invoked if this key is pressed and the boot option
+ /// is active (LOAD_OPTION_ACTIVE is set).
+ ///
+ UINT16 BootOption;
+ ///
+ /// The key codes to compare against those returned by the
+ /// EFI_SIMPLE_TEXT_INPUT and EFI_SIMPLE_TEXT_INPUT_EX protocols.
+ /// The number of key codes (0-3) is specified by the EFI_KEY_CODE_COUNT field in KeyOptions.
+ ///
+ EFI_INPUT_KEY Keys[3];
+ UINT16 OptionNumber;
+} EFI_BOOT_MANAGER_KEY_OPTION;
+#pragma pack()
+
+/**
+ Start the hot key service so that the key press can trigger the boot option.
+
+ @param[in] HotkeyTriggered Return the waitable event and it will be signaled
+ when a valid hot key is pressed.
+
+ @retval EFI_SUCCESS The hot key service is started.
+
+**/
+
+EFI_STATUS
+EFIAPI
+EfiBootManagerStartHotkeyService (
+ IN EFI_EVENT *HotkeyTriggered
+ );
+
+//
+// Modifier for EfiBootManagerAddKeyOptionVariable and EfiBootManagerDeleteKeyOptionVariable
+//
+#define EFI_BOOT_MANAGER_SHIFT_PRESSED 0x00000001
+#define EFI_BOOT_MANAGER_CONTROL_PRESSED 0x00000002
+#define EFI_BOOT_MANAGER_ALT_PRESSED 0x00000004
+#define EFI_BOOT_MANAGER_LOGO_PRESSED 0x00000008
+#define EFI_BOOT_MANAGER_MENU_KEY_PRESSED 0x00000010
+#define EFI_BOOT_MANAGER_SYS_REQ_PRESSED 0x00000020
+
+/**
+ Add the key option.
+ It adds the key option variable and the key option takes affect immediately.
+
+ @param[out] AddedOption Return the added key option.
+ @param[in] BootOptionNumber The boot option number for the key option.
+ @param[in] Modifier Key shift state.
+ @param ... Parameter list of pointer of EFI_INPUT_KEY.
+
+ @retval EFI_SUCCESS The key option is added.
+ @retval EFI_ALREADY_STARTED The hot key is already used by certain key option.
+
+**/
+EFI_STATUS
+EFIAPI
+EfiBootManagerAddKeyOptionVariable (
+ OUT EFI_BOOT_MANAGER_KEY_OPTION *AddedOption, OPTIONAL
+ IN UINT16 BootOptionNumber,
+ IN UINT32 Modifier,
+ ...
+ );
+
+/**
+ Delete the Key Option variable and unregister the hot key
+
+ @param[in] DeletedOption Return the deleted key options.
+ @param[in] Modifier Key shift state.
+ @param ... Parameter list of pointer of EFI_INPUT_KEY.
+
+ @retval EFI_SUCCESS The key option is deleted.
+ @retval EFI_NOT_FOUND The key option cannot be found.
+
+**/
+EFI_STATUS
+EFIAPI
+EfiBootManagerDeleteKeyOptionVariable (
+ IN EFI_BOOT_MANAGER_KEY_OPTION *DeletedOption, OPTIONAL
+ IN UINT32 Modifier,
+ ...
+ );
+
+/**
+ Return the array of key options.
+
+ @param[out] Count Return the number of key options.
+
+ @retval NULL No key option.
+ @retval Other Pointer to the key options.
+
+**/
+EFI_BOOT_MANAGER_KEY_OPTION *
+EFIAPI
+EfiBootManagerGetKeyOptions (
+ OUT UINTN *Count
+ );
+
+/**
+ Free the key options returned from EfiBootManagerGetKeyOptions.
+
+ @param[in] KeyOptions Pointer to the key options.
+ @param[in] KeyOptionCount Number of the key options.
+
+ @retval EFI_SUCCESS The key options are freed.
+ @retval EFI_NOT_FOUND KeyOptions is NULL.
+
+**/
+EFI_STATUS
+EFIAPI
+EfiBootManagerFreeKeyOptions (
+ IN EFI_BOOT_MANAGER_KEY_OPTION *KeyOptions,
+ IN UINTN KeyOptionCount
+ );
+
+/**
+ Register the key option to exit the waiting of the Boot Manager timeout.
+ Platform should ensure that the continue key option isn't conflict with
+ other boot key options.
+
+ @param[in] Modifier Key shift state.
+ @param ... Parameter list of pointer of EFI_INPUT_KEY.
+
+ @retval EFI_SUCCESS Successfully register the continue key option.
+ @retval EFI_ALREADY_STARTED The continue key option is already registered.
+
+**/
+EFI_STATUS
+EFIAPI
+EfiBootManagerRegisterContinueKeyOption (
+ IN UINT32 Modifier,
+ ...
+ );
+
+/**
+ Try to boot the boot option triggered by hot key.
+**/
+VOID
+EFIAPI
+EfiBootManagerHotkeyBoot (
+ VOID
+ );
+//
+// Boot Manager boot library functions.
+//
+
+/**
+ The function enumerates all boot options, creates them and registers them in the BootOrder variable.
+**/
+VOID
+EFIAPI
+EfiBootManagerRefreshAllBootOption (
+ VOID
+ );
+
+/**
+ Attempt to boot the EFI boot option. This routine sets L"BootCurent", clears L"BootNext",
+ and signals the EFI ready to boot event. If the device path for the option
+ starts with a BBS device path a legacy boot is attempted. Short form device paths are
+ also supported via this rountine. A device path starting with
+ MEDIA_HARDDRIVE_DP, MSG_USB_WWID_DP, MSG_USB_CLASS_DP gets expaned out
+ to find the first device that matches. If the BootOption Device Path
+ fails the removable media boot algorithm is attempted (\EFI\BOOTIA32.EFI,
+ \EFI\BOOTX64.EFI,... only one file type is tried per processor type)
+
+ @param[in] BootOption Boot Option to try and boot.
+ On return, BootOption->Status contains the boot status:
+ EFI_SUCCESS BootOption was booted
+ EFI_UNSUPPORTED BootOption isn't supported.
+ EFI_NOT_FOUND The BootOption was not found on the system
+ Others BootOption failed with this error status
+
+**/
+VOID
+EFIAPI
+EfiBootManagerBoot (
+ IN EFI_BOOT_MANAGER_LOAD_OPTION *BootOption
+ );
+
+VOID
+EfiBootManagerDefaultBootBehavior (
+ VOID
+ );
+
+/**
+ This function is called by platform to register a new boot option for the Boot Manager Menu.
+
+ The Boot Manager Menu is shown after successfully booting a boot option.
+
+ @param[in] FilePath Pointer to the Boot Manager Menu
+ @param[in] Description The optional description for the Boot Manager Menu
+ L"Boot Manager Menu" is used if the Description is NULL
+ @param[out] OptionNumber Return the boot option number of the Boot Manager Menu
+
+ @retval EFI_SUCCESS Successfully register the Boot Manager Menu.
+ @retval EFI_ALREADY_STARTED The Boot Manager Menu is already registered.
+
+**/
+EFI_STATUS
+EFIAPI
+EfiBootManagerRegisterBootManagerMenu (
+ IN EFI_DEVICE_PATH_PROTOCOL *FilePath,
+ IN CHAR16 *Description, OPTIONAL
+ OUT UINT16 *OptionNumber OPTIONAL
+ );
+
+/**
+ The function enumerates all the legacy boot options, creates them and registers them in the BootOrder variable.
+**/
+typedef
+VOID
+(EFIAPI *EFI_BOOT_MANAGER_REFRESH_LEGACY_BOOT_OPTION) (
+ VOID
+ );
+
+/**
+ The function boots a legacy boot option.
+**/
+typedef
+VOID
+(EFIAPI *EFI_BOOT_MANAGER_LEGACY_BOOT) (
+ IN EFI_BOOT_MANAGER_LOAD_OPTION *BootOption
+ );
+
+/**
+ The function registers the legacy boot support capabilities.
+
+ @param RefreshLegacyBootOption The function pointer to create all the legacy boot options.
+ @param LegacyBoot The function pointer to boot the legacy boot option.
+**/
+VOID
+EFIAPI
+EfiBootManagerRegisterLegacyBootSupport (
+ EFI_BOOT_MANAGER_REFRESH_LEGACY_BOOT_OPTION RefreshLegacyBootOption,
+ EFI_BOOT_MANAGER_LEGACY_BOOT LegacyBoot
+ );
+
+//
+// Boot Manager connect and disconnect library functions
+//
+
+/**
+ This function creates all handles associated with the given device
+ path node. If the handle associated with one device path node cannot
+ be created, then it tries to execute the dispatch to load the missing drivers.
+
+ @param[in] DevicePath The device path to be connected. Can be
+ a multi-instance device path.
+
+ @retval EFI_SUCCESS All handles associates with every device path node
+ were created.
+ @retval EFI_OUT_OF_RESOURCES Not enough resources to create new handles.
+ @retval EFI_NOT_FOUND The controller specified by the device path cannot be created.
+
+**/
+EFI_STATUS
+EFIAPI
+EfiBootManagerConnectDevicePath (
+ IN EFI_DEVICE_PATH_PROTOCOL *DevicePathToConnect,
+ OUT EFI_HANDLE *MatchingHandle OPTIONAL
+ );
+
+/**
+ This function will disconnect all current system handles.
+
+ gBS->DisconnectController() is invoked for each handle exists in system handle buffer.
+ If handle is a bus type handle, all childrens also are disconnected recursively by
+ gBS->DisconnectController().
+**/
+VOID
+EFIAPI
+EfiBootManagerDisconnectAll (
+ VOID
+ );
+
+/**
+ Connect the specific Usb device which match the short form device path.
+
+ @param[in] DevicePath A short-form device path that starts with the first
+ element being a USB WWID or a USB Class device
+ path
+
+ @return EFI_INVALID_PARAMETER DevicePath is NULL pointer.
+ DevicePath is not a USB device path.
+
+ @return EFI_SUCCESS Success to connect USB device
+ @return EFI_NOT_FOUND Fail to find handle for USB controller to connect.
+
+**/
+EFI_STATUS
+EFIAPI
+EfiBootManagerConnectUsbShortFormDevicePath (
+ IN EFI_DEVICE_PATH_PROTOCOL *DevicePath
+ );
+
+//
+// Boot Manager console library functions
+//
+
+typedef enum {
+ ConIn,
+ ConOut,
+ ErrOut,
+ ConInDev,
+ ConOutDev,
+ ErrOutDev,
+ ConsoleTypeMax
+} CONSOLE_TYPE;
+
+/**
+ This function will search every input/output device in current system,
+ and make every input/output device as potential console device.
+**/
+VOID
+EFIAPI
+EfiBootManagerConnectAllConsoles (
+ VOID
+ );
+
+/**
+ This function will connect all the console devices base on the console
+ device variable ConIn, ConOut and ErrOut.
+**/
+VOID
+EFIAPI
+EfiBootManagerConnectAllDefaultConsoles (
+ VOID
+ );
+
+/**
+ This function updates the console variable based on ConVarName. It can
+ add or remove one specific console device path from the variable
+
+ @param[in] ConsoleType ConIn, ConOut, ErrOut, ConInDev, ConOutDev or ErrOutDev.
+ @param[in] CustomizedConDevicePath The console device path to be added to
+ the console variable. Cannot be multi-instance.
+ @param[in] ExclusiveDevicePath The console device path to be removed
+ from the console variable. Cannot be multi-instance.
+
+ @retval EFI_UNSUPPORTED The added device path is the same as a removed one.
+ @retval EFI_SUCCESS Successfully added or removed the device path from the
+ console variable.
+
+**/
+EFI_STATUS
+EFIAPI
+EfiBootManagerUpdateConsoleVariable (
+ IN CONSOLE_TYPE ConsoleType,
+ IN EFI_DEVICE_PATH_PROTOCOL *CustomizedConDevicePath,
+ IN EFI_DEVICE_PATH_PROTOCOL *ExclusiveDevicePath
+ );
+
+/**
+ Connect the console device base on the variable ConVarName. If
+ ConVarName is a multi-instance device path, and at least one
+ instance connects successfully, then this function
+ will return success.
+
+ @param[in] ConVarName The console related variable name: ConIn, ConOut,
+ ErrOut.
+
+ @retval EFI_NOT_FOUND No console devices were connected successfully
+ @retval EFI_SUCCESS Connected at least one instance of the console
+ device path based on the variable ConVarName.
+
+**/
+EFI_STATUS
+EFIAPI
+EfiBootManagerConnectConsoleVariable (
+ IN CONSOLE_TYPE ConsoleType
+ );
+
+//
+// Boot Manager device path library functions
+//
+/**
+ Delete the instance in Multi that overlaps with Single.
+
+ @param[in] Multi A pointer to a multi-instance device path data
+ structure.
+ @param[in] Single A pointer to a single-instance device path data
+ structure.
+
+ @return This function removes the device path instances in Multi that overlap
+ Single, and returns the resulting device path. If there is no
+ remaining device path as a result, this function will return NULL.
+
+**/
+EFI_DEVICE_PATH_PROTOCOL *
+EFIAPI
+EfiBootManagerDelPartMatchInstance (
+ IN EFI_DEVICE_PATH_PROTOCOL *Multi,
+ IN EFI_DEVICE_PATH_PROTOCOL *Single
+ );
+
+/**
+ This function compares a device path data structure to that of all the nodes of a
+ second device path instance.
+
+ @param[in] Multi A pointer to a multi-instance device path data
+ structure.
+ @param[in] Single A pointer to a single-instance device path data
+ structure.
+
+ @retval TRUE If the Single device path is contained within a
+ Multi device path.
+ @retval FALSE The Single device path is not contained within a
+ Multi device path.
+
+**/
+BOOLEAN
+EFIAPI
+EfiBootManagerMatchDevicePaths (
+ IN EFI_DEVICE_PATH_PROTOCOL *Multi,
+ IN EFI_DEVICE_PATH_PROTOCOL *Single
+ );
+
+/**
+ The function expands a short-form device path to a full device path.
+
+ It supports to expand the short-form hard drive media device path and
+ the short-form USB WWID or USB Class device path.
+
+ @param[in] DevicePath The short-form device path to expand.
+
+ @retval FullDevicePath The full device path after expanding.
+ @retval NULL There is no corresponding full device path.
+ @retval DevicePath The device path is not a short-form device path.
+ Caller can compare the returning pointer value directly
+ against the input DevicePath to determin whether the
+ DevicePath is a short-form device path.
+
+**/
+EFI_DEVICE_PATH_PROTOCOL *
+EFIAPI
+EfiBootManagerExpandShortFormDevicePath (
+ IN EFI_DEVICE_PATH_PROTOCOL *DevicePath
+ );
+
+/**
+ Checks whether the Device path points to a bootable device, and if the device
+ is ready to boot now.
+
+ @param[in] DevicePath The device path to be checked.
+ @param[in] CheckMedia If TRUE, check whether the device is ready to boot now.
+
+ @retval TRUE The device path is bootable.
+ @retval FALSE The device path is not bootable.
+
+**/
+BOOLEAN
+EFIAPI
+EfiBootManagerIsBootableDevicePath (
+ IN EFI_DEVICE_PATH_PROTOCOL *DevicePath,
+ IN BOOLEAN CheckMedia
+ );
+
+//
+// Boot Manager misc library functions.
+//
+
+/**
+ The function will go through the driver option array, and then load and start
+ every driver to which the driver option device path points.
+
+ @param[in] DriverOption Pointer to driver option array to load.
+ @param[in] DriverOptionCount Number of array entries in DriverOption
+
+**/
+VOID
+EFIAPI
+EfiBootManagerLoadDrivers (
+ IN EFI_BOOT_MANAGER_LOAD_OPTION *DriverOption,
+ IN UINTN DriverOptionCount
+ );
+
+/**
+ This function reads the EFI variable (VendorGuid/Name) and returns a dynamically allocated
+ buffer and the size of the buffer. If it fails, return NULL.
+
+ @param[in] Name The string part of the EFI variable name.
+ @param[in] VendorGuid The GUID part of the EFI variable name.
+ @param[out] VariableSize Returns the size of the EFI variable that was read.
+
+ @retval !NULL Dynamically allocated memory that contains a copy
+ of the EFI variable. The caller is responsible to
+ free the buffer.
+ @retval NULL The variable was not found.
+
+**/
+VOID *
+EFIAPI
+EfiBootManagerGetVariableAndSize (
+ IN CHAR16 *Name,
+ IN EFI_GUID *VendorGuid,
+ OUT UINTN *VariableSize
+ );
+
+#endif
diff --git a/BraswellPlatformPkg/Common/Include/Manifest.h b/BraswellPlatformPkg/Common/Include/Manifest.h new file mode 100644 index 0000000000..24721f9d3d --- /dev/null +++ b/BraswellPlatformPkg/Common/Include/Manifest.h @@ -0,0 +1,41 @@ +/** @file
+ Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _MANIFEST_H_
+#define _MANIFEST_H_
+
+#define MAX_DIGEST_SIZE 64
+#define SHA256_TOTAL_BYTE 32
+#define MANIFEST_ADDRESS 0xFFFE0058
+
+typedef struct _MANIFEST_OEM_DATA {
+ UINT32 Signature;
+ UINT8 SystemFirmwareGuid[16];
+ UINT32 BIOSVersion;
+ UINT32 BIOSCompatibleVersion;
+ UINT8 Bios2ndStageHashLen;
+ UINT8 Sha256Hash[32];
+ UINT8 Reserved1[7];
+ UINT8 OSPubKeyHash[32];
+ UINT8 OSBLPubKeyHash[32];
+ UINT8 Reserved2[32];
+ UINT8 RecoveryFVHashLen;
+ UINT8 RecoveryFVHash[32];
+ UINT8 Reserved[32];
+ UINT32 IFWIVersionLen;
+ UINT8 IFWIVersion[32];
+ UINT8 Reserved3[131];
+} MANIFEST_OEM_DATA;
+
+#endif
+
diff --git a/BraswellPlatformPkg/Common/Include/Mcfg.h b/BraswellPlatformPkg/Common/Include/Mcfg.h new file mode 100644 index 0000000000..f37b7fd981 --- /dev/null +++ b/BraswellPlatformPkg/Common/Include/Mcfg.h @@ -0,0 +1,65 @@ +/** @file
+ ACPI Memory mapped configuration space base address Description Table
+ implementation, based on PCI Firmware Specification Revision 3.0 final draft,
+ downloadable at http://www.pcisig.com/home
+
+ Copyright (c) 2004 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _MCFG_H_
+#define _MCFG_H_
+
+//
+// Statements that include other files
+//
+#include <IndustryStandard/Acpi20.h>
+#include "McfgTable.h"
+#include "Platform.h"
+
+//
+// "MCFG" Static Resource Affinity Table
+//
+#define EFI_ACPI_3_0_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE_SIGNATURE 0x4746434D
+
+//
+// MCFG Definitions, see specification for details.
+//
+#define EFI_ACPI_OEM_MCFG_REVISION 0x00000001
+
+//
+// Define the number of each table type.
+// This is where the table layout is modified.
+//
+#define EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_BASE_ADDRESS_STRUCTURE_COUNT 1
+
+//
+// MCFG Table definition. The table must be defined in a platform
+// specific manner.
+//
+//
+// Ensure proper structure formats
+//
+#pragma pack(1)
+
+typedef struct {
+ EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE_HEADER Header;
+
+#if EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_BASE_ADDRESS_STRUCTURE_COUNT > 0
+ EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_BASE_ADDRESS_STRUCTURE Segment[
+ EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_BASE_ADDRESS_STRUCTURE_COUNT];
+#endif
+
+} EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE;
+
+#pragma pack()
+
+#endif // _MCFG_H_
diff --git a/BraswellPlatformPkg/Common/Include/McfgTable.h b/BraswellPlatformPkg/Common/Include/McfgTable.h new file mode 100644 index 0000000000..1c0062aa74 --- /dev/null +++ b/BraswellPlatformPkg/Common/Include/McfgTable.h @@ -0,0 +1,62 @@ +/** @file
+ ACPI Memory mapped configuration space base address Description Table
+ definition, based on PCI Firmware Specification Revision 3.0 final draft,
+ downloadable at http://www.pcisig.com/home
+
+ Copyright (c) 2004 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _MCFG_TABLE_H_
+#define _MCFG_TABLE_H_
+
+//
+// Include files
+//
+#include <PiDxe.h>
+
+//
+// Ensure proper structure formats
+//
+#pragma pack(1)
+
+//
+// MCFG Revision (defined in spec)
+//
+#define EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE_REVISION 0x01
+
+//
+// MCFG Structure Definitions
+//
+//
+// Memory Mapped Enhanced Configuration Base Address Allocation
+// Structure Definition
+//
+typedef struct {
+ UINT64 BaseAddress;
+ UINT16 PciSegmentGroupNumber;
+ UINT8 StartBusNumber;
+ UINT8 EndBusNumber;
+ UINT32 Reserved;
+} EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_BASE_ADDRESS_STRUCTURE;
+
+//
+// MCFG Table header definition. The rest of the table
+// must be defined in a platform specific manner.
+//
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT64 Reserved;
+} EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE_HEADER;
+
+#pragma pack()
+
+#endif // _MCFG_TABLE_H
diff --git a/BraswellPlatformPkg/Common/Include/PeiKscLib.h b/BraswellPlatformPkg/Common/Include/PeiKscLib.h new file mode 100644 index 0000000000..e71bcb57b5 --- /dev/null +++ b/BraswellPlatformPkg/Common/Include/PeiKscLib.h @@ -0,0 +1,230 @@ +/** @file
+ KSC library functions and definitions.
+
+ This library provides basic KSC interface.
+ It is deemed simple enough and uses in very few cases that those are not
+ currently benefit to implement a protocol. If more consumers are added,
+ it may be beneficial to implement as a protocol.
+
+ There may be different libraries for different environments (PEI, BS, RT, SMM).
+ Make sure you meet the requirements for the library (protocol dependencies, use
+ restrictions, etc).
+
+ Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _PEI_KSC_LIB_H_
+#define _PEI_KSC_LIB_H_
+
+//
+// Timeout if KSC command/data fails
+//
+#define KSC_TIME_OUT 0x20000
+
+//
+// The Keyboard and System management Controller (KSC) implements a standard 8042 keyboard
+// controller interface at ports 0x60/0x64 and a ACPI compliant system management controller
+// at ports 0x62/0x66. Port 0x66 is the command and status port, port 0x62 is the data port.
+//
+#define KSC_D_PORT 0x62
+#define KSC_C_PORT 0x66
+
+//
+// Status Port 0x62
+//
+#define KSC_S_OVR_TMP 0x80 // Current CPU temperature exceeds the threshold
+#define KSC_S_SMI_EVT 0x40 // SMI event is pending
+#define KSC_S_SCI_EVT 0x20 // SCI event is pending
+#define KSC_S_BURST 0x10 // KSC is in burst mode or normal mode
+#define KSC_S_CMD 0x08 // Byte in data register is command/data
+#define KSC_S_IGN 0x04 // Ignored
+#define KSC_S_IBF 0x02 // Input buffer is full/empty
+#define KSC_S_OBF 0x01 // Output buffer is full/empty
+
+//
+// KSC commands that are issued to the KSC through the command port (0x66).
+// New commands and command parameters should only be written by the host when IBF=0.
+// Data read from the KSC data port is valid only when OBF=1.
+//
+#define KSC_C_SMI_NOTIFY_ENABLE 0x04 // Enable SMI notifications to the host
+#define KSC_C_SMI_NOTIFY_DISABLE 0x05 // SMI notifications are disabled and pending notifications cleared
+#define KSC_C_QUERY_SYS_STATUS 0x06 // Returns 1 byte of information about the system status
+#define KSC_B_SYS_STATUS_FAN 0x40 // Fan status (1 = ON)
+#define KSC_B_SYS_STATUS_DOCK 0x20 // Dock status (1 = Docked)
+#define KSC_B_SYS_STATUS_AC 0x10 // AC power (1 = AC powered)
+#define KSC_B_SYS_STATUS_THERMAL 0x0F // CPU thermal state (0 ~ 9)
+#define KSC_C_QUERY_BOARD_ID_BIT 0x0A // Board Id 8 or 16 bit
+#define KSC_B_BOARD_ID_BIT_16 0x80 // Bit7 =1 means 16 bit implementation
+#define KSC_C_SMC_GET_MODE 0x09 // Command to detect EC
+#define KSC_C_FAB_ID 0x0D // Get the board fab ID in the lower 3 bits
+#define KSC_B_BOARD_ID 0x0F // Board ID = [3:0]
+#define KSC_C_SYSTEM_POWER_OFF 0x22 // Turn off the system power
+#define KSC_C_NIC_PRESENCE 0X27 // WLAN NIC Card presence Information
+#define KSC_C_LAN_ON 0x46 // Turn on the power to LAN through EC/KSC
+#define KSC_C_LAN_OFF 0x47 // Turn off the power to LAN through EC/KSC
+#define KSC_C_GET_DTEMP 0x50 // Returns the CPU temperature as read from the SMBus thermal sensor.
+#define KSC_C_SET_CTEMP 0x58 // The next byte written to the data port will be the shutdown temperature
+#define KSC_C_EN_DTEMP 0x5E // Commands KSC to begin reading Thermal Diode and comparing to Critical Temperature
+#define KSC_C_DIS_DTEMP 0x5F // Commands KSC to stop reading Thermal Diode
+#define KSC_C_SMI_QUERY 0x70 // The host reads the data port to retrieve the notifications
+#define KSC_C_SMI_TIMER 0x71 // Commands the KSC to generate a periodic SMI to the host
+#define KSC_C_SMI_HOTKEY 0x72 // Get the scan code of hotkey pressed (CTRL + ALT + SHIFT + key)
+#define KSC_C_GETWAKE_STATUS 0x76 // Get wake Event status command
+#define KSC_C_CLEARWAKE_STATUS 0x77 // Clear wake Event status command
+#define KSC_C_READ_MEM 0x80 // Read the KSC memory
+#define KSC_C_WRITE_MEM 0x81 // Write the KSC memory
+#define KSC_C_KSC_REVISION 0x90 // Get the revision for the KSC
+#define KSC_C_SMI_INJECT 0xBA // The next byte written to the data port will generate an immediate SMI
+#define KSC_C_SMI_DISABLE 0xBC // SMI generation by the KSC is disabled
+#define KSC_C_SMI_ENABLE 0xBD // SMI generation by the KSC is enabled
+#define KSC_C_ACPI_ENABLE 0xAA // Enable ACPI mode
+#define KSC_C_ACPI_DISABLE 0xAB // Disable ACPI mode
+
+//
+// SMI notification code table, read through command KSC_C_SMI_QUERY
+//
+#define KSC_N_SMI_NULL 0x00 // Null marks the end of the SMI notification queue
+#define KSC_N_SMI_HOTKEY 0x20 // Hotkey pressed SMI
+#define KSC_N_SMI_ACINSERTION 0x30 // AC insertion SMI
+#define KSC_N_SMI_ACREMOVAL 0x31 // AC removal SMI
+#define KSC_N_SMI_PWRSW 0x32 // Power switch press SMI
+#define KSC_N_SMI_LID 0x33 // Lid switch change SMI
+#define KSC_N_SMI_VB 0x34 // Virtual battery switch change SMI
+#define KSC_N_SMI_THERM_0 0x60 // Thermal state 0 SMI
+#define KSC_N_SMI_THERM_1 0x61 // Thermal state 1 SMI
+#define KSC_N_SMI_THERM_2 0x62 // Thermal state 2 SMI
+#define KSC_N_SMI_THERM_3 0x63 // Thermal state 3 SMI
+#define KSC_N_SMI_THERM_4 0x64 // Thermal state 4 SMI
+#define KSC_N_SMI_THERM_5 0x65 // Thermal state 5 SMI
+#define KSC_N_SMI_THERM_6 0x66 // Thermal state 6 SMI
+#define KSC_N_SMI_THERM_7 0x67 // Thermal state 7 SMI
+#define KSC_N_SMI_THERM_8 0x68 // Thermal state 8 SMI
+#define KSC_N_SMI_DOCKED 0x70 // Dock complete SMI
+#define KSC_N_SMI_UNDOCKED 0x71 // Undock complete SMI
+#define KSC_N_SMI_UNDOCKREQUEST 0x72 // Undocking request SMI
+#define KSC_N_SMI_TIMER 0x80 // Timer wakeup SMI
+
+//
+// Hotkey scan code (CTRL + ALT + SHIFT + key)
+//
+#define KSC_HK_ESC 0x01 // ESC
+#define KSC_HK_1 0x02 // 1 !
+#define KSC_HK_2 0x03 // 2 @
+#define KSC_HK_3 0x04 // 3 #
+#define KSC_HK_4 0x05 // 4 $
+#define KSC_HK_5 0x06 // 5 %
+#define KSC_HK_6 0x07 // 6 ^
+#define KSC_HK_7 0x08 // 7 &
+#define KSC_HK_8 0x09 // 8 *
+#define KSC_HK_9 0x0A // 9 (
+#define KSC_HK_0 0x0B // 0 )
+#define KSC_HK_MINUS 0x0C // - _
+#define KSC_HK_ADD 0x0D // = +
+#define KSC_HK_F1 0x3B // F1
+#define KSC_HK_F2 0x3C // F2
+#define KSC_HK_F3 0x3D // F3
+#define KSC_HK_F4 0x3E // F4
+#define KSC_HK_F5 0x3F // F5
+#define KSC_HK_F6 0x40 // F6
+#define KSC_HK_F7 0x41 // F7
+#define KSC_HK_F8 0x42 // F8
+#define KSC_HK_F9 0x43 // F9
+#define KSC_HK_F10 0x44 // F10
+#define KSC_HK_F11 0x57 // F11
+#define KSC_HK_F12 0x58 // F12
+
+#include <Ppi/CpuIo.h>
+#include <Ppi/Stall.h>
+
+//
+// Function declarations
+//
+
+/**
+Routine Description:
+
+ The PEI function requires CPU IO protocol, through which it reads KSC Command port
+ and ensures that EC exists or not.
+
+Arguments:
+
+ --
+
+Returns:
+
+ EFI_SUCCESS - KscLib is successfully initialized.
+ EFI_DEVICE_ERROR - EC is NOT present on the system.
+
+**/
+EFI_STATUS
+InitializeKscLib ( );
+
+/**
+ Sends command to Keyboard System Controller.
+
+ @param[in] Command Command byte to send
+
+ @retval EFI_SUCCESS Command success
+ @retval EFI_DEVICE_ERROR Command error
+ @retval EFI_TIMEOUT Command timeout
+
+**/
+EFI_STATUS
+SendKscCommand (
+ IN UINT8 Command
+ );
+
+/**
+ Sends data to Keyboard System Controller.
+
+ @param[in] Data Data byte to send
+
+ @retval EFI_SUCCESS Success
+ @retval EFI_DEVICE_ERROR Error
+ @retval EFI_TIMEOUT Command timeout
+
+**/
+EFI_STATUS
+SendKscData (
+ IN UINT8 Data
+ );
+
+/**
+ Receives data from Keyboard System Controller.
+
+ @param[out] Data Data byte received
+
+ @retval EFI_SUCCESS Read success
+ @retval EFI_DEVICE_ERROR Read error
+ @retval EFI_TIMEOUT Command timeout
+
+**/
+EFI_STATUS
+ReceiveKscData (
+ OUT UINT8 *Data
+ );
+
+/**
+ Receives status from Keyboard System Controller.
+
+ @param[out] KscStatus Status byte to receive
+
+ @retval EFI_DEVICE_ERROR Ksc library has not initialized yet or KSC not present
+ @retval EFI_SUCCESS Get KSC status successfully
+
+**/
+EFI_STATUS
+ReceiveKscStatus (
+ OUT UINT8 *KscStatus
+ );
+
+#endif
diff --git a/BraswellPlatformPkg/Common/Include/Platform.h b/BraswellPlatformPkg/Common/Include/Platform.h new file mode 100644 index 0000000000..b82f9c97c8 --- /dev/null +++ b/BraswellPlatformPkg/Common/Include/Platform.h @@ -0,0 +1,129 @@ +/** @file
+ Pinetrail platform specific information.
+
+ Copyright (c) 2004 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _PLATFORM_H
+#define _PLATFORM_H
+
+#include "ChipsetAccess.h"
+#include "BuildVariables.h"
+#include "PlatformBaseAddresses.h"
+
+//
+// Number of P & T states supported.
+//
+#define NPTM_P_STATES_SUPPORTED 16
+#define NPTM_T_STATES_SUPPORTED 8
+
+//
+// I/O APIC IDs, the code uses math to generate the numbers
+// instead of using these defines.
+//
+#define ICH_IOAPIC (1 << 0)
+#define ICH_IOAPIC_ID 0x08
+
+//
+// Possible SMBus addresses that will be present.
+//
+#define SMBUS_ADDR_CH_A_1 0xA0
+#define SMBUS_ADDR_CH_A_2 0xA2
+#define SMBUS_ADDR_CH_B_1 0xA4
+#define SMBUS_ADDR_CH_B_2 0xA6
+#define SMBUS_ADDR_CH_C_1 0xA8
+#define SMBUS_ADDR_CH_C_2 0xAA
+#define SMBUS_ADDR_CH_D_1 0xAC
+#define SMBUS_ADDR_CH_D_2 0xAE
+#define SMBUS_ADDR_HOST_CLK_BUFFER 0xDC
+#define SMBUS_ADDR_ICH_SLAVE 0x44
+#define SMBUS_ADDR_HECETA 0x5C
+#define SMBUS_ADDR_SMBARP 0xC2
+#define SMBUS_ADDR_82573E 0xC6
+#define SMBUS_ADDR_CLKCHIP 0xD2
+#define SMBUS_ADDR_BRD_REV 0x4E
+#define SMBUS_ADDR_DB803 0x82
+
+//
+// SMBus addresses that used on this platform.
+//
+#define PLATFORM_SMBUS_RSVD_ADDRESSES { \
+ SMBUS_ADDR_CH_A_1, \
+ SMBUS_ADDR_CH_A_2, \
+ SMBUS_ADDR_HOST_CLK_BUFFER, \
+ SMBUS_ADDR_ICH_SLAVE, \
+ SMBUS_ADDR_SMBARP, \
+ SMBUS_ADDR_CLKCHIP, \
+ SMBUS_ADDR_BRD_REV, \
+ SMBUS_ADDR_DB803 \
+ }
+
+//
+// Count of addresses present in PLATFORM_SMBUS_RSVD_ADDRESSES.
+//
+#define PLATFORM_NUM_SMBUS_RSVD_ADDRESSES 8
+
+//
+// CMOS usage
+//
+#define CMOS_CPU_BSP_SELECT 0x10
+#define CMOS_CPU_UP_MODE 0x11
+#define CMOS_CPU_RATIO_OFFSET 0x12
+#define CMOS_CPU_CORE_HT_OFFSET 0x13
+#define CMOS_EFI_DEBUG 0x14
+#define CMOS_CPU_BIST_OFFSET 0x15
+#define CMOS_CPU_VMX_OFFSET 0x16
+#define CMOS_ICH_PORT80_OFFSET 0x17
+#define CMOS_PLATFORM_DESIGNATOR 0x18 // Second bank CMOS location of Platform ID
+#define CMOS_VALIDATION_TEST_BYTE 0x19 // BIT0 - Validation mailbox for UPonDP
+#define CMOS_SERIAL_BAUD_RATE 0x1A // 0=115200; 1=57600; 2=38400; 3=19200; 4=9600
+#define CMOS_DCU_MODE_OFFSET 0x1B
+#define CMOS_VR11_SET_OFFSET 0x1C
+#define CMOS_SBSP_TO_AP_COMM 0x20 // SEC code use ONLY!!!
+#define TCG_CMOS_AREA_OFFSET 0x60 // Also Change in Universal\Security\Tpm\PhysicalPresence\Dxe\PhysicalPresence.c &
+ // Also Change in Platform\IntelEpg\Thurley\Dxe\AcpiTables\Dsdt\Tpm.asi
+#define TCG_CMOS_MOR_AREA_OFFSET (TCG_CMOS_AREA_OFFSET + 0x05) // Also Change in Platform\IntelEpg\Thurley\Dxe\AcpiTables\Dsdt\Tpm.asi
+
+//
+// GPIO Index Data Structure
+//
+typedef struct {
+ UINT8 Register;
+ UINT32 Value;
+} ICH_GPIO_DEV;
+
+//
+// CPU Equates
+//
+#define MAX_THREAD 2
+#define MAX_CORE 1
+#define MAX_DIE 2
+#define MAX_CPU_SOCKET 1
+#define MAX_CPU_NUM (MAX_THREAD * MAX_CORE * MAX_DIE * MAX_CPU_SOCKET)
+
+#define MEM64_LEN 0x00100000000
+#define RES_MEM64_36_BASE 0x01000000000 - MEM64_LEN // 2^36
+#define RES_MEM64_36_LIMIT 0x01000000000 - 1 // 2^36
+#define RES_MEM64_39_BASE 0x08000000000 - MEM64_LEN // 2^39
+#define RES_MEM64_39_LIMIT 0x08000000000 - 1 // 2^39
+#define RES_MEM64_40_BASE 0x10000000000 - MEM64_LEN // 2^40
+#define RES_MEM64_40_LIMIT 0x10000000000 - 1 // 2^40
+
+//
+//LT Equates
+//
+#ifdef LT_FLAG
+ #define ACM_BASE AUTHENTICATED_CODE_BASE_ADDR
+ #define ACM_SIZE UTHENTICATED_CODE_SIZE
+#endif
+
+#endif
diff --git a/BraswellPlatformPkg/Common/Include/PlatformDefinitions.h b/BraswellPlatformPkg/Common/Include/PlatformDefinitions.h new file mode 100644 index 0000000000..779b9397a7 --- /dev/null +++ b/BraswellPlatformPkg/Common/Include/PlatformDefinitions.h @@ -0,0 +1,42 @@ +/** @file
+ This header file provides platform specific definitions used by other modules
+ for platform specific initialization.
+
+ THIS FILE SHOULD ONLY CONTAIN #defines BECAUSE IT IS CONSUMED BY NON-C MODULES
+ (ASL and VFR)
+
+ This file should not contain addition or other operations that an ASL compiler or
+ VFR compiler does not understand.
+
+ Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _PLATFORM_DEFINITIONS_H_
+#define _PLATFORM_DEFINITIONS_H_
+
+#include "PlatformBaseAddresses.h"
+
+//
+// Platform Base Address definitions
+//
+#ifndef PCIEX_BASE_ADDRESS
+#define PCIEX_BASE_ADDRESS EDKII_GLUE_PciExpressBaseAddress // Pci Express Configuration Space Base Address
+#endif
+
+#define PCIEX_LENGTH PLATFORM_PCIEXPRESS_LENGTH
+
+#define THERMAL_BASE_ADDRESS 0xFED08000
+
+#ifndef MCH_BASE_ADDRESS
+#define MCH_BASE_ADDRESS 0xFED10000 // MCH Register Base Address
+#endif
+#endif
diff --git a/BraswellPlatformPkg/Common/Include/PlatformGpioTable.h b/BraswellPlatformPkg/Common/Include/PlatformGpioTable.h new file mode 100644 index 0000000000..59add399a8 --- /dev/null +++ b/BraswellPlatformPkg/Common/Include/PlatformGpioTable.h @@ -0,0 +1,43 @@ +/** @file
+ This file provides the definitions of GPIO Table structure
+
+Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#ifndef _PLATFORM_GPIO_TABLE_H_
+#define _PLATFORM_GPIO_TABLE_H_
+
+#include "GpioAttributes.h"
+
+typedef struct {
+ UINT8 Usage;
+ UINT8 FuncNum;
+ UINT8 InitLevel;
+ UINT8 TrigType;
+ UINT8 DriveType;
+ UINT8 PullDirection;
+ UINT8 PullStrength;
+ UINT8 IntType;
+ UINT8 ShareMode;
+ UINT8 DirectIrqNum;
+ UINT8 IntLineNum;
+ UINT8 LightModeBar;
+ UINT8 GlitchFilterConfig;
+ UINT8 InvertRxTx;
+ BOOLEAN ReservedPin;
+}PLATFORM_GPIO_TABLE_ROW;
+
+#define GPIO_TABLE_NORTH_ROW_NUM 59
+#define GPIO_TABLE_EAST_ROW_NUM 24
+#define GPIO_TABLE_SOUTHEAST_ROW_NUM 55
+#define GPIO_TABLE_SOUTHWEST_ROW_NUM 56
+#define GPIO_TABLE_ROW_NUM 194
+
+#endif
diff --git a/BraswellPlatformPkg/Common/Include/Ppi/BoardDetection.h b/BraswellPlatformPkg/Common/Include/Ppi/BoardDetection.h new file mode 100644 index 0000000000..f1b4ab6d71 --- /dev/null +++ b/BraswellPlatformPkg/Common/Include/Ppi/BoardDetection.h @@ -0,0 +1,22 @@ +/** @file
+ The definition of Board detected.
+
+ Copyright (c) 2004 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _PEI_BOARD_DETECTION_H_
+#define _PEI_BOARD_DETECTION_H_
+
+extern EFI_GUID gBoardDetectionStartPpiGuid;
+extern EFI_GUID gBoardDetectedPpiGuid;
+
+#endif
diff --git a/BraswellPlatformPkg/Common/Include/Protocol/LpcWpce791Policy.h b/BraswellPlatformPkg/Common/Include/Protocol/LpcWpce791Policy.h new file mode 100644 index 0000000000..fe9b4ee8c9 --- /dev/null +++ b/BraswellPlatformPkg/Common/Include/Protocol/LpcWpce791Policy.h @@ -0,0 +1,48 @@ +/** @file
+ Protocol used for WPCE791 Policy definition.
+
+ Copyright (c) 2004 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+**/
+
+#ifndef _WPCE791_POLICY_PROTOCOL_H_
+#define _WPCE791_POLICY_PROTOCOL_H_
+
+#define EFI_WPCE791_POLICY_PROTOCOL_GUID \
+ { \
+ 0xab2bee2f, 0xc1a6, 0x4399, 0x85, 0x3d, 0xc0, 0x7c, 0x77, 0x4f, 0xfd, 0xd \
+ }
+
+#define EFI_WPCE791_PS2_KEYBOARD_ENABLE 0x01
+#define EFI_WPCE791_PS2_KEYBOARD_DISABLE 0x00
+
+#define EFI_WPCE791_PS2_MOUSE_ENABLE 0x01
+#define EFI_WPCE791_PS2_MOUSE_DISABLE 0x00
+
+typedef struct {
+ UINT16 Com1 :1; // 0 = Disable, 1 = Enable
+ UINT16 Lpt1 :1; // 0 = Disable, 1 = Enable
+ UINT16 Floppy :1; // 0 = Disable, 1 = Enable
+ UINT16 FloppyWriteProtect :1; // 0 = Write Protect, 1 = Write Enable
+ UINT16 Port80 :1; // 0 = Disable, 1 = Enable
+ UINT16 CIR :1; // CIR enable or disable
+ UINT16 Ps2Keyboard :1; // 0 = Disable, 1 = Enable
+ UINT16 Ps2Mouse :1; // 0 = Disable, 1 = Enable
+ UINT16 Com2 :1; // 0 = Disable, 1 = Enable
+ UINT16 Dac :1; // 0 = Disable, 1 = Enable
+ UINT16 Rsvd :6;
+} EFI_WPCE791_DEVICE_ENABLES;
+
+typedef struct _EFI_WPCE791_POLICY_PROTOCOL {
+ EFI_WPCE791_DEVICE_ENABLES DeviceEnables;
+} EFI_WPCE791_POLICY_PROTOCOL;
+
+extern EFI_GUID gEfiLpcWpce791PolicyProtocolGuid;
+
+#endif
diff --git a/BraswellPlatformPkg/Common/Include/Protocol/SmmSpiDevice.h b/BraswellPlatformPkg/Common/Include/Protocol/SmmSpiDevice.h new file mode 100644 index 0000000000..a4ff1efc82 --- /dev/null +++ b/BraswellPlatformPkg/Common/Include/Protocol/SmmSpiDevice.h @@ -0,0 +1,32 @@ +/** @file
+ Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _EFI_SMM_SPI_DEVICE_H_
+#define _EFI_SMM_SPI_DEVICE_H_
+
+#include <Protocol/SpiDevice.h>
+
+//
+// GUID definition for protocol interface
+//
+#define SMM_SPI_DEVICE_PROTOCOL_GUID \
+ {0xd963c5cd, 0x8cac, 0x498a, {0xbf, 0x78, 0xd1, 0x56, 0x49, 0x1, 0x85, 0x38}};
+
+extern EFI_GUID gSmmSpiDeviceProtocolGuid;
+
+//
+// Common definition for regular and SMM versions of the protocol.
+//
+typedef SPI_DEVICE_PROTOCOL SMM_SPI_DEVICE_PROTOCOL;
+
+#endif
diff --git a/BraswellPlatformPkg/Common/Include/Protocol/SpiDevice.h b/BraswellPlatformPkg/Common/Include/Protocol/SpiDevice.h new file mode 100644 index 0000000000..89f1599b97 --- /dev/null +++ b/BraswellPlatformPkg/Common/Include/Protocol/SpiDevice.h @@ -0,0 +1,159 @@ +/** @file
+ The header file of SPI Device driver.
+
+ Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _EFI_SPI_DEVICE_H_
+#define _EFI_SPI_DEVICE_H_
+
+//
+// GUID definition for protocol interface
+//
+#define SPI_DEVICE_PROTOCOL_GUID \
+ {0x37DCF59A, 0x944A, 0x11DF, {0x97, 0xD4, 0xE3, 0xAA, 0xC9, 0x24, 0x56, 0x53}}
+
+extern EFI_GUID gSpiDeviceProtocolGuid;
+
+//
+// Converts a flash memory mapped address into a flash linear address.
+//
+#define FLASH_LINEAR_ADDRESS(Base) ((Base) - PcdGet32 (PcdFlashAreaBaseAddress))
+
+/**
+ Performs a read from the flash device.
+
+ @param[in] SpiOffset Offset into the flash device.
+ @param[in, out] Size Size of the region to be read on input and the number
+ of bytes read on exit.
+ @param[out] Buffer A pointer to a caller allocated buffer large enough to hold
+ the resulting transaction.
+ @retval EFI_SUCCESS The transaction completed.
+ @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
+ @retval EFI_DEVICE_ERROR Unable to read data due to device state.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI* SPI_DEVICE_READ) (
+ IN UINTN SpiOffset,
+ IN OUT UINTN *Size,
+ OUT UINT8 *Buffer
+ );
+
+/**
+ Performs a write to the flash device.
+
+ @param[in] SpiOffset Offset into the flash device.
+ @param[in, out] Size Size of the region to be written to on input and the number
+ of bytes written on exit.
+ @param[out] Buffer A pointer to a caller allocated buffer that contains the
+ data to be written.
+ @retval EFI_SUCCESS The transaction completed.
+ @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
+ @retval EFI_DEVICE_ERROR Unable to write data due to device state.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI* SPI_DEVICE_WRITE) (
+ IN UINTN SpiOffset,
+ IN OUT UINTN *Size,
+ IN UINT8 *Buffer
+ );
+
+/**
+ Performs an erase operation to the flash device.
+
+ @param[in] SpiOffset Offset into the flash device.
+ @param[in, out] Size Size of the region to be erased on input and the number
+ of bytes erased on exit.
+ @retval EFI_SUCCESS The transaction completed.
+ @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
+ @retval EFI_DEVICE_ERROR Unable to erase data due to device state.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI* SPI_DEVICE_ERASE) (
+ IN UINTN SpiOffset,
+ IN OUT UINTN Size
+ );
+
+/**
+ Locks one or more blocks of the flash device.
+
+ @param[in] SpiOffset Offset into the flash device.
+ @param[in, out] Size Size of the region to be locked/unloced on input and the number
+ of bytes locked/unlocked on exit.
+ @param[in] Lock Selects the Lock or Unlock operation.
+
+ @retval EFI_SUCCESS The transaction completed.
+ @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
+ @retval EFI_DEVICE_ERROR Unable to erase data due to device state.
+ @retval EFI_UNSUPPORTED Feature is not supported at this time. All
+ blocks are to remain unlocked.
+**/
+typedef
+EFI_STATUS
+(EFIAPI* SPI_DEVICE_LOCK) (
+ IN UINTN SpiOffset,
+ IN OUT UINTN Size,
+ IN BOOLEAN Lock
+ );
+
+/**
+ Sets a range to be protected by the flash controller. This will either add
+ a new range or update an existing range. Overlapping regions are not supported.
+
+ @param[in] SpiOffset Defines the base address of the range as an SPI offset.
+ @param[in] Size Defines the size of the range.
+ @param[in] ReadLock Defines the policy for reads to the specified range.
+ @param[in] WriteLock Defines the policy for writes to the specified range.
+
+ @retval EFI_SUCCESS Range added successfully.
+ @retval EFI_ACCESS_DENIED Unable to add range due to configuration lock-down.
+ @retval EFI_OUT_OF_RESOURCES Unable to complete request with current PRRs available.
+ @retval EFI_INVALID_PARAMETER An invalid flash mapping was provided or the region
+ overlaps a region already set.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *SPI_DEVICE_SET_RANGE) (
+ IN UINTN SpiOffset,
+ IN UINTN Size,
+ IN BOOLEAN ReadLock,
+ IN BOOLEAN WriteLock
+ );
+
+/**
+ Locks out all further changes to protected ranges.
+
+ @retval EFI_SUCCESS Lock completed.
+ @retval EFI_ACCESS_DENIED Already locked.
+ @retval EFI_DEVICE_ERROR Unable to lock.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *SPI_DEVICE_LOCK_RANGES) (
+ );
+
+typedef struct {
+ SPI_DEVICE_READ SpiRead;
+ SPI_DEVICE_WRITE SpiWrite;
+ SPI_DEVICE_ERASE SpiErase;
+ SPI_DEVICE_LOCK SpiLock;
+ SPI_DEVICE_SET_RANGE SpiSetRange;
+ SPI_DEVICE_LOCK_RANGES SpiLockRanges;
+} SPI_DEVICE_PROTOCOL;
+
+#endif
diff --git a/BraswellPlatformPkg/Common/Include/Protocol/SpiFlashPart.h b/BraswellPlatformPkg/Common/Include/Protocol/SpiFlashPart.h new file mode 100644 index 0000000000..6b3c9fa7bc --- /dev/null +++ b/BraswellPlatformPkg/Common/Include/Protocol/SpiFlashPart.h @@ -0,0 +1,203 @@ +/** @file
+ SPI flash part protocol declaration
+
+ Copyright (c) 2013 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __SPI_FLASH_PART_H__
+#define __SPI_FLASH_PART_H__
+
+//
+// Index values into the flash part opcode table
+//
+#define SPI_FLASH_PART_OPCODE_JEDEC_ID 0
+#define SPI_FLASH_PART_OPCODE_READ_STATUS 1
+#define SPI_FLASH_PART_OPCODE_WRITE_STATUS 2
+#define SPI_FLASH_PART_OPCODE_READ_BYTES 3
+#define SPI_FLASH_PART_OPCODE_WRITE_256_BYTE_PAGE 4
+#define SPI_FLASH_PART_OPCODE_ERASE_4K_BYTE_BLOCK 5
+#define SPI_FLASH_PART_OPCODE_ERASE_64K_BYTE_BLOCK 6
+#define SPI_FLASH_PART_OPCODE_WRITE_DISABLE_DISCOVERY 7
+
+///
+/// SPI flash part opcode description
+///
+typedef struct {
+ ///
+ /// The maximum frequency in Hz to use for this opcode
+ ///
+ UINT32 MaxFrequency;
+
+ ///
+ /// Maximum transfer length
+ ///
+ UINT32 MaxTransferLength;
+
+ ///
+ /// Set to TRUE if sending the one of the WriteEnable bytes
+ /// before the opcode
+ ///
+ BOOLEAN EnableWrite;
+
+ ///
+ /// Opcode for the flash part
+ ///
+ UINT8 Opcode;
+
+ ///
+ /// Number of address bytes to send for this opcode
+ ///
+ UINT8 AddressBytes;
+
+ ///
+ /// Index for the opcode (SPI_FLASH_PART_OPCODE_*),
+ /// enables sparse opcode tables
+ ///
+ UINT8 OpcodeIndex;
+} SPI_FLASH_PART_OPCODE_ENTRY;
+
+typedef struct {
+ ///
+ /// Part number of the flash device
+ ///
+ CONST CHAR16 *PartNumber;
+
+ ///
+ /// Number of status bytes
+ ///
+ UINT8 StatusBytes;
+
+ ///
+ /// Write enable - Byte to issue before a write or erase command
+ ///
+ UINT8 WriteEnable;
+
+ ///
+ /// Write status enable - Byte to issue before a status write
+ ///
+ UINT8 WriteStatusEnable;
+
+ ///
+ /// Length of the JEDEC ID repsonse.
+ ///
+ UINT8 JededIdResponseLengthInBytes;
+
+ ///
+ /// Number of entries in the opcode table
+ ///
+ UINT8 OpcodeTableEntries;
+
+ ///
+ /// Opcodes supported by the SPI flash part
+ ///
+ SPI_FLASH_PART_OPCODE_ENTRY OpcodeTable [];
+} FLASH_PART_DESCRIPTION;
+
+///
+/// Forward reference to protocol
+///
+typedef struct _SPI_FLASH_PART_PROTOCOL SPI_FLASH_PART_PROTOCOL;
+
+/**
+ Get the flash part size and opcode table.
+
+ Validate support for this flash part and determine
+ the flash part size and opcode description table
+ from the JEDEC ID information provided.
+
+ @param This Pointer to a SPI_FLASH_DATA_PROTOCOL
+ data structure.
+ @param JedecId Pointer to a three byte buffer containing
+ the JEDEC ID returned by the flash part.
+ If the input value is NULL then a
+ table containing the description for the
+ JEDEC ID opcode is returned by this
+ routine.
+ @param FlashSize Pointer to receive the size of the flash
+ part in bytes. Zero (0) is returned when
+ JedecId is NULL.
+ @returns When JedecId is not NULL, this routine returns a pointer
+ to a FLASH_PART_DESCRIPTION data structure which supports
+ this flash part. The returned value is NULL if the flash
+ part is not supported.
+ When JedecId is NULL, this routine returns a pointer to
+ a FLASH_PART_DESCRIPTION structure which supports the
+ JEDEC ID command. This opcode description may be used
+ to determine the manufacture and product data for the
+ SPI flash part.
+
+**/
+typedef
+CONST FLASH_PART_DESCRIPTION *
+(EFIAPI *SPI_FLASH_PART_PROTOCOL_GET_FLASH_DESCRIPTION) (
+ IN SPI_FLASH_PART_PROTOCOL *This,
+ IN UINT8 *JedecId OPTIONAL,
+ OUT UINT64 *FlashSize OPTIONAL
+ );
+
+///
+/// SPI Flash Part Protocol
+///
+/// The SPI flash part protocol provides manufacture
+/// specific SPI flash opcode descriptions to the
+/// generic code which manipulates the SPI flash part.
+/// Descriptions may range from part specific through
+/// family specific to generic. The flash search
+/// algorithm use the Priority value to order which
+/// JEDEC ID opcodes are provided first to the SPI
+/// flash part.
+///
+/// Two Priority values will typically be defined by the
+/// IVH to support:
+/// * A single chip - higher value
+/// * A family of chips - lower value
+/// The GetOpcodeTable routine for these values matches
+/// all or part of the JEDEC ID value to make its determination.
+///
+/// The OEM may also provide a driver to provide a
+/// default opcode set. The GetOpcodeTable routine for the
+/// Priority value selected most likely will ignore the
+/// JEDEC ID value.
+///
+typedef struct _SPI_FLASH_PART_PROTOCOL {
+ ///
+ /// The search code uses the priority value to order
+ /// the processing of the SPI_FLASH_PART_PROTOCOL
+ /// entries to determine the support for the SPI flash
+ /// part. The Priority values of zero (0) is reserved.
+ /// Priority values of 0x00000001-0x0fffffff are reserved
+ /// for the platform/OEM specific drivers. The Priority
+ /// values of 0x10000000-0xffffffff are reserved for IHV
+ /// developed drivers. Note that Priority values do not
+ /// need to be unique. When two or more Priority values
+ /// are equal the order in which the JEDEC commands are
+ /// passed to the SPI flash part is random.
+ ///
+ UINT32 Priority;
+
+ ///
+ /// Get the flash part size and opcode table
+ ///
+ SPI_FLASH_PART_PROTOCOL_GET_FLASH_DESCRIPTION GetFlashDescription;
+} __SPI_FLASH_PART_PROTOCOL;
+
+///
+/// Reference to variable defined in the .DEC file
+///
+extern EFI_GUID gSpiFlashPartProtocolGuid;
+
+///
+/// Tag GUID to indicate that all SPI flash parts are available
+///
+extern EFI_GUID gSpiFlashPartSyncGuid;
+
+#endif // __SPI_FLASH_PART_H__
diff --git a/BraswellPlatformPkg/Common/Include/ReservedAcpiS3Range.h b/BraswellPlatformPkg/Common/Include/ReservedAcpiS3Range.h new file mode 100644 index 0000000000..1dc83b5d99 --- /dev/null +++ b/BraswellPlatformPkg/Common/Include/ReservedAcpiS3Range.h @@ -0,0 +1,33 @@ +/** @file
+ Structure and location in reserved memory used to store the location of ACPI
+ reserved memory used in S3 resume.
+
+ Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _RESERVED_ACPI_S3_RANGE_H_
+#define _RESERVED_ACPI_S3_RANGE_H_
+
+//
+// This structure stores the base and size of the ACPI reserved memory used when
+// resuming from S3. This region must be allocated by the platform code.
+// It is at the top of the first page of the TSEG.
+//
+typedef struct {
+ UINT32 AcpiReservedMemoryBase;
+ UINT32 AcpiReservedMemorySize;
+ UINT32 SystemMemoryLength;
+} RESERVED_ACPI_S3_RANGE;
+
+#define RESERVED_ACPI_S3_RANGE_OFFSET (EFI_PAGE_SIZE - sizeof (RESERVED_ACPI_S3_RANGE))
+
+#endif
|