diff options
| author | Guo Mang <mang.guo@intel.com> | 2016-08-03 10:08:22 +0800 |
|---|---|---|
| committer | Guo Mang <mang.guo@intel.com> | 2016-08-04 10:30:50 +0800 |
| commit | cc95732a88d815178f22793e13b3de8e4073e77b (patch) | |
| tree | 2d81a3b6af7e67c0a8dacd578e170d2b7a80d428 /BraswellPlatformPkg/Common | |
| parent | 40c3a7f1e81582b5a8279d405b5cb6ca80d99c42 (diff) | |
| download | edk2-platforms-cc95732a88d815178f22793e13b3de8e4073e77b.tar.xz | |
BraswellPlatformPkg: Move Library to Common/Library
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Guo Mang <mang.guo@intel.com>
Reviewed-by: David Wei <david.wei@intel.com>
Diffstat (limited to 'BraswellPlatformPkg/Common')
54 files changed, 10389 insertions, 0 deletions
diff --git a/BraswellPlatformPkg/Common/Library/BiosIdLib/BiosIdLib.c b/BraswellPlatformPkg/Common/Library/BiosIdLib/BiosIdLib.c new file mode 100644 index 0000000000..d80cfbf549 --- /dev/null +++ b/BraswellPlatformPkg/Common/Library/BiosIdLib/BiosIdLib.c @@ -0,0 +1,330 @@ +/** @file
+ Boot service DXE BIOS ID library implementation.
+ These functions in this file can be called during DXE and cannot be called during runtime
+ or in SMM which should use a RT or SMM library.
+
+ Copyright (c) 2011 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <PiDxe.h>
+#include <Library/BaseLib.h>
+#include <Library/HobLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BiosIdLib.h>
+#include <Guid/BiosId.h>
+#include <Protocol/FirmwareVolume2.h>
+#include <Protocol/LoadedImage.h>
+
+EFI_STATUS
+GetImageFromFv (
+ IN EFI_FIRMWARE_VOLUME2_PROTOCOL *Fv,
+ IN EFI_GUID *NameGuid,
+ IN EFI_SECTION_TYPE SectionType,
+ OUT VOID **Buffer,
+ OUT UINTN *Size
+ )
+{
+ EFI_STATUS Status;
+ EFI_FV_FILETYPE FileType;
+ EFI_FV_FILE_ATTRIBUTES Attributes;
+ UINT32 AuthenticationStatus;
+
+ //
+ // Read desired section content in NameGuid file
+ //
+ *Buffer = NULL;
+ *Size = 0;
+ Status = Fv->ReadSection (
+ Fv,
+ NameGuid,
+ SectionType,
+ 0,
+ Buffer,
+ Size,
+ &AuthenticationStatus
+ );
+
+ if (EFI_ERROR (Status) && (SectionType == EFI_SECTION_TE)) {
+ //
+ // Try reading PE32 section, since the TE section does not exist
+ //
+ *Buffer = NULL;
+ *Size = 0;
+ Status = Fv->ReadSection (
+ Fv,
+ NameGuid,
+ EFI_SECTION_PE32,
+ 0,
+ Buffer,
+ Size,
+ &AuthenticationStatus
+ );
+ }
+
+ if (EFI_ERROR (Status) &&
+ ((SectionType == EFI_SECTION_TE) || (SectionType == EFI_SECTION_PE32))) {
+ //
+ // Try reading raw file, since the desired section does not exist
+ //
+ *Buffer = NULL;
+ *Size = 0;
+ Status = Fv->ReadFile (
+ Fv,
+ NameGuid,
+ Buffer,
+ Size,
+ &FileType,
+ &Attributes,
+ &AuthenticationStatus
+ );
+ }
+
+ return Status;
+}
+
+EFI_STATUS
+GetImageEx (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_GUID *NameGuid,
+ IN EFI_SECTION_TYPE SectionType,
+ OUT VOID **Buffer,
+ OUT UINTN *Size,
+ BOOLEAN WithinImageFv
+ )
+{
+ EFI_STATUS Status;
+ EFI_HANDLE *HandleBuffer;
+ UINTN HandleCount;
+ UINTN Index;
+ EFI_LOADED_IMAGE_PROTOCOL *LoadedImage;
+
+ EFI_FIRMWARE_VOLUME2_PROTOCOL *ImageFv;
+ EFI_FIRMWARE_VOLUME2_PROTOCOL *Fv;
+
+ if (ImageHandle == NULL && WithinImageFv) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ Status = EFI_NOT_FOUND;
+ ImageFv = NULL;
+ if (ImageHandle != NULL) {
+ Status = gBS->HandleProtocol (
+ ImageHandle,
+ &gEfiLoadedImageProtocolGuid,
+ (VOID **) &LoadedImage
+ );
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+ Status = gBS->HandleProtocol (
+ LoadedImage->DeviceHandle,
+ &gEfiFirmwareVolume2ProtocolGuid,
+ (VOID **) &ImageFv
+ );
+ if (!EFI_ERROR (Status)) {
+ Status = GetImageFromFv (ImageFv, NameGuid, SectionType, Buffer, Size);
+ }
+ }
+
+ if (Status == EFI_SUCCESS || WithinImageFv) {
+ return Status;
+ }
+
+ Status = gBS->LocateHandleBuffer (
+ ByProtocol,
+ &gEfiFirmwareVolume2ProtocolGuid,
+ NULL,
+ &HandleCount,
+ &HandleBuffer
+ );
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ //
+ // Find desired image in all Fvs
+ //
+ for (Index = 0; Index < HandleCount; ++Index) {
+ Status = gBS->HandleProtocol (
+ HandleBuffer[Index],
+ &gEfiFirmwareVolume2ProtocolGuid,
+ (VOID**)&Fv
+ );
+
+ if (EFI_ERROR (Status)) {
+ gBS->FreePool(HandleBuffer);
+ return Status;
+ }
+
+ if (ImageFv != NULL && Fv == ImageFv) {
+ continue;
+ }
+
+ Status = GetImageFromFv (Fv, NameGuid, SectionType, Buffer, Size);
+
+ if (!EFI_ERROR (Status)) {
+ break;
+ }
+ }
+ gBS->FreePool(HandleBuffer);
+
+ //
+ // Not found image
+ //
+ if (Index == HandleCount) {
+ return EFI_NOT_FOUND;
+ }
+
+ return EFI_SUCCESS;
+}
+
+/**
+ This function returns BIOS ID by searching HOB or FV.
+
+ @param[out] BiosIdImage The BIOS ID got from HOB or FV.
+
+ @retval EFI_SUCCESS All parameters were valid and BIOS ID has been got.
+ @retval EFI_NOT_FOUND BiosId image is not found, and no parameter will be modified.
+ @retval EFI_INVALID_PARAMETER The parameter is NULL.
+
+**/
+EFI_STATUS
+GetBiosId (
+ OUT BIOS_ID_IMAGE *BiosIdImage
+ )
+
+{
+ EFI_STATUS Status;
+ VOID *Address = NULL;
+ UINTN Size = 0;
+
+ DEBUG ((EFI_D_INFO, "Get BIOS ID from FV\n"));
+
+ Status = GetImageEx (
+ NULL,
+ &gEfiBiosIdGuid,
+ EFI_SECTION_RAW,
+ &Address,
+ &Size,
+ FALSE
+ );
+
+ if (Status == EFI_SUCCESS) {
+ //
+ // BiosId image is present in FV
+ //
+ if (Address != NULL) {
+ Size = sizeof (BIOS_ID_IMAGE);
+ gBS->CopyMem (
+ (void *) BiosIdImage,
+ Address,
+ Size
+ );
+ //
+ // GetImage () allocated buffer for Address, now clear it.
+ //
+ gBS->FreePool (Address);
+
+ DEBUG ((EFI_D_INFO, "Get BIOS ID from FV successfully\n"));
+ DEBUG ((EFI_D_INFO, "BIOS ID: %s\n", (CHAR16 *) (&(BiosIdImage->BiosIdString))));
+
+ return EFI_SUCCESS;
+ }
+ }
+
+ return EFI_NOT_FOUND;
+}
+
+/**
+ This function returns the Version & Release Date and Time by getting and converting
+ BIOS ID.
+
+ @param[out] BiosVersion The Bios Version out of the conversion.
+ @param[out] BiosReleaseDate The Bios Release Date out of the conversion.
+ @param[out] BiosReleaseTime The Bios Release Time out of the conversion.
+
+ @retval EFI_SUCCESS BIOS Version & Release Date and Time have been got successfully.
+ @retval EFI_NOT_FOUND BiosId image is not found, and no parameter will be modified.
+ @retval EFI_INVALID_PARAMETER All the parameters are NULL.
+
+**/
+EFI_STATUS
+GetBiosVersionDateTime (
+ OUT CHAR16 *BiosVersion, OPTIONAL
+ OUT CHAR16 *BiosReleaseDate, OPTIONAL
+ OUT CHAR16 *BiosReleaseTime OPTIONAL
+ )
+{
+ EFI_STATUS Status;
+ BIOS_ID_IMAGE BiosIdImage;
+
+ if ((BiosVersion == NULL) && (BiosReleaseDate == NULL) && (BiosReleaseTime == NULL)) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ Status = GetBiosId (&BiosIdImage);
+ if (EFI_ERROR (Status)) {
+ return EFI_NOT_FOUND;
+ }
+
+ if (BiosVersion != NULL) {
+ //
+ // Fill the BiosVersion data from the BIOS ID.
+ //
+ StrCpy (BiosVersion, (CHAR16 *) (&(BiosIdImage.BiosIdString)));
+ }
+
+ if (BiosReleaseDate != NULL) {
+ //
+ // Fill the build timestamp date from the BIOS ID in the "MM/DD/YY" format.
+ //
+ BiosReleaseDate[0] = BiosIdImage.BiosIdString.TimeStamp[2];
+ BiosReleaseDate[1] = BiosIdImage.BiosIdString.TimeStamp[3];
+ BiosReleaseDate[2] = (CHAR16) ((UINT8) ('/'));
+
+ BiosReleaseDate[3] = BiosIdImage.BiosIdString.TimeStamp[4];
+ BiosReleaseDate[4] = BiosIdImage.BiosIdString.TimeStamp[5];
+ BiosReleaseDate[5] = (CHAR16) ((UINT8) ('/'));
+
+ //
+ // Add 20 for SMBIOS table
+ // Current Linux kernel will misjudge 09 as year 0, so using 2009 for SMBIOS table
+ //
+ BiosReleaseDate[6] = '2';
+ BiosReleaseDate[7] = '0';
+ BiosReleaseDate[8] = BiosIdImage.BiosIdString.TimeStamp[0];
+ BiosReleaseDate[9] = BiosIdImage.BiosIdString.TimeStamp[1];
+
+ BiosReleaseDate[10] = (CHAR16) ((UINT8) ('\0'));
+ }
+
+ if (BiosReleaseTime != NULL) {
+
+ //
+ // Fill the build timestamp time from the BIOS ID in the "HH:MM" format.
+ //
+
+ BiosReleaseTime[0] = BiosIdImage.BiosIdString.TimeStamp[6];
+ BiosReleaseTime[1] = BiosIdImage.BiosIdString.TimeStamp[7];
+ BiosReleaseTime[2] = (CHAR16) ((UINT8) (':'));
+
+ BiosReleaseTime[3] = BiosIdImage.BiosIdString.TimeStamp[8];
+ BiosReleaseTime[4] = BiosIdImage.BiosIdString.TimeStamp[9];
+
+ BiosReleaseTime[5] = (CHAR16) ((UINT8) ('\0'));
+ }
+
+ return EFI_SUCCESS;
+}
+
diff --git a/BraswellPlatformPkg/Common/Library/BiosIdLib/BiosIdLib.inf b/BraswellPlatformPkg/Common/Library/BiosIdLib/BiosIdLib.inf new file mode 100644 index 0000000000..1443e885ae --- /dev/null +++ b/BraswellPlatformPkg/Common/Library/BiosIdLib/BiosIdLib.inf @@ -0,0 +1,52 @@ +## @file
+# Component description file for BIOS ID library.
+#
+# Getting image from FV, and getting BIOS ID by searching HOB or FV
+#
+# Copyright (c) 2013 - 2015, Intel Corporation. All rights reserved.<BR>
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php.
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = BiosIdLib
+ FILE_GUID = 98546145-64F1-4d2e-814F-6BF963DB7930
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = BiosIdLib
+ PI_SPECIFICATION_VERSION = 0x0001000A
+
+[Sources]
+ BiosIdLib.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ ChvRefCodePkg/ChvRefCodePkg.dec
+ BraswellPlatformPkg/BraswellPlatformPkg.dec
+
+[LibraryClasses]
+ HobLib
+
+[Guids]
+ gEfiBiosIdGuid ## SOMETIMES_CONSUMES ## GUID
+
+[Protocols]
+ ## CONSUMES
+ ## SOMETIMES_CONSUMES
+ gEfiLoadedImageProtocolGuid
+
+ gEfiFirmwareVolume2ProtocolGuid ## CONSUMES
+
+[Depex]
+ gEfiLoadedImageProtocolGuid AND
+ gEfiFirmwareVolume2ProtocolGuid
diff --git a/BraswellPlatformPkg/Common/Library/CpuIA32Lib/CpuIA32Lib.inf b/BraswellPlatformPkg/Common/Library/CpuIA32Lib/CpuIA32Lib.inf new file mode 100644 index 0000000000..d6f440a889 --- /dev/null +++ b/BraswellPlatformPkg/Common/Library/CpuIA32Lib/CpuIA32Lib.inf @@ -0,0 +1,39 @@ +## @file
+# Component description file for the Cpu IA32 library.
+#
+# Getting CPU version, including FamilyId, FamilyId, SteppingId info.
+#
+# Copyright (c) 2013 - 2015, Intel Corporation. All rights reserved.<BR>
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php.
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = CpuIA32Lib
+ FILE_GUID = 98546178-64F1-4d2e-814F-6BF963DB7930
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = CpuIA32Lib
+ PI_SPECIFICATION_VERSION = 0x0001000A
+
+[Sources]
+ EfiCpuVersion.c
+
+[Sources.IA32]
+ IA32/CpuIA32.c
+
+[Sources.X64]
+ X64/Cpu.asm
+ X64/Cpu.S
+
+[Packages]
+ MdePkg/MdePkg.dec
+ BraswellPlatformPkg/BraswellPlatformPkg.dec
diff --git a/BraswellPlatformPkg/Common/Library/CpuIA32Lib/EfiCpuVersion.c b/BraswellPlatformPkg/Common/Library/CpuIA32Lib/EfiCpuVersion.c new file mode 100644 index 0000000000..e11d0dc8c0 --- /dev/null +++ b/BraswellPlatformPkg/Common/Library/CpuIA32Lib/EfiCpuVersion.c @@ -0,0 +1,67 @@ +/** @file
+ Provide Cpu version extract considering extended family & model ID.
+
+ Copyright (c) 2004 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Library/CpuIA32.h>
+
+/**
+ Extract CPU detail version infomation
+
+ @param[in, out] FamilyId FamilyId, including ExtendedFamilyId
+ @param[in, out] Model Model, including ExtendedModel
+ @param[in, out] SteppingId SteppingId
+ @param[in, out] Processor Processor
+
+**/
+VOID
+EFIAPI
+EfiCpuVersion (
+ IN OUT UINT16 *FamilyId, OPTIONAL
+ IN OUT UINT8 *Model, OPTIONAL
+ IN OUT UINT8 *SteppingId, OPTIONAL
+ IN OUT UINT8 *Processor OPTIONAL
+ )
+
+{
+ EFI_CPUID_REGISTER Register;
+ UINT8 TempFamilyId;
+
+ EfiCpuid (EFI_CPUID_VERSION_INFO, &Register);
+
+ if (SteppingId != NULL) {
+ *SteppingId = (UINT8) (Register.RegEax & 0xF);
+ }
+
+ if (Processor != NULL) {
+ *Processor = (UINT8) ((Register.RegEax >> 12) & 0x3);
+ }
+
+ if (Model != NULL || FamilyId != NULL) {
+ TempFamilyId = (UINT8) ((Register.RegEax >> 8) & 0xF);
+
+ if (Model != NULL) {
+ *Model = (UINT8) ((Register.RegEax >> 4) & 0xF);
+ if (TempFamilyId == 0x6 || TempFamilyId == 0xF) {
+ *Model = (UINT8) (*Model | ((Register.RegEax >> 12) & 0xF0));
+ }
+ }
+
+ if (FamilyId != NULL) {
+ *FamilyId = TempFamilyId;
+ if (TempFamilyId == 0xF) {
+ *FamilyId = (UINT8 ) (*FamilyId + (UINT16) ((Register.RegEax >> 20) & 0xFF));
+ }
+ }
+ }
+}
diff --git a/BraswellPlatformPkg/Common/Library/CpuIA32Lib/IA32/CpuIA32.S b/BraswellPlatformPkg/Common/Library/CpuIA32Lib/IA32/CpuIA32.S new file mode 100644 index 0000000000..42041752a2 --- /dev/null +++ b/BraswellPlatformPkg/Common/Library/CpuIA32Lib/IA32/CpuIA32.S @@ -0,0 +1,221 @@ +## @file
+# Assembly code that supports IA32 CPU architectural protocol.
+#
+# Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.<BR>
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php.
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED
+#
+##
+
+##include "CpuIA32.h"
+#include "EfiBind.h"
+
+#---------------------------------------------------------------------------
+ .586p:
+ #.MODEL flat,C
+ .code:
+
+#---------------------------------------------------------------------------
+
+.globl ASM_PFX(EfiHalt)
+.globl ASM_PFX(EfiWbinvd)
+.globl ASM_PFX(EfiInvd)
+.globl ASM_PFX(EfiCpuid)
+.globl ASM_PFX(EfiReadMsr)
+.globl ASM_PFX(EfiWriteMsr)
+.globl ASM_PFX(EfiReadTsc)
+.globl ASM_PFX(EfiDisableCache)
+.globl ASM_PFX(EfiEnableCache)
+.globl ASM_PFX(EfiGetEflags)
+.globl ASM_PFX(EfiDisableInterrupts)
+.globl ASM_PFX(EfiEnableInterrupts)
+.globl ASM_PFX(EfiCpuidExt)
+
+
+#VOID
+#EfiHalt (
+# VOID
+#)
+ASM_PFX(EfiHalt):
+ hlt
+ ret
+#EfiHalt ENDP
+
+#VOID
+#EfiWbinvd (
+# VOID
+#)
+ASM_PFX(EfiWbinvd):
+ wbinvd
+ ret
+#EfiWbinvd ENDP
+
+#VOID
+#EfiInvd (
+# VOID
+#)
+ASM_PFX(EfiInvd):
+ invd
+ ret
+#EfiInvd ENDP
+
+#VOID
+#EfiCpuid (IN UINT32 RegisterInEax,
+# OUT EFI_CPUID_REGISTER *Reg OPTIONAL)
+ASM_PFX(EfiCpuid):
+ pushl %ebp
+ movl %esp, %ebp
+ pushl %ebx
+ pushl %esi
+ pushl %edi
+ pushal
+
+ movl 8(%ebp), %eax #RegisterInEax
+ cpuid
+ cmpl $0, 0xC(%ebp) # Reg
+ je L1
+ movl 0xC(%ebp), %edi # Reg
+
+ movl %eax, (%edi) # Reg->RegEax
+ movl %ebx, 4(%edi) # Reg->RegEbx
+ movl %ecx, 8(%edi) # Reg->RegEcx
+ movl %edx, 0xC(%edi) # Reg->RegEdx
+
+L1:
+ popal
+ popl %edi
+ popl %esi
+ popl %ebx
+ popl %ebp
+
+ ret
+#EfiCpuid ENDP
+
+
+#UINT64
+#EfiReadMsr (
+# IN UINT32 Index
+# );
+ASM_PFX(EfiReadMsr):
+ movl 4(%esp), %ecx # Index
+ rdmsr
+ ret
+#EfiReadMsr ENDP
+
+#VOID
+#EfiWriteMsr (
+# IN UINT32 Index,
+# IN UINT64 Value
+# );
+ASM_PFX(EfiWriteMsr):
+ movl 4(%esp), %ecx # Index
+ movl 8(%esp), %eax # DWORD PTR Value[0]
+ movl 0xC(%esp), %edx # DWORD PTR Value[4]
+ wrmsr
+ ret
+#EfiWriteMsr ENDP
+
+#UINT64
+#EfiReadTsc (
+# VOID
+# )
+ASM_PFX(EfiReadTsc):
+ rdtsc
+ ret
+#EfiReadTsc ENDP
+
+#VOID
+#EfiDisableCache (
+# VOID
+#)
+ASM_PFX(EfiDisableCache):
+ movl %cr0, %eax
+ bswapl %eax
+ andb $0x60, %al
+ cmpb $0x60, %al
+ je L2
+ movl %cr0, %eax
+ orl $0x60000000, %eax
+ movl %eax, %cr0
+ wbinvd
+L2:
+ ret
+#EfiDisableCache ENDP
+
+#VOID
+#EfiEnableCache (
+# VOID
+# )
+ASM_PFX(EfiEnableCache):
+ wbinvd
+ movl %cr0, %eax
+ andl $0x9fffffff, %eax
+ movl %eax, %cr0
+ ret
+#EfiEnableCache ENDP
+
+#UINT32
+#EfiGetEflags (
+# VOID
+# )
+ASM_PFX(EfiGetEflags):
+ pushfl
+ popl %eax
+ ret
+#EfiGetEflags ENDP
+
+#VOID
+#EfiDisableInterrupts (
+# VOID
+# )
+ASM_PFX(EfiDisableInterrupts):
+ cli
+ ret
+#EfiDisableInterrupts ENDP
+
+#VOID
+#EfiEnableInterrupts (
+# VOID
+# )
+ASM_PFX(EfiEnableInterrupts):
+ sti
+ ret
+#EfiEnableInterrupts ENDP
+
+#VOID
+#EfiCpuidExt (
+# IN UINT32 RegisterInEax,
+# IN UINT32 CacheLevel,
+# OUT EFI_CPUID_REGISTER *Regs
+# )
+ASM_PFX(EfiCpuidExt):
+ push %ebx
+ push %edi
+ push %esi
+ pushal
+
+ movl 0x30(%esp), %eax # RegisterInEax
+ movl 0x34(%esp), %ecx # CacheLevel
+ cpuid
+ movl 0x38(%esp), %edi # DWORD PTR Regs
+
+ movl %eax, (%edi) # Reg->RegEax
+ movl %ebx, 4(%edi) # Reg->RegEbx
+ movl %ecx, 8(%edi) # Reg->RegEcx
+ movl %edx, 0xC(%edi) # Reg->RegEdx
+
+ popal
+ pop %esi
+ pop %edi
+ pop %ebx
+ ret
+#EfiCpuidExt ENDP
+
+
+
diff --git a/BraswellPlatformPkg/Common/Library/CpuIA32Lib/IA32/CpuIA32.asm b/BraswellPlatformPkg/Common/Library/CpuIA32Lib/IA32/CpuIA32.asm new file mode 100644 index 0000000000..07ccefa191 --- /dev/null +++ b/BraswellPlatformPkg/Common/Library/CpuIA32Lib/IA32/CpuIA32.asm @@ -0,0 +1,197 @@ +;; @file
+;
+; Copyright (c) 2004 - 2015, Intel Corporation. All rights reserved.<BR>
+;
+; This program and the accompanying materials
+; are licensed and made available under the terms and conditions of the BSD License
+; which accompanies this distribution. The full text of the license may be found at
+; http://opensource.org/licenses/bsd-license.php.
+;
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+;
+;;
+
+;#include "CpuIA32.h"
+
+;---------------------------------------------------------------------------
+ .586p
+ .model flat,C
+ .code
+
+;---------------------------------------------------------------------------
+;VOID
+;EfiHalt (
+; VOID
+;)
+EfiHalt PROC C PUBLIC
+ hlt
+ ret
+EfiHalt ENDP
+
+;VOID
+;EfiWbinvd (
+; VOID
+;)
+EfiWbinvd PROC C PUBLIC
+ wbinvd
+ ret
+EfiWbinvd ENDP
+
+;VOID
+;EfiInvd (
+; VOID
+;)
+EfiInvd PROC C PUBLIC
+ invd
+ ret
+EfiInvd ENDP
+
+;VOID
+;EfiCpuid (IN UINT32 RegisterInEax,
+; OUT EFI_CPUID_REGISTER *Reg OPTIONAL)
+EfiCpuid PROC C PUBLIC
+ push ebp
+ mov ebp, esp
+ push ebx
+ push esi
+ push edi
+ pushad
+
+ mov eax, dword ptr[ebp + 8] ;egisterInEax
+ cpuid
+ cmp dword ptr[ebp + 0Ch], 0 ; Reg
+ je @F
+ mov edi,dword ptr [ebp+0Ch] ; Reg
+
+ mov dword ptr [edi],eax ; Reg->RegEax
+ mov dword ptr [edi+4],ebx ; Reg->RegEbx
+ mov dword ptr [edi+8],ecx ; Reg->RegEcx
+ mov dword ptr [edi+0Ch],edx ; Reg->RegEdx
+
+@@:
+ popad
+ pop edi
+ pop esi
+ pop ebx
+ pop ebp
+
+ ret
+EfiCpuid ENDP
+
+
+;UINT64
+;EfiReadMsr (
+; IN UINT32 Index
+; );
+EfiReadMsr PROC C PUBLIC
+ mov ecx, dword ptr [esp + 4]; Index
+ rdmsr
+ ret
+EfiReadMsr ENDP
+
+;VOID
+;EfiWriteMsr (
+; IN UINT32 Index,
+; IN UINT64 Value
+; );
+EfiWriteMsr PROC C PUBLIC
+ mov ecx, dword ptr [esp+4]; Index
+ mov eax, dword ptr [esp+8]; DWORD PTR Value[0]
+ mov edx, dword ptr [esp+0Ch]; DWORD PTR Value[4]
+ wrmsr
+ ret
+EfiWriteMsr ENDP
+
+;UINT64
+;EfiReadTsc (
+; VOID
+; )
+EfiReadTsc PROC C PUBLIC
+ rdtsc
+ ret
+EfiReadTsc ENDP
+
+;VOID
+;EfiDisableCache (
+; VOID
+;)
+EfiDisableCache PROC C PUBLIC
+ mov eax, cr0
+ bswap eax
+ and al, 60h
+ cmp al, 60h
+ je @F
+ mov eax, cr0
+ or eax, 060000000h
+ mov cr0, eax
+ wbinvd
+@@:
+ ret
+EfiDisableCache ENDP
+
+;VOID
+;EfiEnableCache (
+; VOID
+; )
+EfiEnableCache PROC C PUBLIC
+ wbinvd
+ mov eax, cr0
+ and eax, 09fffffffh
+ mov cr0, eax
+ ret
+EfiEnableCache ENDP
+
+;UINT32
+;EfiGetEflags (
+; VOID
+; )
+EfiGetEflags PROC C PUBLIC
+ pushfd
+ pop eax
+ ret
+EfiGetEflags ENDP
+
+;VOID
+;EfiDisableInterrupts (
+; VOID
+; )
+EfiDisableInterrupts PROC C PUBLIC
+ cli
+ ret
+EfiDisableInterrupts ENDP
+
+;VOID
+;EfiEnableInterrupts (
+; VOID
+; )
+EfiEnableInterrupts PROC C PUBLIC
+ sti
+ ret
+EfiEnableInterrupts ENDP
+
+;VOID
+;EfiCpuidExt (
+; IN UINT32 RegisterInEax,
+; IN UINT32 CacheLevel,
+; OUT EFI_CPUID_REGISTER *Regs
+; )
+EfiCpuidExt PROC C PUBLIC USES ebx edi esi
+ pushad
+
+ mov eax, dword ptr [esp + 30h] ; RegisterInEax
+ mov ecx, dword ptr [esp + 34h] ; CacheLevel
+ cpuid
+ mov edi, dword ptr [esp + 38h] ; DWORD PTR Regs
+
+ mov dword ptr [edi], eax ; Reg->RegEax
+ mov dword ptr [edi + 4], ebx ; Reg->RegEbx
+ mov dword ptr [edi + 8], ecx ; Reg->RegEcx
+ mov dword ptr [edi + 0Ch], edx ; Reg->RegEdx
+
+ popad
+ ret
+EfiCpuidExt ENDP
+
+ END
+
diff --git a/BraswellPlatformPkg/Common/Library/CpuIA32Lib/IA32/CpuIA32.c b/BraswellPlatformPkg/Common/Library/CpuIA32Lib/IA32/CpuIA32.c new file mode 100644 index 0000000000..bff93cf135 --- /dev/null +++ b/BraswellPlatformPkg/Common/Library/CpuIA32Lib/IA32/CpuIA32.c @@ -0,0 +1,174 @@ +/** @file
+
+ Copyright (c) 2004 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Library/CpuIA32.h>
+
+VOID
+EfiHalt (VOID)
+{
+ __asm {
+ hlt
+ }
+}
+
+VOID
+EfiWbinvd (VOID)
+{
+ __asm {
+ wbinvd
+ }
+}
+
+VOID
+EfiInvd (VOID)
+{
+ __asm {
+ invd
+ }
+}
+
+VOID
+EfiCpuid (IN UINT32 RegisterInEax,
+ OUT EFI_CPUID_REGISTER *Reg OPTIONAL)
+{
+ __asm {
+ pushad
+
+ mov eax, RegisterInEax
+ cpuid
+ cmp Reg, 0
+ je _Exit
+ mov edi, DWORD PTR Reg
+
+ mov DWORD PTR [edi].RegEax, eax ; Reg->RegEax
+ mov DWORD PTR [edi].RegEbx, ebx ; Reg->RegEbx
+ mov DWORD PTR [edi].RegEcx, ecx ; Reg->RegEcx
+ mov DWORD PTR [edi].RegEdx, edx ; Reg->RegEdx
+
+_Exit:
+ popad
+ }
+}
+
+UINT64
+EfiReadMsr (IN UINT32 Index)
+{
+ __asm {
+ mov ecx, Index
+ rdmsr
+ }
+}
+
+VOID
+EfiWriteMsr (
+ IN UINT32 Index,
+ IN UINT64 Value
+ )
+{
+ __asm {
+ mov ecx, Index
+ mov eax, DWORD PTR Value[0]
+ mov edx, DWORD PTR Value[4]
+ wrmsr
+ }
+}
+
+UINT64
+EfiReadTsc (VOID)
+{
+ __asm {
+ rdtsc
+ }
+}
+
+VOID
+EfiDisableCache (VOID)
+{
+ __asm {
+ mov eax, cr0
+ bswap eax
+ and al, 60h
+ cmp al, 60h
+ je Exit
+ mov eax, cr0
+ or eax, 060000000h
+ mov cr0, eax
+ wbinvd
+Exit:
+ }
+}
+
+VOID
+EfiEnableCache (VOID)
+{
+ __asm {
+ wbinvd
+ mov eax, cr0
+ and eax, 09fffffffh
+ mov cr0, eax
+ }
+}
+
+UINT32
+EfiGetEflags (
+ VOID
+ )
+{
+ __asm {
+ pushfd
+ pop eax
+ }
+}
+
+VOID
+EfiDisableInterrupts (VOID)
+{
+ __asm {
+ cli
+ }
+}
+
+VOID
+EfiEnableInterrupts (
+ VOID
+ )
+{
+ __asm {
+ sti
+ }
+}
+
+VOID
+EfiCpuidExt (
+ IN UINT32 RegisterInEax,
+ IN UINT32 CacheLevel,
+ OUT EFI_CPUID_REGISTER *Regs
+ )
+{
+ __asm {
+ pushad
+
+ mov eax, RegisterInEax
+ mov ecx, CacheLevel
+ cpuid
+ mov edi, DWORD PTR Regs
+
+ mov DWORD PTR [edi].RegEax, eax ; Reg->RegEax
+ mov DWORD PTR [edi].RegEbx, ebx ; Reg->RegEbx
+ mov DWORD PTR [edi].RegEcx, ecx ; Reg->RegEcx
+ mov DWORD PTR [edi].RegEdx, edx ; Reg->RegEdx
+
+ popad
+ }
+}
diff --git a/BraswellPlatformPkg/Common/Library/CpuIA32Lib/X64/Cpu.S b/BraswellPlatformPkg/Common/Library/CpuIA32Lib/X64/Cpu.S new file mode 100644 index 0000000000..7a0c839f8f --- /dev/null +++ b/BraswellPlatformPkg/Common/Library/CpuIA32Lib/X64/Cpu.S @@ -0,0 +1,206 @@ +## @file
+# Assembly code that supports CPU architectural protocol.
+#
+# Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.<BR>
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php.
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED
+#
+##
+
+##include <EfiBind.h>
+
+.globl ASM_PFX(EfiHalt)
+.globl ASM_PFX(EfiWbinvd)
+.globl ASM_PFX(EfiInvd)
+.globl ASM_PFX(EfiCpuid)
+.globl ASM_PFX(EfiReadTsc)
+.globl ASM_PFX(EfiDisableCache)
+.globl ASM_PFX(EfiEnableCache)
+.globl ASM_PFX(EfiReadMsr)
+.globl ASM_PFX(EfiWriteMsr)
+.globl ASM_PFX(EfiGetEflags)
+.globl ASM_PFX(EfiDisableInterrupts)
+.globl ASM_PFX(EfiEnableInterrupts)
+.globl ASM_PFX(EfiCpuidExt)
+
+.text
+
+
+#------------------------------------------------------------------------------
+# VOID
+# EfiHalt (
+# VOID
+# )
+#------------------------------------------------------------------------------
+ASM_PFX(EfiHalt):
+ hlt
+ retq
+
+
+#------------------------------------------------------------------------------
+# VOID
+# EfiWbinvd (
+# VOID
+# )
+#------------------------------------------------------------------------------
+ASM_PFX(EfiWbinvd):
+ wbinvd
+ retq
+
+
+#------------------------------------------------------------------------------
+# VOID
+# EfiInvd (
+# VOID
+# )
+#------------------------------------------------------------------------------
+ASM_PFX(EfiInvd):
+ invd
+ retq
+
+#------------------------------------------------------------------------------
+# VOID
+# EfiCpuid (
+# IN UINT32 RegisterInEax, // rcx
+# OUT EFI_CPUID_REGISTER *Reg OPTIONAL // rdx
+# )
+#------------------------------------------------------------------------------
+ASM_PFX(EfiCpuid):
+ push %rbx
+ mov %rdx,%r8
+ mov %rcx,%rax
+ cpuid
+ cmp $0x0,%r8
+ je _Exit
+ mov %eax,(%r8)
+ mov %ebx,0x4(%r8)
+ mov %ecx,0x8(%r8)
+ mov %edx,0xc(%r8)
+_Exit:
+ pop %rbx
+ retq
+
+#------------------------------------------------------------------------------
+# UINT64
+# EfiReadMsr (
+# IN UINT32 Index, // rcx
+# )
+#------------------------------------------------------------------------------
+ASM_PFX(EfiReadMsr):
+ rdmsr
+ shl $0x20,%rdx
+ or %rdx,%rax
+ retq
+
+#------------------------------------------------------------------------------
+# VOID
+# EfiWriteMsr (
+# IN UINT32 Index, // rcx
+# IN UINT64 Value // rdx
+# )
+#------------------------------------------------------------------------------
+ASM_PFX(EfiWriteMsr):
+ mov %rdx,%rax
+ sar $0x20,%rdx
+ wrmsr
+ retq
+
+#------------------------------------------------------------------------------
+# UINT64
+# EfiReadTsc (
+# VOID
+# );
+#------------------------------------------------------------------------------
+ASM_PFX(EfiReadTsc):
+ rdtsc
+ shl $0x20,%rax
+ shrd $0x20,%rdx,%rax
+ retq
+
+#------------------------------------------------------------------------------
+# VOID
+# EfiDisableCache (
+# VOID
+# );
+#------------------------------------------------------------------------------
+ASM_PFX(EfiDisableCache):
+# added a check to see if cache is already disabled. If it is, then skip.
+ mov %cr0,%rax
+ and $0x60000000,%rax
+ cmp $0x0,%rax
+ jne 1f
+ mov %cr0,%rax
+ or $0x60000000,%rax
+ mov %rax,%cr0
+ wbinvd
+1:
+ retq
+
+#------------------------------------------------------------------------------
+# VOID
+# EfiEnableCache (
+# VOID
+# );
+#------------------------------------------------------------------------------
+ASM_PFX(EfiEnableCache):
+ wbinvd
+ mov %cr0,%rax
+ and $0xffffffff9fffffff,%rax
+ mov %rax,%cr0
+ retq
+
+#------------------------------------------------------------------------------
+# UINTN
+# EfiGetEflags (
+# VOID
+# );
+#------------------------------------------------------------------------------
+ASM_PFX(EfiGetEflags):
+ pushfq
+ pop %rax
+ retq
+
+#------------------------------------------------------------------------------
+# VOID
+# EfiDisableInterrupts (
+# VOID
+# );
+#------------------------------------------------------------------------------
+ASM_PFX(EfiDisableInterrupts):
+ cli
+ ret
+
+#------------------------------------------------------------------------------
+# VOID
+# EfiEnableInterrupts (
+# VOID
+# );
+#------------------------------------------------------------------------------
+ASM_PFX(EfiEnableInterrupts):
+ sti
+ ret
+#------------------------------------------------------------------------------
+# VOID
+# EfiCpuidExt (
+# IN UINT32 RegisterInEax,
+# IN UINT32 CacheLevel,
+# OUT EFI_CPUID_REGISTER *Regs
+# )
+#------------------------------------------------------------------------------
+ASM_PFX(EfiCpuidExt):
+ push %rbx
+ mov %rcx,%rax
+ mov %rdx,%rcx
+ cpuid
+ mov %eax,(%r8)
+ mov %ebx,0x4(%r8)
+ mov %ecx,0x8(%r8)
+ mov %edx,0xc(%r8)
+ pop %rbx
+ retq
diff --git a/BraswellPlatformPkg/Common/Library/CpuIA32Lib/X64/Cpu.asm b/BraswellPlatformPkg/Common/Library/CpuIA32Lib/X64/Cpu.asm new file mode 100644 index 0000000000..a272ad506c --- /dev/null +++ b/BraswellPlatformPkg/Common/Library/CpuIA32Lib/X64/Cpu.asm @@ -0,0 +1,209 @@ +;; @file
+; Assembly code for the x64 resources.
+;
+; Copyright (c) 2004 - 2015, Intel Corporation. All rights reserved.<BR>
+;
+; This program and the accompanying materials
+; are licensed and made available under the terms and conditions of the BSD License
+; which accompanies this distribution. The full text of the license may be found at
+; http://opensource.org/licenses/bsd-license.php.
+;
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+;
+;;
+
+text SEGMENT
+
+
+;------------------------------------------------------------------------------
+; VOID
+; EfiHalt (
+; VOID
+; )
+;------------------------------------------------------------------------------
+EfiHalt PROC PUBLIC
+ hlt
+ ret
+EfiHalt ENDP
+
+
+;------------------------------------------------------------------------------
+; VOID
+; EfiWbinvd (
+; VOID
+; )
+;------------------------------------------------------------------------------
+EfiWbinvd PROC PUBLIC
+ wbinvd
+ ret
+EfiWbinvd ENDP
+
+
+;------------------------------------------------------------------------------
+; VOID
+; EfiInvd (
+; VOID
+; )
+;------------------------------------------------------------------------------
+EfiInvd PROC PUBLIC
+ invd
+ ret
+EfiInvd ENDP
+
+;------------------------------------------------------------------------------
+; VOID
+; EfiCpuid (
+; IN UINT32 RegisterInEax, // rcx
+; OUT EFI_CPUID_REGISTER *Reg OPTIONAL // rdx
+; )
+;------------------------------------------------------------------------------
+EfiCpuid PROC PUBLIC
+ push rbx
+
+ mov r8, rdx ; r8 = *Reg
+ mov rax, rcx ; RegisterInEax
+ cpuid
+ cmp r8, 0
+ je _Exit
+ mov [r8 + 0], eax ; Reg->RegEax
+ mov [r8 + 4], ebx ; Reg->RegEbx
+ mov [r8 + 8], ecx ; Reg->RegEcx
+ mov [r8 + 12], edx ; Reg->RegEdx
+
+_Exit:
+ pop rbx
+ ret
+EfiCpuid ENDP
+
+;------------------------------------------------------------------------------
+; UINT64
+; EfiReadMsr (
+; IN UINT32 Index, // rcx
+; )
+;------------------------------------------------------------------------------
+EfiReadMsr PROC PUBLIC
+ rdmsr
+ sal rdx, 32 ; edx:eax -> rax
+ or rax, rdx ; rax = edx:eax
+ ret
+EfiReadMsr ENDP
+
+;------------------------------------------------------------------------------
+; VOID
+; EfiWriteMsr (
+; IN UINT32 Index, // rcx
+; IN UINT64 Value // rdx
+; )
+;------------------------------------------------------------------------------
+EfiWriteMsr PROC PUBLIC
+ mov rax, rdx ; rdx = Value
+ sar rdx, 32 ; convert rdx to edx upper 32-bits
+ wrmsr ; wrmsr[ecx] result = edx:eax
+ ret
+EfiWriteMsr ENDP
+
+
+;------------------------------------------------------------------------------
+; UINT64
+; EfiReadTsc (
+; VOID
+; );
+;------------------------------------------------------------------------------
+EfiReadTsc PROC PUBLIC
+ rdtsc
+ shl rax, 32
+ shrd rax, rdx, 32
+ ret
+EfiReadTsc ENDP
+
+;------------------------------------------------------------------------------
+; VOID
+; EfiDisableCache (
+; VOID
+; );
+;------------------------------------------------------------------------------
+EfiDisableCache PROC PUBLIC
+; added a check to see if cache is already disabled. If it is, then skip.
+ mov rax, cr0
+ and rax, 060000000h
+ cmp rax, 0
+ jne @f
+ mov rax, cr0
+ or rax, 060000000h
+ mov cr0, rax
+ wbinvd
+@@:
+ ret
+EfiDisableCache ENDP
+
+;------------------------------------------------------------------------------
+; VOID
+; EfiEnableCache (
+; VOID
+; );
+;------------------------------------------------------------------------------
+EfiEnableCache PROC PUBLIC
+ wbinvd
+ mov rax, cr0
+ and rax, 09fffffffh
+ mov cr0, rax
+ ret
+EfiEnableCache ENDP
+
+;------------------------------------------------------------------------------
+; UINTN
+; EfiGetEflags (
+; VOID
+; );
+;------------------------------------------------------------------------------
+EfiGetEflags PROC PUBLIC
+ pushfq
+ pop rax
+ ret
+EfiGetEflags ENDP
+
+;------------------------------------------------------------------------------
+; VOID
+; EfiDisableInterrupts (
+; VOID
+; );
+;------------------------------------------------------------------------------
+EfiDisableInterrupts PROC PUBLIC
+ cli
+ ret
+EfiDisableInterrupts ENDP
+
+;------------------------------------------------------------------------------
+; VOID
+; EfiEnableInterrupts (
+; VOID
+; );
+;------------------------------------------------------------------------------
+EfiEnableInterrupts PROC PUBLIC
+ sti
+ ret
+EfiEnableInterrupts ENDP
+;------------------------------------------------------------------------------
+; VOID
+; EfiCpuidExt (
+; IN UINT32 RegisterInEax,
+; IN UINT32 CacheLevel,
+; OUT EFI_CPUID_REGISTER *Regs
+; )
+;------------------------------------------------------------------------------
+EfiCpuidExt PROC PUBLIC
+ push rbx
+ mov rax, rcx ; rax = RegisterInEax
+ mov rcx, rdx ; rcx = CacheLevel
+
+ cpuid
+ mov [r8 + 0 ], eax ; Reg->RegEax
+ mov [r8 + 4 ], ebx ; Reg->RegEbx
+ mov [r8 + 8 ], ecx ; Reg->RegEcx
+ mov [r8 + 12], edx ; Reg->RegEdx
+
+ pop rbx
+ ret
+EfiCpuidExt ENDP
+END
diff --git a/BraswellPlatformPkg/Common/Library/EfiRegTableLib/EfiRegTableLib.c b/BraswellPlatformPkg/Common/Library/EfiRegTableLib/EfiRegTableLib.c new file mode 100644 index 0000000000..4e94d32832 --- /dev/null +++ b/BraswellPlatformPkg/Common/Library/EfiRegTableLib/EfiRegTableLib.c @@ -0,0 +1,276 @@ +/** @file
+ Lib function for table driven register initialization.
+
+ Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Library/EfiRegTableLib.h>
+#include <Library/S3BootScriptLib.h>
+
+//
+// Local Functions
+//
+
+/**
+ Local worker function to process PCI_WRITE table entries. Performs write and
+ may also call BootScriptSave protocol if indicated in the Entry flags
+
+ @param Entry A pointer to the PCI_WRITE entry to process
+
+ @param PciRootBridgeIo A pointer to the instance of PciRootBridgeIo that is used
+ when processing the entry.
+
+ @retval Nothing.
+
+**/
+STATIC
+VOID
+PciWrite (
+ EFI_REG_TABLE_PCI_WRITE *Entry,
+ EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo
+ )
+{
+ EFI_STATUS Status;
+
+ Status = PciRootBridgeIo->Pci.Write (
+ PciRootBridgeIo,
+ (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) (OPCODE_EXTRA_DATA (Entry->OpCode)),
+ (UINT64) Entry->PciAddress,
+ 1,
+ &Entry->Data
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ if (OPCODE_FLAGS (Entry->OpCode) & OPCODE_FLAG_S3SAVE) {
+ Status = S3BootScriptSavePciCfgWrite (
+ (EFI_BOOT_SCRIPT_WIDTH) (OPCODE_EXTRA_DATA (Entry->OpCode)),
+ (UINT64) Entry->PciAddress,
+ 1,
+ &Entry->Data
+ );
+ ASSERT_EFI_ERROR (Status);
+ }
+}
+
+/**
+ Local worker function to process PCI_READ_MODIFY_WRITE table entries.
+ Performs RMW write and may also call BootScriptSave protocol if indicated in
+ the Entry flags.
+
+ @param Entry A pointer to the PCI_READ_MODIFY_WRITE entry to process.
+
+ @param PciRootBridgeIo A pointer to the instance of PciRootBridgeIo that is used
+ when processing the entry.
+
+ @retval Nothing.
+
+**/
+STATIC
+VOID
+PciReadModifyWrite (
+ EFI_REG_TABLE_PCI_READ_MODIFY_WRITE *Entry,
+ EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo
+ )
+{
+ EFI_STATUS Status;
+ UINT32 TempData;
+
+ Status = PciRootBridgeIo->Pci.Read (
+ PciRootBridgeIo,
+ (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) (OPCODE_EXTRA_DATA (Entry->OpCode)),
+ (UINT64) Entry->PciAddress,
+ 1,
+ &TempData
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ Entry->OrMask &= Entry->AndMask;
+ TempData &= ~Entry->AndMask;
+ TempData |= Entry->OrMask;
+
+ Status = PciRootBridgeIo->Pci.Write (
+ PciRootBridgeIo,
+ (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) (OPCODE_EXTRA_DATA (Entry->OpCode)),
+ (UINT64) Entry->PciAddress,
+ 1,
+ &TempData
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ if (OPCODE_FLAGS (Entry->OpCode) & OPCODE_FLAG_S3SAVE) {
+ Status = S3BootScriptSavePciCfgReadWrite (
+ (EFI_BOOT_SCRIPT_WIDTH) (OPCODE_EXTRA_DATA (Entry->OpCode)),
+ (UINT64) Entry->PciAddress,
+ &Entry->OrMask,
+ &Entry->AndMask
+ );
+ ASSERT_EFI_ERROR (Status);
+ }
+}
+
+/**
+ Local worker function to process MEM_READ_MODIFY_WRITE table entries.
+ Performs RMW write and may also call BootScriptSave protocol if indicated in
+ the Entry flags.
+
+ @param Entry A pointer to the MEM_READ_MODIFY_WRITE entry to process.
+
+ @param PciRootBridgeIo A pointer to the instance of PciRootBridgeIo that is used
+ when processing the entry.
+
+ @retval Nothing.
+
+**/
+STATIC
+VOID
+MemReadModifyWrite (
+ EFI_REG_TABLE_MEM_READ_MODIFY_WRITE *Entry,
+ EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo
+ )
+{
+ EFI_STATUS Status;
+ UINT32 TempData;
+
+ Status = PciRootBridgeIo->Mem.Read (
+ PciRootBridgeIo,
+ (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) (OPCODE_EXTRA_DATA (Entry->OpCode)),
+ (UINT64) Entry->MemAddress,
+ 1,
+ &TempData
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ Entry->OrMask &= Entry->AndMask;
+ TempData &= ~Entry->AndMask;
+ TempData |= Entry->OrMask;
+
+ Status = PciRootBridgeIo->Mem.Write (
+ PciRootBridgeIo,
+ (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) (OPCODE_EXTRA_DATA (Entry->OpCode)),
+ (UINT64) Entry->MemAddress,
+ 1,
+ &TempData
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ if (OPCODE_FLAGS (Entry->OpCode) & OPCODE_FLAG_S3SAVE) {
+ Status = S3BootScriptSaveMemReadWrite (
+ (EFI_BOOT_SCRIPT_WIDTH) (OPCODE_EXTRA_DATA (Entry->OpCode)),
+ Entry->MemAddress,
+ &Entry->OrMask,
+ &Entry->AndMask
+ );
+ ASSERT_EFI_ERROR (Status);
+ }
+}
+
+//
+// Exported functions
+//
+
+/**
+ Processes register table assuming which may contain PCI, IO, MEM, and STALL
+ entries.
+
+ No parameter checking is done so the caller must be careful about omitting
+ values for PciRootBridgeIo or CpuIo parameters. If the regtable does
+ not contain any PCI accesses, it is safe to omit the PciRootBridgeIo (supply
+ NULL). If the regtable does not contain any IO or Mem entries, it is safe to
+ omit the CpuIo (supply NULL).
+
+ The RegTableEntry parameter is not checked, but is required.
+
+ gBS is assumed to have been defined and is used when processing stalls.
+
+ The function processes each entry sequentially until an OP_TERMINATE_TABLE
+ entry is encountered.
+
+ @param RegTableEntry A pointer to the register table to process
+
+ @param PciRootBridgeIo A pointer to the instance of PciRootBridgeIo that is used
+ when processing PCI table entries
+
+ @param CpuIo A pointer to the instance of CpuIo that is used when processing IO and
+ MEM table entries
+
+ @retval Nothing.
+
+**/
+VOID
+ProcessRegTablePci (
+ EFI_REG_TABLE *RegTableEntry,
+ EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo,
+ EFI_CPU_IO_PROTOCOL *CpuIo
+ )
+{
+ while (OPCODE_BASE (RegTableEntry->Generic.OpCode) != OP_TERMINATE_TABLE) {
+ switch (OPCODE_BASE (RegTableEntry->Generic.OpCode)) {
+ case OP_PCI_WRITE:
+ PciWrite ((EFI_REG_TABLE_PCI_WRITE *) RegTableEntry, PciRootBridgeIo);
+ break;
+
+ case OP_PCI_READ_MODIFY_WRITE:
+ PciReadModifyWrite ((EFI_REG_TABLE_PCI_READ_MODIFY_WRITE *) RegTableEntry, PciRootBridgeIo);
+ break;
+
+ case OP_MEM_READ_MODIFY_WRITE:
+ MemReadModifyWrite ((EFI_REG_TABLE_MEM_READ_MODIFY_WRITE *) RegTableEntry, PciRootBridgeIo);
+ break;
+
+ default:
+ DEBUG ((EFI_D_ERROR, "RegTable ERROR: Unknown RegTable OpCode (%x)\n", OPCODE_BASE (RegTableEntry->Generic.OpCode)));
+ ASSERT (0);
+ break;
+ }
+
+ RegTableEntry++;
+ }
+}
+
+/**
+ Processes register table assuming which may contain IO, MEM, and STALL
+ entries, but must NOT contain any PCI entries. Any PCI entries cause an
+ ASSERT in a DEBUG build and are skipped in a free build.
+
+ No parameter checking is done. Both RegTableEntry and CpuIo parameters are
+ required.
+
+ gBS is assumed to have been defined and is used when processing stalls.
+
+ The function processes each entry sequentially until an OP_TERMINATE_TABLE
+ entry is encountered.
+
+ @param RegTableEntry A pointer to the register table to process
+
+ @param CpuIo A pointer to the instance of CpuIo that is used when processing IO and
+ MEM table entries
+
+ @retval Nothing.
+
+**/
+VOID
+ProcessRegTableCpu (
+ EFI_REG_TABLE *RegTableEntry,
+ EFI_CPU_IO_PROTOCOL *CpuIo
+ )
+{
+ while (OPCODE_BASE (RegTableEntry->Generic.OpCode) != OP_TERMINATE_TABLE) {
+ switch (OPCODE_BASE (RegTableEntry->Generic.OpCode)) {
+ default:
+ DEBUG ((EFI_D_ERROR, "RegTable ERROR: Unknown RegTable OpCode (%x)\n", OPCODE_BASE (RegTableEntry->Generic.OpCode)));
+ ASSERT (0);
+ break;
+ }
+
+ RegTableEntry++;
+ }
+}
diff --git a/BraswellPlatformPkg/Common/Library/EfiRegTableLib/EfiRegTableLib.inf b/BraswellPlatformPkg/Common/Library/EfiRegTableLib/EfiRegTableLib.inf new file mode 100644 index 0000000000..24200e78a5 --- /dev/null +++ b/BraswellPlatformPkg/Common/Library/EfiRegTableLib/EfiRegTableLib.inf @@ -0,0 +1,42 @@ +## @file
+# Lib function for table driven register initialization.
+#
+# Implement PCI/MMIO read/write function.
+#
+# Copyright (c) 2013 - 2015, Intel Corporation. All rights reserved.<BR>
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php.
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = EfiRegTableLib
+ FILE_GUID = 98546145-64F1-4d2e-814F-6BF963DB7930
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = EfiRegTableLib
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = IA32 X64 IPF EBC
+#
+
+[Sources]
+ EfiRegTableLib.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ BraswellPlatformPkg/BraswellPlatformPkg.dec
+ IntelFrameworkPkg/IntelFrameworkPkg.dec
+
+[LibraryClasses]
+
diff --git a/BraswellPlatformPkg/Common/Library/FlashDeviceLib/FlashDeviceLib.c b/BraswellPlatformPkg/Common/Library/FlashDeviceLib/FlashDeviceLib.c new file mode 100644 index 0000000000..71791691f3 --- /dev/null +++ b/BraswellPlatformPkg/Common/Library/FlashDeviceLib/FlashDeviceLib.c @@ -0,0 +1,457 @@ +/** @file
+ Lib function for SPI Flash Device
+
+ Copyright (c) 2004 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <PiDxe.h>
+
+#include <Library/FlashDeviceLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiRuntimeServicesTableLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/UefiRuntimeLib.h>
+#include <Protocol/SmmBase2.h>
+#include <Guid/EventGroup.h>
+#include "SpiChipDefinitions.h"
+
+UINTN FlashDeviceBase = FLASH_DEVICE_BASE_ADDRESS;
+
+EFI_SPI_PROTOCOL *mSpiProtocol = NULL;
+
+EFI_STATUS
+SpiFlashErase (
+ UINT8 *BaseAddress,
+ UINTN NumBytes
+ )
+{
+ EFI_STATUS Status = EFI_SUCCESS;
+ UINT32 SectorSize;
+ UINT32 SpiAddress;
+
+ SpiAddress = (UINT32)(UINTN)(BaseAddress) - (UINT32)FlashDeviceBase;
+ SectorSize = SECTOR_SIZE_4KB;
+ while ( (NumBytes > 0) && (NumBytes <= MAX_FWH_SIZE) ) {
+ Status = mSpiProtocol->Execute (
+ mSpiProtocol,
+ SPI_SERASE,
+ SPI_WREN,
+ FALSE,
+ TRUE,
+ FALSE,
+ (UINT32) SpiAddress,
+ 0,
+ NULL,
+ EnumSpiRegionBios
+ );
+ if (EFI_ERROR (Status)) {
+ break;
+ }
+ SpiAddress += SectorSize;
+ NumBytes -= SectorSize;
+ }
+
+ return Status;
+}
+
+EFI_STATUS
+SpiFlashBlockErase (
+ UINT8 *BaseAddress,
+ UINTN NumBytes
+ )
+{
+ EFI_STATUS Status = EFI_SUCCESS;
+ UINT32 SectorSize;
+ UINT32 SpiAddress;
+
+ SpiAddress = (UINT32)(UINTN)(BaseAddress) - (UINT32)FlashDeviceBase;
+ SectorSize = SECTOR_SIZE_64KB;
+ while ( (NumBytes > 0) && (NumBytes <= MAX_FWH_SIZE) ) {
+ Status = mSpiProtocol->Execute (
+ mSpiProtocol,
+ SPI_BERASE,
+ SPI_WREN,
+ FALSE,
+ TRUE,
+ FALSE,
+ (UINT32) SpiAddress,
+ 0,
+ NULL,
+ EnumSpiRegionBios
+ );
+ if (EFI_ERROR (Status)) {
+ break;
+ }
+ SpiAddress += SectorSize;
+ NumBytes -= SectorSize;
+ }
+
+ return Status;
+}
+
+static
+EFI_STATUS
+SpiFlashWrite (
+ UINT8 *DstBufferPtr,
+ UINT8 *Byte,
+ IN UINTN Length
+ )
+{
+ EFI_STATUS Status;
+ UINT32 NumBytes = (UINT32)Length;
+ UINT8* pBuf8 = Byte;
+ UINT32 SpiAddress;
+
+ SpiAddress = (UINT32)(UINTN)(DstBufferPtr) - (UINT32)FlashDeviceBase;
+ Status = mSpiProtocol->Execute (
+ mSpiProtocol,
+ SPI_PROG,
+ SPI_WREN,
+ TRUE,
+ TRUE,
+ TRUE,
+ (UINT32)SpiAddress,
+ NumBytes,
+ pBuf8,
+ EnumSpiRegionBios
+ );
+ return Status;
+}
+
+/**
+ Read the Serial Flash Status Registers.
+
+ @param SpiStatus Pointer to a caller-allocated UINT8. On successful return, it contains the
+ status data read from the Serial Flash Status Register.
+
+ @retval EFI_SUCCESS Operation success, status is returned in SpiStatus.
+ @retval EFI_DEVICE_ERROR The block device is not functioning correctly and the operation failed.
+
+**/
+EFI_STATUS
+ReadStatusRegister (
+ UINT8 *SpiStatus
+ )
+{
+ EFI_STATUS Status;
+
+ Status = mSpiProtocol->Execute (
+ mSpiProtocol,
+ SPI_RDSR,
+ SPI_WREN,
+ TRUE,
+ FALSE,
+ FALSE,
+ 0,
+ 1,
+ SpiStatus,
+ EnumSpiRegionBios
+ );
+ return Status;
+}
+
+EFI_STATUS
+SpiFlashLock (
+ IN UINT8 *BaseAddress,
+ IN UINTN NumBytes,
+ IN BOOLEAN Lock
+ )
+{
+ EFI_STATUS Status;
+ UINT8 SpiData;
+ UINT8 SpiStatus;
+
+ if (Lock) {
+ SpiData = SF_SR_WPE;
+ } else {
+ SpiData = 0;
+ }
+
+ //
+ // Always disable block protection to workaround tool issue.
+ // Feature may be re-enabled in a future bios.
+ //
+ SpiData = 0;
+ Status = mSpiProtocol->Execute (
+ mSpiProtocol,
+ SPI_WRSR,
+ SPI_EWSR,
+ TRUE,
+ TRUE,
+ TRUE,
+ 0,
+ 1,
+ &SpiData,
+ EnumSpiRegionBios
+ );
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ Status = ReadStatusRegister (&SpiStatus);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ if ((SpiStatus & SpiData) != SpiData) {
+ Status = EFI_DEVICE_ERROR;
+ }
+
+ return Status;
+}
+
+/**
+ Read NumBytes bytes of data from the address specified by
+ PAddress into Buffer.
+
+ @param[in] PAddress The starting physical address of the read.
+ @param[in,out] NumBytes On input, the number of bytes to read. On output, the number
+ of bytes actually read.
+ @param[out] Buffer The destination data buffer for the read.
+
+ @retval EFI_SUCCESS. Opertion is successful.
+ @retval EFI_DEVICE_ERROR If there is any device errors.
+
+**/
+EFI_STATUS
+EFIAPI
+LibFvbFlashDeviceRead (
+ IN UINTN PAddress,
+ IN OUT UINTN *NumBytes,
+ OUT UINT8 *Buffer
+ )
+{
+ CopyMem(Buffer, (VOID*)PAddress, *NumBytes);
+ return EFI_SUCCESS;
+}
+
+/**
+ Write NumBytes bytes of data from Buffer to the address specified by
+ PAddresss.
+
+ @param[in] PAddress The starting physical address of the write.
+ @param[in,out] NumBytes On input, the number of bytes to write. On output,
+ the actual number of bytes written.
+ @param[in] Buffer The source data buffer for the write.
+
+ @retval EFI_SUCCESS. Opertion is successful.
+ @retval EFI_DEVICE_ERROR If there is any device errors.
+
+**/
+EFI_STATUS
+EFIAPI
+LibFvbFlashDeviceWrite (
+ IN UINTN PAddress,
+ IN OUT UINTN *NumBytes,
+ IN UINT8 *Buffer
+ )
+{
+EFI_STATUS Status;
+ Status = SpiFlashWrite((UINT8 *)PAddress, Buffer, *NumBytes);
+ return Status;
+}
+
+/**
+ Erase the block staring at PAddress.
+
+ @param[in] PAddress The starting physical address of the block to be erased.
+ This library assume that caller garantee that the PAddress
+ is at the starting address of this block.
+ @param[in] LbaLength The length of the logical block to be erased.
+
+ @retval EFI_SUCCESS. Opertion is successful.
+ @retval EFI_DEVICE_ERROR If there is any device errors.
+
+**/
+EFI_STATUS
+EFIAPI
+LibFvbFlashDeviceBlockErase (
+ IN UINTN PAddress,
+ IN UINTN LbaLength
+ )
+{
+ EFI_STATUS Status;
+ Status = SpiFlashBlockErase((UINT8 *)PAddress, LbaLength);
+
+ return Status;
+}
+
+/**
+ Lock or unlock the block staring at PAddress.
+
+ @param[in] PAddress The starting physical address of region to be (un)locked.
+ @param[in] LbaLength The length of the logical block to be erased.
+ @param[in] Lock TRUE to lock. FALSE to unlock.
+
+ @retval EFI_SUCCESS. Opertion is successful.
+ @retval EFI_DEVICE_ERROR If there is any device errors.
+
+**/
+EFI_STATUS
+EFIAPI
+LibFvbFlashDeviceBlockLock (
+ IN UINTN PAddress,
+ IN UINTN LbaLength,
+ IN BOOLEAN Lock
+ )
+{
+ EFI_STATUS Status;
+
+ Status = SpiFlashLock((UINT8*)PAddress, LbaLength, Lock);
+ return Status;
+}
+
+VOID
+EFIAPI
+LibFvbFlashDeviceVirtualAddressChangeNotifyEvent (
+ IN EFI_EVENT Event,
+ IN VOID *Context
+ )
+{
+ gRT->ConvertPointer (0, (VOID **) &mSpiProtocol);
+ gRT->ConvertPointer (0, (VOID **) &FlashDeviceBase);
+}
+
+/**
+ The library constructuor.
+
+ The function does the necessary initialization work for this library
+ instance. Please put all initialization works in it.
+
+ @param[in] ImageHandle The firmware allocated handle for the UEFI image.
+ @param[in] SystemTable A pointer to the EFI system table.
+
+ @retval EFI_SUCCESS The function always return EFI_SUCCESS for now.
+ It will ASSERT on error for debug version.
+ @retval EFI_ERROR Please reference LocateProtocol for error code details.
+
+**/
+EFI_STATUS
+EFIAPI
+LibFvbFlashDeviceSupportInit (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+ EFI_EVENT Event;
+ UINT8 SfId[3];
+ UINT8 FlashIndex;
+ UINT8 SpiReadError;
+ UINT8 SpiNotMatchError;
+ EFI_SMM_BASE2_PROTOCOL *SmmBase;
+ BOOLEAN InSmm;
+
+ SpiReadError = 0x00;
+ SpiNotMatchError = 0x00;
+
+ InSmm = FALSE;
+ Status = gBS->LocateProtocol (
+ &gEfiSmmBase2ProtocolGuid,
+ NULL,
+ (void **)&SmmBase
+ );
+ if (!EFI_ERROR(Status)) {
+ Status = SmmBase->InSmm(SmmBase, &InSmm);
+ if (EFI_ERROR(Status)) {
+ InSmm = FALSE;
+ }
+ }
+
+ if (!InSmm) {
+ Status = gBS->LocateProtocol (
+ &gEfiSpiProtocolGuid,
+ NULL,
+ (VOID **)&mSpiProtocol
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ Status = gBS->CreateEventEx (
+ EVT_NOTIFY_SIGNAL,
+ TPL_NOTIFY,
+ LibFvbFlashDeviceVirtualAddressChangeNotifyEvent,
+ NULL,
+ &gEfiEventVirtualAddressChangeGuid,
+ &Event
+ );
+ ASSERT_EFI_ERROR (Status);
+ } else {
+ Status = gBS->LocateProtocol (
+ &gEfiSmmSpiProtocolGuid,
+ NULL,
+ (VOID **)&mSpiProtocol
+ );
+ ASSERT_EFI_ERROR (Status);
+ }
+
+ for (FlashIndex = EnumSpiFlashW25Q64; FlashIndex < EnumSpiFlashMax; FlashIndex++) {
+ Status = mSpiProtocol->Init (mSpiProtocol, &(mInitTable[FlashIndex]));
+ if (!EFI_ERROR (Status)) {
+ //
+ // Read Vendor/Device IDs to check if the driver supports the Serial Flash device.
+ //
+ Status = mSpiProtocol->Execute (
+ mSpiProtocol,
+ SPI_READ_ID,
+ SPI_WREN,
+ TRUE,
+ FALSE,
+ FALSE,
+ 0,
+ 3,
+ SfId,
+ EnumSpiRegionAll
+ );
+ if (!EFI_ERROR (Status)) {
+ if ((SfId[0] == mInitTable[FlashIndex].VendorId) &&
+ (SfId[1] == mInitTable[FlashIndex].DeviceId0) &&
+ (SfId[2] == mInitTable[FlashIndex].DeviceId1)) {
+ //
+ // Found a matching SPI device, FlashIndex now contains flash device.
+ //
+ DEBUG ((EFI_D_ERROR, "OK - Found SPI Flash Type in SPI Flash Driver, Device Type ID 0 = 0x%02x!\n", mInitTable[FlashIndex].DeviceId0));
+ DEBUG ((EFI_D_ERROR, "Device Type ID 1 = 0x%02x!\n", mInitTable[FlashIndex].DeviceId1));
+
+ if (mInitTable[FlashIndex].BiosStartOffset == (UINTN) (-1)) {
+ DEBUG ((EFI_D_ERROR, "ERROR - The size of BIOS image is bigger than SPI Flash device!\n"));
+ CpuDeadLoop ();
+ }
+ break;
+ } else {
+ SpiNotMatchError++;
+ }
+ } else {
+ SpiReadError++;
+ }
+ }
+ }
+
+ DEBUG ((EFI_D_ERROR, "SPI flash chip VID = 0x%X, DID0 = 0x%X, DID1 = 0x%X\n", SfId[0], SfId[1], SfId[2]));
+
+ if (FlashIndex < EnumSpiFlashMax) {
+ return EFI_SUCCESS;
+ } else {
+ if (SpiReadError != 0) {
+ DEBUG ((EFI_D_ERROR, "ERROR - SPI Read ID execution failed! Error Count = %d\n", SpiReadError));
+ }
+ else {
+ if (SpiNotMatchError != 0) {
+ DEBUG ((EFI_D_ERROR, "ERROR - No supported SPI flash chip found! Error Count = %d\n", SpiNotMatchError));
+ DEBUG ((EFI_D_ERROR, "SPI flash chip VID = 0x%X, DID0 = 0x%X, DID1 = 0x%X\n", SfId[0], SfId[1], SfId[2]));
+ }
+ }
+ return EFI_UNSUPPORTED;
+ }
+}
+
diff --git a/BraswellPlatformPkg/Common/Library/FlashDeviceLib/FlashDeviceLib.inf b/BraswellPlatformPkg/Common/Library/FlashDeviceLib/FlashDeviceLib.inf new file mode 100644 index 0000000000..04aade44a6 --- /dev/null +++ b/BraswellPlatformPkg/Common/Library/FlashDeviceLib/FlashDeviceLib.inf @@ -0,0 +1,51 @@ +## @file
+# Provides flash operation routines
+#
+# This library read/write/lock/erase APIs for flash operation.
+#
+# Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.<BR>
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php.
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = FlashDeviceLib
+ FILE_GUID = E38A1C3C-928C-4bf7-B6C1-7F0EF163FAA5
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = FlashDeviceLib | DXE_SMM_DRIVER DXE_RUNTIME_DRIVER
+ CONSTRUCTOR = LibFvbFlashDeviceSupportInit
+
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = IA32 X64
+#
+
+[Sources]
+ FlashDeviceLib.c
+
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ BraswellPlatformPkg/BraswellPlatformPkg.dec
+ ChvRefCodePkg/ChvRefCodePkg.dec
+
+[LibraryClasses]
+ DebugLib
+
+[Protocols]
+ gEfiSpiProtocolGuid ## SOMETIMES_CONSUMES
+ gEfiSmmSpi2ProtocolGuid ## SOMETIMES_CONSUMES
+ gEfiSmmBase2ProtocolGuid ## CONSUMES
+
diff --git a/BraswellPlatformPkg/Common/Library/FlashDeviceLib/SpiChipDefinitions.h b/BraswellPlatformPkg/Common/Library/FlashDeviceLib/SpiChipDefinitions.h new file mode 100644 index 0000000000..0d41ccca8a --- /dev/null +++ b/BraswellPlatformPkg/Common/Library/FlashDeviceLib/SpiChipDefinitions.h @@ -0,0 +1,840 @@ +/** @file
+ The Definitions of SPI Chip type.
+
+ Copyright (c) 2004 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Library/SpiFlash.h>
+
+#define FLASH_SIZE 0x200000
+#define FLASH_DEVICE_BASE_ADDRESS (0xFFFFFFFF-FLASH_SIZE+1)
+
+//
+// Serial Flash device initialization data table provided to the
+// Intel(R) SPI Host Controller Compatibility Interface.
+//
+SPI_INIT_TABLE mInitTable[] = {
+ {
+ SF_VENDOR_ID_WINBOND, // VendorId
+ SF_DEVICE_ID0_W25QXX, // DeviceId 0
+ SF_DEVICE_ID1_W25Q64, // DeviceId 1
+ {
+ SF_INST_WREN, // Prefix Opcode 0: Write Enable
+ SF_INST_EWSR // Prefix Opcode 1: Enable Write Status Register
+ },
+ {
+ {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID
+ {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData }, // Opcode 1: Read
+ {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register
+ {EnumSpiOpcodeRead, SF_INST_SFDP, EnumSpiCycle50MHz, EnumSpiOperationDiscoveryParameters}, // Opcode 3: Serial Flash Discovery Parameters
+ {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)
+ {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (64KB
+ {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program
+ {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register
+ },
+ //
+ // The offset of the start of the BIOS image in flash. This value is platform specific
+ // and depends on the system flash map. If BIOS size is bigger than flash return -1
+ //
+ ((WINBOND_W25Q64_SIZE >= FLASH_SIZE) ? WINBOND_W25Q64_SIZE - FLASH_SIZE : (UINTN) (-1)),
+ //
+ // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map
+ //
+ FLASH_SIZE
+ },
+ {
+ SF_VENDOR_ID_ATMEL, // VendorId
+ SF_DEVICE_ID0_AT25DF321A, // DeviceId 0
+ SF_DEVICE_ID1_AT25DF321A, // DeviceId 1
+ {
+ SF_INST_WREN, // Prefix Opcode 0: Write Enable
+ SF_INST_WREN // Prefix Opcode 1: Write Enable (this part doesn't support EWSR)
+ },
+ {
+ {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID
+ {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData }, // Opcode 1: Read
+ {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register
+ {EnumSpiOpcodeWriteNoAddr, SF_INST_WRDI, EnumSpiCycle50MHz, EnumSpiOperationWriteDisable }, // Opcode 3: Write Disable
+ {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)
+ {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (32KB)
+ {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program
+ {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register
+ },
+ //
+ // The offset of the start of the BIOS image in flash. This value is platform specific
+ // and depends on the system flash map. If BIOS size is bigger than flash return -1
+ //
+ ((ATMEL_AT25DF321A_SIZE >= FLASH_SIZE) ? ATMEL_AT25DF321A_SIZE - FLASH_SIZE : (UINTN) (-1)),
+ //
+ // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map
+ //
+ FLASH_SIZE
+ },
+
+ {
+ SF_VENDOR_ID_NUMONYX, // VendorId
+ SF_DEVICE_ID0_N25QXXX, // DeviceId 0
+ SF_DEVICE_ID1_N25Q064, // DeviceId 1
+ {
+ SF_INST_WREN, // Prefix Opcode 0: Write Enable
+ SF_INST_WREN // Prefix Opcode 1: Write Enable (this part doesn't support EWSR)
+ },
+ {
+ {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID
+ {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle33MHz, EnumSpiOperationReadData }, // Opcode 1: Read
+ {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register
+ {EnumSpiOpcodeWriteNoAddr, SF_INST_WRDI, EnumSpiCycle50MHz, EnumSpiOperationWriteDisable }, // Opcode 3: Write Disable
+ {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)
+ {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (64KB
+ {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program
+ {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register
+ },
+ //
+ // The offset of the start of the BIOS image in flash. This value is platform specific
+ // and depends on the system flash map. If BIOS size is bigger than flash return -1
+ //
+ ((NUMONYX_N25Q064_SIZE >= FLASH_SIZE) ? NUMONYX_N25Q064_SIZE - FLASH_SIZE : (UINTN) (-1)),
+ //
+ // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map
+ //
+ FLASH_SIZE
+ },
+
+ {
+ SF_VENDOR_ID_MICRON, // VendorId
+ SF_DEVICE_ID0_N25WXXX // DeviceId 0
+ SF_DEVICE_ID1_N25W064, // DeviceId 1
+ {
+ SF_INST_WREN, // Prefix Opcode 0: Write Enable
+ SF_INST_WREN // Prefix Opcode 1: Write Enable (this part doesn't support EWSR)
+ },
+ {
+ {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID
+ {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle33MHz, EnumSpiOperationReadData }, // Opcode 1: Read
+ {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register
+ {EnumSpiOpcodeWriteNoAddr, SF_INST_WRDI, EnumSpiCycle50MHz, EnumSpiOperationWriteDisable }, // Opcode 3: Write Disable
+ {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)
+ {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (64KB
+ {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program
+ {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register
+ },
+ //
+ // The offset of the start of the BIOS image in flash. This value is platform specific
+ // and depends on the system flash map. If BIOS size is bigger than flash return -1
+ //
+ ((MICRON_N25W064_SIZE >= FLASH_SIZE) ? MICRON_N25W064_SIZE - FLASH_SIZE : (UINTN) (-1)),
+ //
+ // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map
+ //
+ FLASH_SIZE
+ },
+ {
+ SF_VENDOR_ID_ATMEL, // VendorId
+ SF_DEVICE_ID0_AT26DF321, // DeviceId 0
+ SF_DEVICE_ID1_AT26DF321, // DeviceId 1
+ {
+ SF_INST_WREN, // Prefix Opcode 0: Write Enable
+ SF_INST_WREN // Prefix Opcode 1: Write Enable (this part doesn't support EWSR)
+ },
+ {
+ {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID
+ {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData }, // Opcode 1: Read
+ {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register
+ {EnumSpiOpcodeWriteNoAddr, SF_INST_WRDI, EnumSpiCycle50MHz, EnumSpiOperationWriteDisable }, // Opcode 3: Write Disable
+ {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)
+ {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (32KB)
+ {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program
+ {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register
+ },
+ //
+ // The offset of the start of the BIOS image in flash. This value is platform specific
+ // and depends on the system flash map. If BIOS size is bigger than flash return -1
+ //
+ ((ATMEL_AT26DF321_SIZE >= FLASH_SIZE) ? ATMEL_AT26DF321_SIZE - FLASH_SIZE : (UINTN) (-1)),
+ //
+ // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map
+ //
+ FLASH_SIZE
+ },
+ {
+ SF_VENDOR_ID_ATMEL, // VendorId
+ SF_DEVICE_ID0_AT25DF641, // DeviceId 0
+ SF_DEVICE_ID1_AT25DF641, // DeviceId 1
+ {
+ SF_INST_WREN, // Prefix Opcode 0: Write Enable
+ SF_INST_WREN // Prefix Opcode 1: Write Enable (this part doesn't support EWSR)
+ },
+ {
+ {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID
+ {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData }, // Opcode 1: Read
+ {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register
+ {EnumSpiOpcodeWriteNoAddr, SF_INST_WRDI, EnumSpiCycle50MHz, EnumSpiOperationWriteDisable }, // Opcode 3: Write Disable
+ {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)
+ {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (32KB)
+ {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program
+ {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register
+ },
+ //
+ // The offset of the start of the BIOS image in flash. This value is platform specific
+ // and depends on the system flash map. If BIOS size is bigger than flash return -1
+ //
+ ((ATMEL_AT25DF641_SIZE >= FLASH_SIZE) ? ATMEL_AT25DF641_SIZE - FLASH_SIZE : (UINTN) (-1)),
+ //
+ // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map
+ //
+ FLASH_SIZE
+ },
+ {
+ SF_VENDOR_ID_WINBOND, // VendorId
+ SF_DEVICE_ID0_W25QXX, // DeviceId 0
+ SF_DEVICE_ID1_W25Q16, // DeviceId 1
+ {
+ SF_INST_WREN, // Prefix Opcode 0: Write Enable
+ SF_INST_EWSR // Prefix Opcode 1: Enable Write Status Register
+ },
+ {
+ {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID
+ {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData }, // Opcode 1: Read
+ {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register
+ {EnumSpiOpcodeRead, SF_INST_SFDP, EnumSpiCycle50MHz, EnumSpiOperationDiscoveryParameters}, // Opcode 3: Serial Flash Discovery Parameters
+ {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)
+ {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (64KB
+ {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program
+ {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register
+ },
+ //
+ // The offset of the start of the BIOS image in flash. This value is platform specific
+ // and depends on the system flash map. If BIOS size is bigger than flash return -1
+ //
+ ((WINBOND_W25Q16_SIZE >= FLASH_SIZE) ? WINBOND_W25Q16_SIZE - FLASH_SIZE : (UINTN) (-1)),
+ //
+ // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map
+ //
+ FLASH_SIZE
+ },
+ {
+ SF_VENDOR_ID_WINBOND, // VendorId
+ SF_DEVICE_ID0_W25QXX, // DeviceId 0
+ SF_DEVICE_ID1_W25Q32, // DeviceId 1
+ {
+ SF_INST_WREN, // Prefix Opcode 0: Write Enable
+ SF_INST_EWSR // Prefix Opcode 1: Enable Write Status Register
+ },
+ {
+ {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID
+ {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData }, // Opcode 1: Read
+ {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register
+ {EnumSpiOpcodeRead, SF_INST_SFDP, EnumSpiCycle50MHz, EnumSpiOperationDiscoveryParameters}, // Opcode 3: Serial Flash Discovery Parameters
+ {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)
+ {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (64KB
+ {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program
+ {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register
+ },
+ //
+ // The offset of the start of the BIOS image in flash. This value is platform specific
+ // and depends on the system flash map. If BIOS size is bigger than flash return -1
+ //
+ ((WINBOND_W25Q32_SIZE >= FLASH_SIZE) ? WINBOND_W25Q32_SIZE - FLASH_SIZE : (UINTN) (-1)),
+ //
+ // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map
+ //
+ FLASH_SIZE
+ },
+ {
+ SF_VENDOR_ID_WINBOND, // VendorId
+ SF_DEVICE_ID0_W25XXX, // DeviceId 0
+ SF_DEVICE_ID1_W25X32, // DeviceId 1
+ {
+ SF_INST_WREN, // Prefix Opcode 0: Write Enable
+ SF_INST_EWSR // Prefix Opcode 1: Enable Write Status Register
+ },
+ {
+ {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID
+ {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData }, // Opcode 1: Read
+ {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register
+ {EnumSpiOpcodeRead, SF_INST_SFDP, EnumSpiCycle50MHz, EnumSpiOperationDiscoveryParameters}, // Opcode 3: Serial Flash Discovery Parameters
+ {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)
+ {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (64KB
+ {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program
+ {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register
+ },
+ //
+ // The offset of the start of the BIOS image in flash. This value is platform specific
+ // and depends on the system flash map. If BIOS size is bigger than flash return -1
+ //
+ ((WINBOND_W25X32_SIZE >= FLASH_SIZE) ? WINBOND_W25X32_SIZE - FLASH_SIZE : (UINTN) (-1)),
+ //
+ // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map
+ //
+ FLASH_SIZE
+ },
+ {
+ SF_VENDOR_ID_WINBOND, // VendorId
+ SF_DEVICE_ID0_W25XXX, // DeviceId 0
+ SF_DEVICE_ID1_W25X64, // DeviceId 1
+ {
+ SF_INST_WREN, // Prefix Opcode 0: Write Enable
+ SF_INST_EWSR // Prefix Opcode 1: Enable Write Status Register
+ },
+ {
+ {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID
+ {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData }, // Opcode 1: Read
+ {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register
+ {EnumSpiOpcodeRead, SF_INST_SFDP, EnumSpiCycle50MHz, EnumSpiOperationDiscoveryParameters}, // Opcode 3: Serial Flash Discovery Parameters
+ {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)
+ {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (64KB
+ {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program
+ {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register
+ },
+ //
+ // The offset of the start of the BIOS image in flash. This value is platform specific
+ // and depends on the system flash map. If BIOS size is bigger than flash return -1
+ //
+ ((WINBOND_W25X64_SIZE >= FLASH_SIZE) ? WINBOND_W25X64_SIZE - FLASH_SIZE : (UINTN) (-1)),
+ //
+ // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map
+ //
+ FLASH_SIZE
+ },
+ {
+ SF_VENDOR_ID_WINBOND, // VendorId
+ SF_DEVICE_ID0_W25QXX, // DeviceId 0
+ SF_DEVICE_ID1_W25Q128, // DeviceId 1
+ {
+ SF_INST_WREN, // Prefix Opcode 0: Write Enable
+ SF_INST_EWSR // Prefix Opcode 1: Enable Write Status Register
+ },
+ {
+ {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID
+ {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData }, // Opcode 1: Read
+ {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register
+ {EnumSpiOpcodeRead, SF_INST_SFDP, EnumSpiCycle50MHz, EnumSpiOperationDiscoveryParameters}, // Opcode 3: Serial Flash Discovery Parameters
+ {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)
+ {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (64KB
+ {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program
+ {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register
+ },
+ //
+ // The offset of the start of the BIOS image in flash. This value is platform specific
+ // and depends on the system flash map. If BIOS size is bigger than flash return -1
+ //
+ ((WINBOND_W25Q128_SIZE >= FLASH_SIZE) ? WINBOND_W25Q128_SIZE - FLASH_SIZE : (UINTN) (-1)),
+ //
+ // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map
+ //
+ FLASH_SIZE
+ },
+ {
+ SF_VENDOR_ID_MACRONIX, // VendorId
+ SF_DEVICE_ID0_MX25LXX, // DeviceId 0
+ SF_DEVICE_ID1_MX25L16, // DeviceId 1
+ {
+ SF_INST_WREN, // Prefix Opcode 0: Write Enable
+ SF_INST_EWSR // Prefix Opcode 1: Write Enable (this part doesn't support EWSR)
+ },
+ {
+ {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID
+ {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle33MHz, EnumSpiOperationReadData }, // Opcode 1: Read
+ {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register
+ {EnumSpiOpcodeRead, SF_INST_SFDP, EnumSpiCycle50MHz, EnumSpiOperationDiscoveryParameters}, // Opcode 3: Serial Flash Discovery Parameters
+ {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)
+ {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (64KB
+ {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program
+ {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register
+ },
+ //
+ // The offset of the start of the BIOS image in flash. This value is platform specific
+ // and depends on the system flash map. If BIOS size is bigger than flash return -1
+ //
+ ((MACRONIX_MX25L16_SIZE >= FLASH_SIZE) ? MACRONIX_MX25L16_SIZE - FLASH_SIZE : (UINTN) (-1)),
+ //
+ // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map
+ //
+ FLASH_SIZE
+ },
+ {
+ SF_VENDOR_ID_MACRONIX, // VendorId
+ SF_DEVICE_ID0_MX25LXX, // DeviceId 0
+ SF_DEVICE_ID1_MX25L32, // DeviceId 1
+ {
+ SF_INST_WREN, // Prefix Opcode 0: Write Enable
+ SF_INST_EWSR // Prefix Opcode 1: Write Enable (this part doesn't support EWSR)
+ },
+ {
+ {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID
+ {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle33MHz, EnumSpiOperationReadData }, // Opcode 1: Read
+ {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register
+ {EnumSpiOpcodeRead, SF_INST_SFDP, EnumSpiCycle50MHz, EnumSpiOperationDiscoveryParameters}, // Opcode 3: Serial Flash Discovery Parameters
+ {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)
+ {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (64KB
+ {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program
+ {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register
+ },
+ //
+ // The offset of the start of the BIOS image in flash. This value is platform specific
+ // and depends on the system flash map. If BIOS size is bigger than flash return -1
+ //
+ ((MACRONIX_MX25L32_SIZE >= FLASH_SIZE) ? MACRONIX_MX25L32_SIZE - FLASH_SIZE : (UINTN) (-1)),
+ //
+ // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map
+ //
+ FLASH_SIZE
+ },
+ {
+ SF_VENDOR_ID_MACRONIX, // VendorId
+ SF_DEVICE_ID0_MX25LXX, // DeviceId 0
+ SF_DEVICE_ID1_MX25L64, // DeviceId 1
+ {
+ SF_INST_WREN, // Prefix Opcode 0: Write Enable
+ SF_INST_EWSR // Prefix Opcode 1: Write Enable (this part doesn't support EWSR)
+ },
+ {
+ {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID
+ {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle33MHz, EnumSpiOperationReadData }, // Opcode 1: Read
+ {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register
+ {EnumSpiOpcodeRead, SF_INST_SFDP, EnumSpiCycle50MHz, EnumSpiOperationDiscoveryParameters}, // Opcode 3: Serial Flash Discovery Parameters
+ {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)
+ {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (64KB
+ {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program
+ {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register
+ },
+ //
+ // The offset of the start of the BIOS image in flash. This value is platform specific
+ // and depends on the system flash map. If BIOS size is bigger than flash return -1
+ //
+ ((MACRONIX_MX25L64_SIZE >= FLASH_SIZE) ? MACRONIX_MX25L64_SIZE - FLASH_SIZE : (UINTN) (-1)),
+ //
+ // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map
+ //
+ FLASH_SIZE
+ },
+ {
+ SF_VENDOR_ID_MACRONIX, // VendorId
+ SF_DEVICE_ID0_MX25LXX, // DeviceId 0
+ SF_DEVICE_ID1_MX25L128, // DeviceId 1
+ {
+ SF_INST_WREN, // Prefix Opcode 0: Write Enable
+ SF_INST_EWSR // Prefix Opcode 1: Write Enable (this part doesn't support EWSR)
+ },
+ {
+ {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID
+ {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle33MHz, EnumSpiOperationReadData }, // Opcode 1: Read
+ {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register
+ {EnumSpiOpcodeRead, SF_INST_SFDP, EnumSpiCycle50MHz, EnumSpiOperationDiscoveryParameters}, // Opcode 3: Serial Flash Discovery Parameters
+ {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)
+ {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (64KB
+ {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program
+ {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register
+ },
+ //
+ // The offset of the start of the BIOS image in flash. This value is platform specific
+ // and depends on the system flash map. If BIOS size is bigger than flash return -1
+ //
+ ((MACRONIX_MX25L128_SIZE >= FLASH_SIZE) ? MACRONIX_MX25L128_SIZE - FLASH_SIZE : (UINTN) (-1)),
+ //
+ // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map
+ //
+ FLASH_SIZE
+ },
+ {
+ SF_VENDOR_ID_MACRONIX, // VendorId
+ SF_DEVICE_ID0_MX25UXX, // DeviceId 0
+ SF_DEVICE_ID1_MX25U6435F, // DeviceId 1
+ {
+ SF_INST_WREN, // Prefix Opcode 0: Write Enable
+ SF_INST_EWSR // Prefix Opcode 1: Write Enable (this part doesn't support EWSR)
+ },
+ {
+ {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID
+ {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle33MHz, EnumSpiOperationReadData }, // Opcode 1: Read
+ {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register
+ {EnumSpiOpcodeRead, SF_INST_SFDP, EnumSpiCycle50MHz, EnumSpiOperationDiscoveryParameters}, // Opcode 3: Serial Flash Discovery Parameters
+ {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)
+ {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (64KB
+ {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program
+ {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register
+ },
+ //
+ // The offset of the start of the BIOS image in flash. This value is platform specific
+ // and depends on the system flash map. If BIOS size is bigger than flash return -1
+ //
+ ((MACRONIX_MX25U64_SIZE >= FLASH_SIZE) ? MACRONIX_MX25U64_SIZE - FLASH_SIZE : (UINTN) (-1)),
+ //
+ // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map
+ //
+ FLASH_SIZE
+ },
+ {
+ SF_VENDOR_ID_SST, // VendorId
+ SF_DEVICE_ID0_SST25VF0XXX,// DeviceId 0
+ SF_DEVICE_ID1_SST25VF016B,// DeviceId 1
+ {
+ SF_INST_WREN, // Prefix Opcode 0: Write Enable
+ SF_INST_EWSR // Prefix Opcode 1: Enable Write Status Register
+ },
+ {
+ {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID
+ {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle20MHz, EnumSpiOperationReadData }, // Opcode 1: Read
+ {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register
+ {EnumSpiOpcodeWriteNoAddr, SF_INST_WRDI, EnumSpiCycle50MHz, EnumSpiOperationWriteDisable }, // Opcode 3: Write Disable
+ {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)
+ {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (32KB)
+ {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program
+ {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register
+ },
+ //
+ // The offset of the start of the BIOS image in flash. This value is platform specific
+ // and depends on the system flash map. If BIOS size is bigger than flash return -1
+ //
+ ((SST_SST25VF016B_SIZE >= FLASH_SIZE) ? SST_SST25VF016B_SIZE - FLASH_SIZE : (UINTN) (-1)),
+ //
+ // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map
+ //
+ FLASH_SIZE
+ },
+ {
+ SF_VENDOR_ID_SST, // VendorId
+ SF_DEVICE_ID0_SST25VF0XXX,// DeviceId 0
+ SF_DEVICE_ID1_SST25VF064C,// DeviceId 1
+ {
+ SF_INST_WREN, // Prefix Opcode 0: Write Enable
+ SF_INST_EWSR // Prefix Opcode 1: Enable Write Status Register
+ },
+ {
+ {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID
+ {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle20MHz, EnumSpiOperationReadData }, // Opcode 1: Read
+ {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register
+ {EnumSpiOpcodeWriteNoAddr, SF_INST_WRDI, EnumSpiCycle50MHz, EnumSpiOperationWriteDisable }, // Opcode 3: Write Disable
+ {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)
+ {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (32KB)
+ {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program
+ {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register
+ },
+ //
+ // The offset of the start of the BIOS image in flash. This value is platform specific
+ // and depends on the system flash map. If BIOS size is bigger than flash return -1
+ //
+ ((SST_SST25VF064C_SIZE >= FLASH_SIZE) ? SST_SST25VF064C_SIZE - FLASH_SIZE : (UINTN) (-1)),
+ //
+ // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map
+ //
+ FLASH_SIZE
+ },
+ {
+ SF_VENDOR_ID_NUMONYX, // VendorId
+ SF_DEVICE_ID0_N25Q064, // DeviceId 0
+ SF_DEVICE_ID1_N25Q064, // DeviceId 1
+ {
+ SF_INST_WREN, // Prefix Opcode 0: Write Enable
+ SF_INST_WREN // Prefix Opcode 1: Write Enable (this part doesn't support EWSR)
+ },
+ {
+ {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID
+ {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle33MHz, EnumSpiOperationReadData }, // Opcode 1: Read
+ {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register
+ {EnumSpiOpcodeWriteNoAddr, SF_INST_WRDI, EnumSpiCycle50MHz, EnumSpiOperationWriteDisable }, // Opcode 3: Write Disable
+ {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)
+ {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (64KB
+ {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program
+ {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register
+ },
+ //
+ // The offset of the start of the BIOS image in flash. This value is platform specific
+ // and depends on the system flash map. If BIOS size is bigger than flash return -1
+ //
+ ((NUMONYX_N25Q064_SIZE >= FLASH_SIZE) ? NUMONYX_N25Q064_SIZE - FLASH_SIZE : (UINTN) (-1)),
+ //
+ // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map
+ //
+ FLASH_SIZE
+ },
+ {
+ SF_VENDOR_ID_NUMONYX, // VendorId
+ SF_DEVICE_ID0_M25PXXX, // DeviceId 0
+ SF_DEVICE_ID1_M25PX16, // DeviceId 1
+ {
+ SF_INST_WREN, // Prefix Opcode 0: Write Enable
+ SF_INST_WREN // Prefix Opcode 1: Write Enable (this part doesn't support EWSR)
+ },
+ {
+ {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID
+ {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle33MHz, EnumSpiOperationReadData }, // Opcode 1: Read
+ {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register
+ {EnumSpiOpcodeWriteNoAddr, SF_INST_WRDI, EnumSpiCycle50MHz, EnumSpiOperationWriteDisable }, // Opcode 3: Write Disable
+ {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)
+ {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (64KB
+ {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program
+ {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register
+ },
+ //
+ // The offset of the start of the BIOS image in flash. This value is platform specific
+ // and depends on the system flash map. If BIOS size is bigger than flash return -1
+ //
+ ((NUMONYX_M25PX16_SIZE >= FLASH_SIZE) ? NUMONYX_M25PX16_SIZE - FLASH_SIZE : (UINTN) (-1)),
+ //
+ // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map
+ //
+ FLASH_SIZE
+ },
+ {
+ SF_VENDOR_ID_NUMONYX, // VendorId
+ SF_DEVICE_ID0_N25QXXX, // DeviceId 0
+ SF_DEVICE_ID1_N25Q032, // DeviceId 1
+ {
+ SF_INST_WREN, // Prefix Opcode 0: Write Enable
+ SF_INST_WREN // Prefix Opcode 1: Write Enable (this part doesn't support EWSR)
+ },
+ {
+ {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID
+ {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle33MHz, EnumSpiOperationReadData }, // Opcode 1: Read
+ {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register
+ {EnumSpiOpcodeWriteNoAddr, SF_INST_WRDI, EnumSpiCycle50MHz, EnumSpiOperationWriteDisable }, // Opcode 3: Write Disable
+ {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)
+ {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (64KB
+ {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program
+ {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register
+ },
+ //
+ // The offset of the start of the BIOS image in flash. This value is platform specific
+ // and depends on the system flash map. If BIOS size is bigger than flash return -1
+ //
+ ((NUMONYX_N25Q032_SIZE >= FLASH_SIZE) ? NUMONYX_N25Q032_SIZE - FLASH_SIZE : (UINTN) (-1)),
+ //
+ // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map
+ //
+ FLASH_SIZE
+ },
+ {
+ SF_VENDOR_ID_NUMONYX, // VendorId
+ SF_DEVICE_ID0_M25PXXX, // DeviceId 0
+ SF_DEVICE_ID1_M25PX32, // DeviceId 1
+ {
+ SF_INST_WREN, // Prefix Opcode 0: Write Enable
+ SF_INST_WREN // Prefix Opcode 1: Write Enable (this part doesn't support EWSR)
+ },
+ {
+ {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID
+ {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle33MHz, EnumSpiOperationReadData }, // Opcode 1: Read
+ {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register
+ {EnumSpiOpcodeWriteNoAddr, SF_INST_WRDI, EnumSpiCycle50MHz, EnumSpiOperationWriteDisable }, // Opcode 3: Write Disable
+ {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)
+ {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (64KB
+ {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program
+ {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register
+ },
+ //
+ // The offset of the start of the BIOS image in flash. This value is platform specific
+ // and depends on the system flash map. If BIOS size is bigger than flash return -1
+ //
+ ((NUMONYX_M25PX32_SIZE >= FLASH_SIZE) ? NUMONYX_M25PX32_SIZE - FLASH_SIZE : (UINTN) (-1)),
+ //
+ // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map
+ //
+ FLASH_SIZE
+ },
+ {
+ SF_VENDOR_ID_NUMONYX, // VendorId
+ SF_DEVICE_ID0_M25PXXX, // DeviceId 0
+ SF_DEVICE_ID1_M25PX64, // DeviceId 1
+ {
+ SF_INST_WREN, // Prefix Opcode 0: Write Enable
+ SF_INST_WREN // Prefix Opcode 1: Write Enable (this part doesn't support EWSR)
+ },
+ {
+ {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID
+ {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle33MHz, EnumSpiOperationReadData }, // Opcode 1: Read
+ {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register
+ {EnumSpiOpcodeWriteNoAddr, SF_INST_WRDI, EnumSpiCycle50MHz, EnumSpiOperationWriteDisable }, // Opcode 3: Write Disable
+ {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)
+ {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (64KB
+ {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program
+ {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register
+ },
+ //
+ // The offset of the start of the BIOS image in flash. This value is platform specific
+ // and depends on the system flash map. If BIOS size is bigger than flash return -1
+ //
+ ((NUMONYX_M25PX64_SIZE >= FLASH_SIZE) ? NUMONYX_M25PX64_SIZE - FLASH_SIZE : (UINTN) (-1)),
+ //
+ // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map
+ //
+ FLASH_SIZE
+ },
+ {
+ SF_VENDOR_ID_NUMONYX, // VendorId
+ SF_DEVICE_ID0_N25QXXX, // DeviceId 0
+ SF_DEVICE_ID1_N25Q128, // DeviceId 1
+ {
+ SF_INST_WREN, // Prefix Opcode 0: Write Enable
+ SF_INST_WREN // Prefix Opcode 1: Write Enable (this part doesn't support EWSR)
+ },
+ {
+ {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID
+ {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle33MHz, EnumSpiOperationReadData }, // Opcode 1: Read
+ {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register
+ {EnumSpiOpcodeWriteNoAddr, SF_INST_WRDI, EnumSpiCycle50MHz, EnumSpiOperationWriteDisable }, // Opcode 3: Write Disable
+ {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)
+ {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (64KB
+ {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program
+ {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register
+ },
+ //
+ // The offset of the start of the BIOS image in flash. This value is platform specific
+ // and depends on the system flash map. If BIOS size is bigger than flash return -1
+ //
+ ((NUMONYX_N25Q128_SIZE >= FLASH_SIZE) ? NUMONYX_N25Q128_SIZE - FLASH_SIZE : (UINTN) (-1)),
+ //
+ // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map
+ //
+ FLASH_SIZE
+ },
+ {
+ SF_VENDOR_ID_EON, // VendorId
+ SF_DEVICE_ID0_EN25QXX, // DeviceId 0
+ SF_DEVICE_ID1_EN25Q16, // DeviceId 1
+ {
+ SF_INST_WREN, // Prefix Opcode 0: Write Enable
+ SF_INST_WREN // Prefix Opcode 1: Write Enable (this part doesn't support EWSR)
+ },
+ {
+ {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID
+ {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData }, // Opcode 1: Read
+ {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register
+ {EnumSpiOpcodeWriteNoAddr, SF_INST_WRDI, EnumSpiCycle50MHz, EnumSpiOperationWriteDisable }, // Opcode 3: Write Disable
+ {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)
+ {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (64KB
+ {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program
+ {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register
+ },
+ //
+ // The offset of the start of the BIOS image in flash. This value is platform specific
+ // and depends on the system flash map. If BIOS size is bigger than flash return -1
+ //
+ ((EON_EN25Q16_SIZE >= FLASH_SIZE) ? EON_EN25Q16_SIZE - FLASH_SIZE : (UINTN) (-1)),
+ //
+ // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map
+ //
+ FLASH_SIZE
+ },
+ {
+ SF_VENDOR_ID_EON, // VendorId
+ SF_DEVICE_ID0_EN25QXX, // DeviceId 0
+ SF_DEVICE_ID1_EN25Q32, // DeviceId 1
+ {
+ SF_INST_WREN, // Prefix Opcode 0: Write Enable
+ SF_INST_WREN // Prefix Opcode 1: Write Enable (this part doesn't support EWSR)
+ },
+ {
+ {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID
+ {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle33MHz, EnumSpiOperationReadData }, // Opcode 1: Read
+ {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register
+ {EnumSpiOpcodeWriteNoAddr, SF_INST_WRDI, EnumSpiCycle50MHz, EnumSpiOperationWriteDisable }, // Opcode 3: Write Disable
+ {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)
+ {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (64KB
+ {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program
+ {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register
+ },
+ //
+ // The offset of the start of the BIOS image in flash. This value is platform specific
+ // and depends on the system flash map. If BIOS size is bigger than flash return -1
+ //
+ ((EON_EN25Q32_SIZE >= FLASH_SIZE) ? EON_EN25Q32_SIZE - FLASH_SIZE : (UINTN) (-1)),
+ //
+ // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map
+ //
+ FLASH_SIZE
+ },
+ {
+ SF_VENDOR_ID_EON, // VendorId
+ SF_DEVICE_ID0_EN25QXX, // DeviceId 0
+ SF_DEVICE_ID1_EN25Q64, // DeviceId 1
+ {
+ SF_INST_WREN, // Prefix Opcode 0: Write Enable
+ SF_INST_WREN // Prefix Opcode 1: Write Enable (this part doesn't support EWSR)
+ },
+ {
+ {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID
+ {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData }, // Opcode 1: Read
+ {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register
+ {EnumSpiOpcodeWriteNoAddr, SF_INST_WRDI, EnumSpiCycle50MHz, EnumSpiOperationWriteDisable }, // Opcode 3: Write Disable
+ {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)
+ {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (64KB
+ {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program
+ {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register
+ },
+ //
+ // The offset of the start of the BIOS image in flash. This value is platform specific
+ // and depends on the system flash map. If BIOS size is bigger than flash return -1
+ //
+ ((EON_EN25Q64_SIZE >= FLASH_SIZE) ? EON_EN25Q64_SIZE - FLASH_SIZE : (UINTN) (-1)),
+ //
+ // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map
+ //
+ FLASH_SIZE
+ },
+ {
+ SF_VENDOR_ID_EON, // VendorId
+ SF_DEVICE_ID0_EN25QXX, // DeviceId 0
+ SF_DEVICE_ID1_EN25Q128, // DeviceId 1
+ {
+ SF_INST_WREN, // Prefix Opcode 0: Write Enable
+ SF_INST_WREN // Prefix Opcode 1: Write Enable (this part doesn't support EWSR)
+ },
+ {
+ {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID
+ {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData }, // Opcode 1: Read
+ {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register
+ {EnumSpiOpcodeWriteNoAddr, SF_INST_WRDI, EnumSpiCycle50MHz, EnumSpiOperationWriteDisable }, // Opcode 3: Write Disable
+ {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)
+ {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (64KB
+ {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program
+ {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register
+ },
+ //
+ // The offset of the start of the BIOS image in flash. This value is platform specific
+ // and depends on the system flash map. If BIOS size is bigger than flash return -1
+ //
+ ((EON_EN25Q128_SIZE >= FLASH_SIZE) ? EON_EN25Q128_SIZE - FLASH_SIZE : (UINTN) (-1)),
+ //
+ // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map
+ //
+ FLASH_SIZE
+ },
+ {
+ SF_VENDOR_ID_AMIC, // VendorId
+ SF_DEVICE_ID0_A25L016, // DeviceId 0
+ SF_DEVICE_ID1_A25L016, // DeviceId 1
+ {
+ SF_INST_WREN, // Prefix Opcode 0: Write Enable
+ SF_INST_WREN // Prefix Opcode 1: Write Enable (this part doesn't support EWSR)
+ },
+ {
+ {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID
+ {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData }, // Opcode 1: Read
+ {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register
+ {EnumSpiOpcodeWriteNoAddr, SF_INST_WRDI, EnumSpiCycle50MHz, EnumSpiOperationWriteDisable }, // Opcode 3: Write Disable
+ {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)
+ {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (64KB
+ {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program
+ {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register
+ },
+ //
+ // The offset of the start of the BIOS image in flash. This value is platform specific
+ // and depends on the system flash map. If BIOS size is bigger than flash return -1
+ //
+ ((AMIC_A25L16_SIZE >= FLASH_SIZE) ? AMIC_A25L16_SIZE - FLASH_SIZE : (UINTN) (-1)),
+ //
+ // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map
+ //
+ FLASH_SIZE
+ }
+};
diff --git a/BraswellPlatformPkg/Common/Library/IntelPchAcpiTimerLib/CommonHeader.h b/BraswellPlatformPkg/Common/Library/IntelPchAcpiTimerLib/CommonHeader.h new file mode 100644 index 0000000000..f350ba3cf2 --- /dev/null +++ b/BraswellPlatformPkg/Common/Library/IntelPchAcpiTimerLib/CommonHeader.h @@ -0,0 +1,28 @@ +/** @file
+ Common header file shared by all source files.
+ This file includes package header files, library classes and protocol, PPI & GUID definitions.
+
+ Copyright (c) 2007 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __COMMON_HEADER_H_
+#define __COMMON_HEADER_H_
+
+#include <Base.h>
+#include <PchAccess.h>
+#include <Library/TimerLib.h>
+#include <Library/BaseLib.h>
+#include <Library/IoLib.h>
+#include <Library/PciLib.h>
+#include <Library/PcdLib.h>
+
+#endif
diff --git a/BraswellPlatformPkg/Common/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.c b/BraswellPlatformPkg/Common/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.c new file mode 100644 index 0000000000..1e0b272074 --- /dev/null +++ b/BraswellPlatformPkg/Common/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.c @@ -0,0 +1,260 @@ +/** @file
+ ICH9 ACPI Timer implements one instance of Timer Library.
+
+ Copyright (c) 2007 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "CommonHeader.h"
+
+/**
+ The constructor function enables ACPI IO space.
+
+ If ACPI I/O space not enabled, this function will enable it.
+ It will always return RETURN_SUCCESS.
+
+ @retval EFI_SUCCESS The constructor always returns RETURN_SUCCESS.
+
+**/
+RETURN_STATUS
+EFIAPI
+IntelPchAcpiTimerLibConstructor (
+ VOID
+ )
+{
+
+ //
+ // If ACPI I/O space is not enabled, program ACPI I/O base address and enable it.
+ //
+ MmioWrite16 (
+ MmPciAddress (
+ 0,
+ DEFAULT_PCI_BUS_NUMBER_PCH,
+ PCI_DEVICE_NUMBER_PCH_LPC,
+ PCI_FUNCTION_NUMBER_PCH_LPC,
+ R_PCH_LPC_ACPI_BASE
+ ),
+ ((PcdGet16 (PcdPchAcpiIoPortBaseAddress) & B_PCH_LPC_ACPI_BASE_BAR) | B_PCH_LPC_ACPI_BASE_EN)
+ );
+
+ return RETURN_SUCCESS;
+}
+
+/**
+ Internal function to read the current tick counter of ACPI.
+
+ Internal function to read the current tick counter of ACPI.
+
+ @return The tick counter read.
+
+**/
+STATIC
+UINT32
+InternalAcpiGetTimerTick (
+ VOID
+ )
+{
+ return IoRead32 (PcdGet16 (PcdPchAcpiIoPortBaseAddress) + R_PCH_ACPI_PM1_TMR);
+}
+
+/**
+ Stalls the CPU for at least the given number of ticks.
+
+ Stalls the CPU for at least the given number of ticks. It's invoked by
+ MicroSecondDelay() and NanoSecondDelay().
+
+ @param Delay A period of time to delay in ticks.
+
+**/
+STATIC
+VOID
+InternalAcpiDelay (
+ IN UINT32 Delay
+ )
+{
+ UINT32 Ticks;
+ UINT32 Times;
+
+ Times = Delay >> 22;
+ Delay &= BIT22 - 1;
+ do {
+ //
+ // The target timer count is calculated here
+ //
+ Ticks = InternalAcpiGetTimerTick () + Delay;
+ Delay = BIT22;
+ //
+ // Wait until time out
+ // Delay >= 2^23 could not be handled by this function
+ // Timer wrap-arounds are handled correctly by this function
+ //
+ while (((Ticks - InternalAcpiGetTimerTick ()) & BIT23) == 0) {
+ CpuPause ();
+ }
+ } while (Times-- > 0);
+}
+
+/**
+ Stalls the CPU for at least the given number of microseconds.
+
+ Stalls the CPU for the number of microseconds specified by MicroSeconds.
+
+ @param[in] MicroSeconds The minimum number of microseconds to delay.
+
+ @return MicroSeconds
+
+**/
+UINTN
+EFIAPI
+MicroSecondDelay (
+ IN UINTN MicroSeconds
+ )
+{
+ InternalAcpiDelay (
+ (UINT32)DivU64x32 (
+ MultU64x32 (
+ MicroSeconds,
+ V_PCH_ACPI_PM1_TMR_FREQUENCY
+ ),
+ 1000000u
+ )
+ );
+
+ return MicroSeconds;
+}
+
+/**
+ Stalls the CPU for at least the given number of nanoseconds.
+
+ Stalls the CPU for the number of nanoseconds specified by NanoSeconds.
+
+ @param[in] NanoSeconds The minimum number of nanoseconds to delay.
+
+ @return NanoSeconds
+
+**/
+UINTN
+EFIAPI
+NanoSecondDelay (
+ IN UINTN NanoSeconds
+ )
+{
+ InternalAcpiDelay (
+ (UINT32)DivU64x32 (
+ MultU64x32 (
+ NanoSeconds,
+ V_PCH_ACPI_PM1_TMR_FREQUENCY
+ ),
+ 1000000000u
+ )
+ );
+
+ return NanoSeconds;
+}
+
+/**
+ Retrieves the current value of a 64-bit free running performance counter.
+
+ Retrieves the current value of a 64-bit free running performance counter. The
+ counter can either count up by 1 or count down by 1. If the physical
+ performance counter counts by a larger increment, then the counter values
+ must be translated. The properties of the counter can be retrieved from
+ GetPerformanceCounterProperties().
+
+ @return The current value of the free running performance counter.
+
+**/
+UINT64
+EFIAPI
+GetPerformanceCounter (
+ VOID
+ )
+{
+ return (UINT64)InternalAcpiGetTimerTick ();
+}
+
+/**
+ Retrieves the 64-bit frequency in Hz and the range of performance counter
+ values.
+
+ If StartValue is not NULL, then the value that the performance counter starts
+ with immediately after is it rolls over is returned in StartValue. If
+ EndValue is not NULL, then the value that the performance counter end with
+ immediately before it rolls over is returned in EndValue. The 64-bit
+ frequency of the performance counter in Hz is always returned. If StartValue
+ is less than EndValue, then the performance counter counts up. If StartValue
+ is greater than EndValue, then the performance counter counts down. For
+ example, a 64-bit free running counter that counts up would have a StartValue
+ of 0 and an EndValue of 0xFFFFFFFFFFFFFFFF. A 24-bit free running counter
+ that counts down would have a StartValue of 0xFFFFFF and an EndValue of 0.
+
+ @param[out] StartValue The value the performance counter starts with when it
+ rolls over.
+ @param[out] EndValue The value that the performance counter ends with before
+ it rolls over.
+
+ @return The frequency in Hz.
+
+**/
+UINT64
+EFIAPI
+GetPerformanceCounterProperties (
+ OUT UINT64 *StartValue, OPTIONAL
+ OUT UINT64 *EndValue OPTIONAL
+ )
+{
+ if (StartValue != NULL) {
+ *StartValue = 0;
+ }
+
+ if (EndValue != NULL) {
+ *EndValue = V_PCH_ACPI_PM1_TMR_MAX_VAL - 1;
+ }
+
+ return V_PCH_ACPI_PM1_TMR_FREQUENCY;
+}
+
+/**
+ Converts elapsed ticks of performance counter to time in nanoseconds.
+
+ This function converts the elapsed ticks of running performance counter to
+ time value in unit of nanoseconds.
+
+ @param[in] Ticks The number of elapsed ticks of running performance counter.
+
+ @return The elapsed time in nanoseconds.
+
+**/
+UINT64
+EFIAPI
+GetTimeInNanoSecond (
+ IN UINT64 Ticks
+ )
+{
+ UINT64 NanoSeconds;
+ UINT32 Remainder;
+
+ //
+ // Ticks
+ // Time = --------- x 1,000,000,000
+ // Frequency
+ //
+ NanoSeconds = MultU64x32 (DivU64x32Remainder (Ticks, V_PCH_ACPI_PM1_TMR_FREQUENCY, &Remainder), 1000000000u);
+
+ //
+ // Frequency < 0x100000000, so Remainder < 0x100000000, then (Remainder * 1,000,000,000)
+ // will not overflow 64-bit.
+ //
+ NanoSeconds += DivU64x32 (MultU64x32 ((UINT64) Remainder, 1000000000u), V_PCH_ACPI_PM1_TMR_FREQUENCY);
+
+ return NanoSeconds;
+}
+
diff --git a/BraswellPlatformPkg/Common/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.inf b/BraswellPlatformPkg/Common/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.inf new file mode 100644 index 0000000000..cc1fc6acfd --- /dev/null +++ b/BraswellPlatformPkg/Common/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.inf @@ -0,0 +1,51 @@ +## @file
+# Provides the Inte PCH ACPI Timer Library
+#
+# Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.<BR>
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php.
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = IntelPchAcpiTimerLib
+ FILE_GUID = 0C0AC8C1-E368-4d20-85FE-23EFB3DB094E
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = TimerLib
+ EDK_RELEASE_VERSION = 0x00020000
+ EFI_SPECIFICATION_VERSION = 0x00020000
+
+ CONSTRUCTOR = IntelPchAcpiTimerLibConstructor
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = IA32 X64 IPF EBC
+#
+
+[Sources.common]
+ IntelPchAcpiTimerLib.c
+ CommonHeader.h
+
+[Packages]
+ MdePkg/MdePkg.dec
+ ChvRefCodePkg/ChvRefCodePkg.dec
+ BraswellPlatformPkg/BraswellPlatformPkg.dec
+
+[LibraryClasses]
+ PcdLib
+ PciLib
+ IoLib
+ BaseLib
+
+[Pcd.common]
+ gEfiPchTokenSpaceGuid.PcdPchAcpiIoPortBaseAddress # CONSUMES
+ gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress # CONSUMES
diff --git a/BraswellPlatformPkg/Common/Library/Ksc/Dxe/DxeKscLib.c b/BraswellPlatformPkg/Common/Library/Ksc/Dxe/DxeKscLib.c new file mode 100644 index 0000000000..d4f5a59709 --- /dev/null +++ b/BraswellPlatformPkg/Common/Library/Ksc/Dxe/DxeKscLib.c @@ -0,0 +1,184 @@ +/** @file
+ Boot service DXE KSC library implementation.
+
+ Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "KscLib.h"
+#include "DxeKsclib.h"
+
+BOOLEAN mDxeKscLibInitialized = FALSE;
+
+//
+// Function implemenations
+//
+/**
+ Initialize the library.
+ Read KSC Command port (0x66), if found 0xff means no EC exists else EC exists
+
+ @return EFI_SUCCESS KscLib is successfully initialized.
+
+**/
+EFI_STATUS
+InitializeKscLib (
+ VOID
+ )
+{
+ if (IoRead8(KSC_C_PORT) == 0xff) {
+ mDxeKscLibInitialized = FALSE;
+ return EFI_DEVICE_ERROR; // EC Doesn't exists
+ }
+
+ mDxeKscLibInitialized = TRUE;
+
+ return EFI_SUCCESS; // EC exists
+}
+
+/**
+ Sends command to Keyboard System Controller.
+
+ @param Command Command byte to send
+
+ @retval EFI_SUCCESS Command success
+ @retval EFI_DEVICE_ERROR Command error
+
+**/
+EFI_STATUS
+SendKscCommand (
+ UINT8 Command
+ )
+{
+ UINTN Index;
+ UINT8 KscStatus = 0;
+
+ Index = 0;
+
+ //
+ // Wait for KSC to be ready (with a timeout)
+ //
+ ReceiveKscStatus (&KscStatus);
+ while (((KscStatus & KSC_S_IBF) != 0) && (Index < KSC_TIME_OUT)) {
+ gBS->Stall (15);
+ ReceiveKscStatus (&KscStatus);
+ Index++;
+ }
+ if (Index >= KSC_TIME_OUT) {
+ return EFI_DEVICE_ERROR;
+ }
+
+ //
+ // Send the KSC command
+ //
+ DEBUG ((EFI_D_INFO, "SendKscCommand: command = %x\n", Command));
+ IoWrite8(KSC_C_PORT, Command);
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Receives status from Keyboard System Controller.
+
+ @param Status Status byte to receive
+
+ @retval EFI_SUCCESS Always success
+
+**/
+EFI_STATUS
+ReceiveKscStatus (
+ UINT8 *KscStatus
+ )
+{
+ //
+ // Read and return the status
+ //
+ *KscStatus = IoRead8(KSC_C_PORT);
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Sends data to Keyboard System Controller.
+
+ @param Data Data byte to send
+
+ @retval EFI_SUCCESS Success
+ @retval EFI_TIMEOUT Timeout
+ @retval Other Failed
+
+**/
+EFI_STATUS
+SendKscData (
+ UINT8 Data
+ )
+{
+ UINTN Index;
+ UINT8 KscStatus;
+
+ Index = 0;
+
+ //
+ // Wait for KSC to be ready (with a timeout)
+ //
+ ReceiveKscStatus (&KscStatus);
+ while (((KscStatus & KSC_S_IBF) != 0) && (Index < KSC_TIME_OUT)) {
+ gBS->Stall (15);
+ ReceiveKscStatus (&KscStatus);
+ Index++;
+ }
+ if (Index >= KSC_TIME_OUT) {
+ return EFI_DEVICE_ERROR;
+ }
+
+ IoWrite8(KSC_D_PORT, Data);
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Receives data from Keyboard System Controller.
+
+ @param Data Data byte received
+
+ @retval EFI_SUCCESS Read success
+ @retval EFI_DEVICE_ERROR Read error
+
+**/
+EFI_STATUS
+ReceiveKscData (
+ UINT8 *Data
+ )
+{
+ UINTN Index;
+ UINT8 KscStatus;
+
+ Index = 0;
+
+ //
+ // Wait for KSC to be ready (with a timeout)
+ //
+ ReceiveKscStatus (&KscStatus);
+ while (((KscStatus & KSC_S_OBF) == 0) && (Index < KSC_TIME_OUT)) {
+ gBS->Stall (15);
+ ReceiveKscStatus (&KscStatus);
+ Index++;
+ }
+ if (Index >= KSC_TIME_OUT) {
+ return EFI_DEVICE_ERROR;
+ }
+
+ //
+ // Read KSC data and return
+ //
+ *Data = IoRead8(KSC_D_PORT);
+
+ return EFI_SUCCESS;
+}
diff --git a/BraswellPlatformPkg/Common/Library/Ksc/Dxe/DxeKscLib.h b/BraswellPlatformPkg/Common/Library/Ksc/Dxe/DxeKscLib.h new file mode 100644 index 0000000000..5d1d7ee59d --- /dev/null +++ b/BraswellPlatformPkg/Common/Library/Ksc/Dxe/DxeKscLib.h @@ -0,0 +1,26 @@ +/** @file
+ Platform Info Driver.
+
+ Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _PLATFORM_INFO_DRIVER_H_
+#define _PLATFORM_INFO_DRIVER_H_
+
+#include <Library/IoLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseLib.h>
+#include <Library/HobLib.h>
+#include <Protocol/CpuIo2.h>
+#include <Library/UefiBootServicesTableLib.h>
+
+#endif
diff --git a/BraswellPlatformPkg/Common/Library/Ksc/Dxe/DxeKscLib.inf b/BraswellPlatformPkg/Common/Library/Ksc/Dxe/DxeKscLib.inf new file mode 100644 index 0000000000..ac575975a1 --- /dev/null +++ b/BraswellPlatformPkg/Common/Library/Ksc/Dxe/DxeKscLib.inf @@ -0,0 +1,34 @@ +## @file
+# DxeKscLib Localized Abstract and Description Content
+#
+# Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.<BR>
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php.
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = DxeKscLib
+ FILE_GUID = C8AE8AF6-ABB4-44b1-A679-E218E1782799
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = DxeKscLib
+
+[Sources]
+ DxeKscLib.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ BraswellPlatformPkg/BraswellPlatformPkg.dec
+ IntelFrameworkPkg/IntelFrameworkPkg.dec
+
+[LibraryClasses]
+ DebugLib
+ IoLib
diff --git a/BraswellPlatformPkg/Common/Library/Ksc/Pei/PeiKsc.h b/BraswellPlatformPkg/Common/Library/Ksc/Pei/PeiKsc.h new file mode 100644 index 0000000000..fd4a16d503 --- /dev/null +++ b/BraswellPlatformPkg/Common/Library/Ksc/Pei/PeiKsc.h @@ -0,0 +1,31 @@ +/** @file
+ This file contains Multi Platform PPI information.
+
+ Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _PEI_MULTIPLATFORM_PPI_H
+#define _PEI_MULTIPLATFORM_PPI_H
+
+//
+// Include files
+//
+#include <Library/IoLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseLib.h>
+#include "PeiKscLib.h"
+
+#ifndef STALL_ONE_MICRO_SECOND
+#define STALL_ONE_MICRO_SECOND 1
+#endif
+
+#endif
diff --git a/BraswellPlatformPkg/Common/Library/Ksc/Pei/PeiKscLib.c b/BraswellPlatformPkg/Common/Library/Ksc/Pei/PeiKscLib.c new file mode 100644 index 0000000000..6d02a7293e --- /dev/null +++ b/BraswellPlatformPkg/Common/Library/Ksc/Pei/PeiKscLib.c @@ -0,0 +1,176 @@ +/** @file
+ Ksc settings in PEI phase.
+
+ Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "PeiKsc.h"
+
+//
+// Function implemenations
+//
+/**
+ The PEI function requires CPU IO protocol, through which it reads KSC Command port
+ and ensures that EC exists or not.
+
+ Retval EFI_SUCCESS EC found and KscLib is successfully initialized.
+ Retval EFI_DEVICE_ERROR EC is NOT present on the system.
+
+**/
+EFI_STATUS
+InitializeKscLib ( )
+{
+ //
+ // Read from EC Command/Status port (0x66), if value is 0xFF means EC dose not exist.
+ //
+ if (IoRead8 (KSC_C_PORT) == 0xFF) {
+ return EFI_DEVICE_ERROR;
+ }
+
+ return EFI_SUCCESS;
+
+}
+
+/**
+ Sends command to Keyboard System Controller.
+
+ @param[in] Command Command byte to send
+
+ @retval EFI_SUCCESS Command success
+ @retval EFI_DEVICE_ERROR Command error
+ @retval EFI_TIMEOUT Command timeout
+
+**/
+EFI_STATUS
+SendKscCommand (
+ IN UINT8 Command
+ )
+{
+ UINTN Index = 0;
+ UINT8 KscStatus = 0;
+
+ //
+ // Wait for KSC to be ready (with a timeout)
+ //
+ ReceiveKscStatus (&KscStatus);
+ while (((KscStatus & KSC_S_IBF) != 0) && (Index < KSC_TIME_OUT)) {
+ ReceiveKscStatus (&KscStatus);
+ Index++;
+ }
+
+ if (Index >= KSC_TIME_OUT) {
+ DEBUG ((EFI_D_INFO, "SendKscCommand Time Out Error\n"));
+ return EFI_TIMEOUT;
+ }
+ //
+ // Send the KSC command
+ //
+ IoWrite8 (KSC_C_PORT, Command);
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Receives status from Keyboard System Controller.
+
+ @param[out] KscStatus Status byte to receive
+
+ @retval EFI_DEVICE_ERROR Ksc library has not initialized yet or KSC not present
+ @retval EFI_SUCCESS Get KSC status successfully
+
+**/
+EFI_STATUS
+ReceiveKscStatus (
+ OUT UINT8 *KscStatus
+ )
+{
+ *KscStatus = IoRead8 (KSC_C_PORT);
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Sends data to Keyboard System Controller.
+
+ @param[in] Data Data byte to send
+
+ @retval EFI_SUCCESS Success
+ @retval EFI_DEVICE_ERROR Error
+ @retval EFI_TIMEOUT Command timeout
+
+**/
+EFI_STATUS
+SendKscData (
+ IN UINT8 Data
+ )
+{
+ UINTN Index = 0;
+ UINT8 KscStatus = 0;
+ //
+ // Wait for KSC to be ready (with a timeout)
+ //
+ ReceiveKscStatus (&KscStatus);
+ while (((KscStatus & KSC_S_IBF) != 0) && (Index < KSC_TIME_OUT)) {
+ ReceiveKscStatus (&KscStatus);
+ Index++;
+ }
+
+ if (Index >= KSC_TIME_OUT) {
+ DEBUG ((EFI_D_INFO, "SendKscData Time Out Error\n"));
+ return EFI_TIMEOUT;
+ }
+ //
+ // Write Data at EC Port (0x62)
+ //
+ IoWrite8 (KSC_D_PORT, Data);
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Receives data from Keyboard System Controller.
+
+ @param[out] Data Data byte received
+
+ @retval EFI_SUCCESS Read success
+ @retval EFI_DEVICE_ERROR Read error
+ @retval EFI_TIMEOUT Command timeout
+
+**/
+EFI_STATUS
+ReceiveKscData (
+ OUT UINT8 *Data
+ )
+{
+ UINTN Index = 0;
+ UINT8 KscStatus = 0;
+ //
+ // Wait for KSC to be ready (with a timeout)
+ //
+ ReceiveKscStatus (&KscStatus);
+ while (((KscStatus & KSC_S_OBF) == 0) && (Index < KSC_TIME_OUT)) {
+ ReceiveKscStatus (&KscStatus);
+ Index++;
+ }
+
+ if (Index >= KSC_TIME_OUT) {
+ DEBUG ((EFI_D_INFO, "ReceiveKscData Time Out Error\n"));
+ return EFI_TIMEOUT;
+ }
+ //
+ // Read KSC data and return
+ //
+ *Data = IoRead8 (KSC_D_PORT);
+
+ return EFI_SUCCESS;
+}
+
diff --git a/BraswellPlatformPkg/Common/Library/Ksc/Pei/PeiKscLib.inf b/BraswellPlatformPkg/Common/Library/Ksc/Pei/PeiKscLib.inf new file mode 100644 index 0000000000..a972b4aa20 --- /dev/null +++ b/BraswellPlatformPkg/Common/Library/Ksc/Pei/PeiKscLib.inf @@ -0,0 +1,34 @@ +## @file
+# Component description file for PEI KSC library
+#
+# Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.<BR>
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php.
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = PeiKscLib
+ FILE_GUID = CD537150-B828-477d-935E-C3853950FC75
+ MODULE_TYPE = PEIM
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = PeiKscLib
+
+[Sources]
+ PeiKscLib.c
+ PeiKsc.h
+
+[Packages]
+ MdePkg/MdePkg.dec
+ BraswellPlatformPkg/BraswellPlatformPkg.dec
+
+[LibraryClasses]
+ DebugLib
+ IoLib
diff --git a/BraswellPlatformPkg/Common/Library/Ksc/Smm/SmmKscLib.c b/BraswellPlatformPkg/Common/Library/Ksc/Smm/SmmKscLib.c new file mode 100644 index 0000000000..dc553ce523 --- /dev/null +++ b/BraswellPlatformPkg/Common/Library/Ksc/Smm/SmmKscLib.c @@ -0,0 +1,217 @@ +/** @file
+ SMM KSC library implementation.
+
+ Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "SmmKscLib.h"
+
+BOOLEAN mSmmKscLibInitialized = FALSE;
+
+//
+// Function implemenations
+//
+/**
+ Initialize the library.
+ The SMM library only requires SMM IO library and has no initialization.
+ However, this must be called prior to use of any other KSC library functions
+ for future compatibility.
+
+ @Return EFI_SUCCESS KscLib is successfully initialized.
+
+**/
+EFI_STATUS
+InitializeKscLib (
+ VOID
+ )
+{
+ //
+ // Fail if EC doesn't exist.
+ //
+ if (SmmIoRead8(KSC_C_PORT) == 0xff) {
+ mSmmKscLibInitialized = FALSE;
+ return EFI_DEVICE_ERROR;
+ }
+
+ mSmmKscLibInitialized = TRUE;
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Sends command to Keyboard System Controller.
+
+ @param Command Command byte to send
+
+ @retval EFI_SUCCESS Command success
+ @retval EFI_DEVICE_ERROR Command error
+
+**/
+EFI_STATUS
+SendKscCommand (
+ UINT8 Command
+ )
+{
+ UINTN Index;
+ UINT8 KscStatus = 0;
+
+ //
+ // Verify if KscLib has been initialized, NOT if EC dose not exist.
+ //
+ if (mSmmKscLibInitialized == FALSE) {
+ return EFI_DEVICE_ERROR;
+ }
+
+ Index = 0;
+
+ //
+ // Wait for KSC to be ready (with a timeout)
+ //
+ ReceiveKscStatus (&KscStatus);
+ while (((KscStatus & KSC_S_IBF) != 0) && (Index < KSC_TIME_OUT)) {
+ SmmStall (15);
+ ReceiveKscStatus (&KscStatus);
+ Index++;
+ }
+ if (Index >= KSC_TIME_OUT) {
+ return EFI_DEVICE_ERROR;
+ }
+
+ //
+ // Send the KSC command
+ //
+ SmmIoWrite8 (KSC_C_PORT, Command);
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Receives status from Keyboard System Controller.
+
+ @param KscStatus Status byte to receive
+
+ @Return EFI_SUCCESS Always success
+
+**/
+EFI_STATUS
+ReceiveKscStatus (
+ UINT8 *KscStatus
+ )
+{
+ //
+ // Verify if KscLib has been initialized, NOT if EC dose not exist.
+ //
+ if (mSmmKscLibInitialized == FALSE) {
+ return EFI_DEVICE_ERROR;
+ }
+
+ //
+ // Read and return the status
+ //
+ *KscStatus = SmmIoRead8 (KSC_C_PORT);
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Sends data to Keyboard System Controller.
+
+ @param Data Data byte to send
+
+ @retval EFI_SUCCESS Success
+ @retval EFI_DEVICE_ERROR Error
+
+**/
+EFI_STATUS
+SendKscData (
+ UINT8 Data
+ )
+{
+ UINTN Index;
+ UINT8 KscStatus;
+
+ //
+ // Verify if KscLib has been initialized, NOT if EC dose not exist.
+ //
+ if (mSmmKscLibInitialized == FALSE) {
+ return EFI_DEVICE_ERROR;
+ }
+
+ Index = 0;
+
+ //
+ // Wait for KSC to be ready (with a timeout)
+ //
+ ReceiveKscStatus (&KscStatus);
+ while (((KscStatus & KSC_S_IBF) != 0) && (Index < KSC_TIME_OUT)) {
+ SmmStall (15);
+ ReceiveKscStatus (&KscStatus);
+ Index++;
+ }
+ if (Index >= KSC_TIME_OUT) {
+ return EFI_DEVICE_ERROR;
+ }
+
+ //
+ // Send the data and return
+ //
+ SmmIoWrite8 (KSC_D_PORT, Data);
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Receives data from Keyboard System Controller.
+
+ @param Data Data byte received
+
+ @retval EFI_SUCCESS Read success
+ @retval EFI_DEVICE_ERROR Read error
+
+**/
+EFI_STATUS
+ReceiveKscData (
+ UINT8 *Data
+ )
+{
+ UINTN Index;
+ UINT8 KscStatus;
+
+ //
+ // Verify if KscLib has been initialized, NOT if EC dose not exist.
+ //
+ if (mSmmKscLibInitialized == FALSE) {
+ return EFI_DEVICE_ERROR;
+ }
+
+ Index = 0;
+
+ //
+ // Wait for KSC to be ready (with a timeout)
+ //
+ ReceiveKscStatus (&KscStatus);
+ while (((KscStatus & KSC_S_OBF) == 0) && (Index < KSC_TIME_OUT)) {
+ SmmStall (15);
+ ReceiveKscStatus (&KscStatus);
+ Index++;
+ }
+ if (Index >= KSC_TIME_OUT) {
+ return EFI_DEVICE_ERROR;
+ }
+
+ //
+ // Read KSC data and return
+ //
+ *Data = SmmIoRead8 (KSC_D_PORT);
+
+ return EFI_SUCCESS;
+}
diff --git a/BraswellPlatformPkg/Common/Library/Ksc/Smm/SmmKscLib.h b/BraswellPlatformPkg/Common/Library/Ksc/Smm/SmmKscLib.h new file mode 100644 index 0000000000..52c626ed98 --- /dev/null +++ b/BraswellPlatformPkg/Common/Library/Ksc/Smm/SmmKscLib.h @@ -0,0 +1,24 @@ +/** @file
+ KSC Library from smm support
+
+ Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _PLATFORM_INFO_DRIVER_H_
+#define _PLATFORM_INFO_DRIVER_H_
+
+#include "KscLib.h"
+#include <Library/DebugLib.h>
+#include "Library/SmmIoLib.h"
+#include "Library/StallSmmLib.h"
+
+#endif
diff --git a/BraswellPlatformPkg/Common/Library/Ksc/Smm/SmmKscLib.inf b/BraswellPlatformPkg/Common/Library/Ksc/Smm/SmmKscLib.inf new file mode 100644 index 0000000000..d716dabf7d --- /dev/null +++ b/BraswellPlatformPkg/Common/Library/Ksc/Smm/SmmKscLib.inf @@ -0,0 +1,37 @@ +## @file
+# Component description file for internal graphics device library
+#
+# Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.<BR>
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php.
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = SmmKscLib
+ FILE_GUID = EA30D07C-2AE7-454e-AE1F-12FBF9BD3A62
+ MODULE_TYPE = DXE_SMM_DRIVER
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = SmmKscLib
+
+
+[Sources]
+ SmmKscLib.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ BraswellPlatformPkg/BraswellPlatformPkg.dec
+ IntelFrameworkPkg/IntelFrameworkPkg.dec
+
+
+[LibraryClasses]
+ DebugLib
+ SmmIoLib
+ StallSmmLib
diff --git a/BraswellPlatformPkg/Common/Library/MultiPlatformLib/BoardIdentify.c b/BraswellPlatformPkg/Common/Library/MultiPlatformLib/BoardIdentify.c new file mode 100644 index 0000000000..2606810f68 --- /dev/null +++ b/BraswellPlatformPkg/Common/Library/MultiPlatformLib/BoardIdentify.c @@ -0,0 +1,140 @@ +/** @file
+ Boards identification for multiplatform.
+
+ Copyright (c) 2013 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <MultiPlatformLib.h>
+#include <PeiKscLib.h>
+#include <Library/TimerLib.h>
+#include <Library/GpioLib.h>
+
+/**
+ This function Issues EC command (0x0D) to EC to get board ID and FAB ID details and returns to the
+ calling function. Procedure to get Board ID & FAB ID is common to both Mobile and Desktop platforms.
+ Bit position details
+ when EC Command 0x0D is issue to EC
+ Read value 1st byte = EC LSB [ 7:0]
+ Read value 2nd byte = EC MSB [15:8]
+
+ Bits [3:0] - Board ID (Range from 0x00 to 0x0F)
+ Bit 6 - 0 = Mobile/ULT/Embedded;
+ - 1 = Desktop
+ (Note: Not required consider this bit when Bit 7 is set)
+ Bit 7 - 0 = Mainstream
+ - 1 = Entry Notebook & Desktop (Essential Notebook)
+ Bit 8 - Generation (Tick / Tock)
+ (Note: Not required consider this bit when Bit 7 is set)
+ Bits 11:9 - FAB ID (Range from 0x00 to 0x07)
+ Bits 15:12 - Reserved
+
+ @param[in] BoardFabIds Board ID & FabId ID as determined through the EC.
+
+ @retval EFI_SUCCESS The function completed successfully.
+ BoardFabIds word contains
+ LSB - FAB ID (0x00 - 0x07)
+ MSB - Board ID (1, 2, 4, 8)
+ @retval EFI_DEVICE_ERROR KSC fails to respond.
+
+**/
+EFI_STATUS
+GetBoardFabIdsKsc (
+ OUT UINT16 *BoardFabIds
+ )
+{
+ EFI_STATUS Status = EFI_SUCCESS;
+ UINT8 EcMSB;
+ UINT8 EcLSB;
+
+ //
+ // Return Unknown Board ID & Fab ID in case of error.
+ //
+ *BoardFabIds = 0xFFFF;
+
+ //
+ // Send Board ID command to EC
+ //
+ Status = SendKscCommand (0x0D);
+ if (!EFI_ERROR(Status)) {
+ //
+ // Read 1st Byte from EC (MSB)
+ //
+ Status = ReceiveKscData (&EcLSB);
+ if (!EFI_ERROR(Status)) {
+ //
+ // Read 2nd Byte from EC (LSB)
+ //
+ Status = ReceiveKscData (&EcMSB);
+ if (!EFI_ERROR(Status)) {
+ EcMSB = EcMSB & 0x0E;
+ EcMSB = EcMSB >> 1;
+ EcLSB = EcLSB & 0x7; // Need new EC to support 4 bits for BSW CR board ID, or it would be wrong if and w/ 0xF
+ *BoardFabIds = (UINT16) ((EcLSB << 8) | EcMSB ); // MSB[11:8] - Board ID; LSB[3:0] - FAB ID
+ Status = EFI_SUCCESS;
+ }
+ }
+ }
+
+ return Status;
+}
+
+EFI_STATUS
+GetBoradFabIdsGpio (
+ OUT UINT8 *BoardId,
+ OUT UINT8 *FabId
+ )
+{
+ UINT32 mmio_conf0;
+
+ //
+ // Assuming Braswell Cherry Hill/Cherry Island - Get Board ID/Fab ID from GPIO
+ // Set Pad Config to GPIO for BoardId read
+ // mmio_conf0 = (IO_BASE_ADDRESS + Community + Offset + 0x0);
+ // PANEL1_BKLTCTL - BoardId Bit 0, North Community is 0x8000
+ //
+ mmio_conf0 = (IO_BASE_ADDRESS + 0x8000 + 0x5428) + CHV_GPIO_PAD_CONF0_OFFSET;
+ MmioWrite32(mmio_conf0 ,0x00008200); //Set GPIOCfg [10:8] - GPI(0x02), GPIOEn -BIT15
+ //PANEL1_BKLTEN - BoardId Bit 1
+ mmio_conf0 = (IO_BASE_ADDRESS + 0x8000 + 0x5400) + CHV_GPIO_PAD_CONF0_OFFSET;
+ MmioWrite32(mmio_conf0 ,0x00008200); //Set GPIOCfg [10:8] - GPI(0x02), GPIOEn -BIT15
+ //PANEL1_VDDEN - BoardId Bit 2
+ mmio_conf0 = (IO_BASE_ADDRESS + 0x8000 + 0x5460) + CHV_GPIO_PAD_CONF0_OFFSET;
+ MmioWrite32(mmio_conf0 ,0x00008200); //Set GPIOCfg [10:8] - GPI(0x02), GPIOEn -BIT15
+ //Get BoardId
+ *BoardId = (UINT8)((MmioRead16(IO_BASE_ADDRESS + 0x8000 + 0x5428) & BIT0) | \
+ ((MmioRead16(IO_BASE_ADDRESS + 0x8000 + 0x5400) & BIT0) << 1) | \
+ ((MmioRead16(IO_BASE_ADDRESS + 0x8000 + 0x5460) & BIT0) << 2));
+
+ //
+ // Set Pad Config to GPIO for FabId read
+ // mmio_conf0 = (IO_BASE_ADDRESS + Community + Offset + 0x0);
+ // MF_ISH_GPIO_0 - FAB ID bit 0, East Community is 0x10000
+ //
+ mmio_conf0 = (IO_BASE_ADDRESS + 0x10000 + 0x4830) + CHV_GPIO_PAD_CONF0_OFFSET;
+ MmioWrite32(mmio_conf0 ,0x00008200); //Set GPIOCfg [10:8] - GPI(0x02), GPIOEn -BIT15
+ // MF_ISH_GPIO_1 - FAB ID bit 1
+ mmio_conf0 = (IO_BASE_ADDRESS + 0x10000 + 0x4818) + CHV_GPIO_PAD_CONF0_OFFSET;
+ MmioWrite32(mmio_conf0 ,0x00008200); //Set GPIOCfg [10:8] - GPI(0x02), GPIOEn -BIT15
+ // MF_ISH_GPIO_2 - FAB ID bit 2
+ mmio_conf0 = (IO_BASE_ADDRESS + 0x10000 + 0x4848) + CHV_GPIO_PAD_CONF0_OFFSET;
+ MmioWrite32(mmio_conf0 ,0x00008200); //Set GPIOCfg [10:8] - GPI(0x02), GPIOEn -BIT15
+ // MF_ISH_GPIO_3 - FAB ID bit 3
+ mmio_conf0 = (IO_BASE_ADDRESS + 0x10000 + 0x4800) + CHV_GPIO_PAD_CONF0_OFFSET;
+ MmioWrite32(mmio_conf0 ,0x00008200); //Set GPIOCfg [10:8] - GPI(0x02), GPIOEn -BIT15
+ //Get FabId
+ *FabId = (UINT8)((MmioRead16(IO_BASE_ADDRESS + 0x10000 + 0x4830) & BIT0) | \
+ ((MmioRead16(IO_BASE_ADDRESS + 0x10000 + 0x4818) & BIT0) << 1) | \
+ ((MmioRead16(IO_BASE_ADDRESS + 0x10000 + 0x4848) & BIT0) << 2) | \
+ ((MmioRead16(IO_BASE_ADDRESS + 0x10000 + 0x4800) & BIT0) << 3));
+
+ return EFI_SUCCESS;
+}
diff --git a/BraswellPlatformPkg/Common/Library/MultiPlatformLib/BswBoardGpios/BoardGpios.c b/BraswellPlatformPkg/Common/Library/MultiPlatformLib/BswBoardGpios/BoardGpios.c new file mode 100644 index 0000000000..8d7544e508 --- /dev/null +++ b/BraswellPlatformPkg/Common/Library/MultiPlatformLib/BswBoardGpios/BoardGpios.c @@ -0,0 +1,105 @@ +/** @file
+ Gpio setting programming for platform.
+
+ Copyright (c) 2013 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <BoardGpios.h>
+
+typedef
+VOID
+(EFIAPI *GPIO_INIT) (
+ VOID
+ );
+
+
+/**
+ Set GPIO PAD SAI registers for N/E/SW/SE GPIO communities
+
+ @param SAI_Conf_Data GPIO_SAI_INIT data array for each GPIO communities.
+
+**/
+VOID
+SAI_SettingOfGpioFamilies (
+ GPIO_SAI_INIT* SAI_Conf_Data,
+ UINT32 familySize
+ )
+{
+
+ UINT32 count=0;
+ DEBUG ((EFI_D_ERROR, "++SAI Setting of GPIO families%x\n ",familySize));
+
+ //
+ // community SAI programming
+ //
+ for (count=0;count < familySize;count++) {
+ MmioWrite32 (SAI_Conf_Data[count].Offset, SAI_Conf_Data[count].val_.secSAI);
+ }
+
+ DEBUG ((EFI_D_ERROR, "--SAI Setting of GPIO families %x\n ",familySize));
+}
+
+/**
+ Returns the Correct GPIO table for Mobile/Desktop respectively.
+ Before call it, make sure PlatformInfoHob->BoardId&PlatformFlavor is get correctly.
+
+ @param[in] PeiServices General purpose services available to every PEIM.
+ @param[in] PlatformInfoHob PlatformInfoHob pointer with PlatformFlavor specified.
+
+ @retval EFI_SUCCESS The function completed successfully.
+ @retval EFI_DEVICE_ERROR KSC fails to respond.
+
+**/
+EFI_STATUS
+MultiPlatformGpioProgram (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PLATFORM_INFO_HOB *PlatformInfoHob
+ )
+{
+ CHV_CONF_PAD0 lpadvar;
+ GPIO_INIT GpioInit;
+
+ DEBUG ((EFI_D_ERROR, "MultiPlatformGpioProgram()...\n"));
+
+ //
+ // Clearing Interrupt unmask registers
+ //
+ MmioWrite32 (IO_BASE_ADDRESS + GPIO_MMIO_OFFSET_N + GPIO_INTERRUPT_MASK, 0);
+ MmioWrite32 (IO_BASE_ADDRESS + GPIO_MMIO_OFFSET_E + GPIO_INTERRUPT_MASK, 0);
+ MmioWrite32 (IO_BASE_ADDRESS + GPIO_MMIO_OFFSET_SW + GPIO_INTERRUPT_MASK, 0);
+ MmioWrite32 (IO_BASE_ADDRESS + GPIO_MMIO_OFFSET_SE + GPIO_INTERRUPT_MASK, 0);
+ MmioWrite32 (IO_BASE_ADDRESS + GPIO_MMIO_OFFSET_VIRT + GPIO_INTERRUPT_MASK, 0);
+
+ GpioInit = (GPIO_INIT)(UINTN)PcdGet64 (PcdGpioInitFunc);
+ if (GpioInit != NULL) {
+ GpioInit ();
+ }
+
+ //
+ // TODO: W/A [HSD # 4963135] HPD GPIOs drive 0 in mode 1.
+ //
+ lpadvar.padCnf0 = 0;
+ lpadvar.r.Pmode = 0x1;
+ lpadvar.r.RXTXEnCfg = 0x3;
+
+ MmioOr32 (IO_BASE_ADDRESS+0x8000 + 0x5408,lpadvar.padCnf0 ); // HV_DDI0_HPD
+ MmioOr32 (IO_BASE_ADDRESS+0x8000 + 0x5420,lpadvar.padCnf0 ); // HV_DDI1_HPD
+ MmioOr32 (IO_BASE_ADDRESS+0x8000 + 0x5440,lpadvar.padCnf0 ); // HV_DDI2_HPD
+
+ //
+ // Set SDCard RCOMP Trigger Delay to 5ms
+ //
+ MmioWrite32 (IO_BASE_ADDRESS + R_PCH_CFIO_SOUTHEAST + 0x1080, 0x1E848);
+
+ return EFI_SUCCESS;
+}
+
diff --git a/BraswellPlatformPkg/Common/Library/MultiPlatformLib/BswBoardGpios/BoardGpios.h b/BraswellPlatformPkg/Common/Library/MultiPlatformLib/BswBoardGpios/BoardGpios.h new file mode 100644 index 0000000000..eb2431dad8 --- /dev/null +++ b/BraswellPlatformPkg/Common/Library/MultiPlatformLib/BswBoardGpios/BoardGpios.h @@ -0,0 +1,68 @@ +/** @file
+ GPIO setting for Platform.
+ This file includes package header files, library classes.
+
+ Copyright (c) 2013 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _BOARDGPIOS_H_
+#define _BOARDGPIOS_H_
+
+#include <PiPei.h>
+#include "PchAccess.h"
+#include "PlatformBaseAddresses.h"
+#include <../MultiPlatformLib.h>
+#include <Library/IoLib.h>
+#include <Library/HobLib.h>
+#include <Library/Timerlib.h>
+#include <Library/PchPlatformLib.h>
+#include <Library/GpioLib.h>
+#include <Guid/PlatformInfo.h>
+#include <Ppi/Smbus2.h>
+
+#define GPIO_DFX1_PAD0 0x4418
+#define GPIO_DFX3_PAD0 0x4408
+#define GPIO_MF_ISH_I2C1_SCL_PAD0 0x4810
+#define GPIO_MF_ISH_I2C1_SDA_PAD0 0x4858
+#define GPIO_PCIE_CLKREQ0B_PAD0 0x5C00
+#define GPIO_SEC_GPIO_SUS8_PAD0 0x4840
+#define GPIO_SEC_GPIO_SUS8_PAD1 0x4844
+#define GPIO_SEC_GPIO_SUS9_PAD0 0x4860
+#define GPIO_SEC_GPIO_SUS9_PAD1 0x4864
+#define GPIO_SEC_GPIO_SUS10_PAD0 0x4808
+#define GPIO_SEC_GPIO_SUS10_PAD1 0x480C
+#define GPIO_I2C_NFC_SCL_PAD0 0x5038
+#define GPIO_I2C_NFC_SCL_PAD1 0x503C
+#define GPIO_I2C_NFC_SDA_PAD0 0x5020
+#define GPIO_I2C_NFC_SDA_PAD1 0x5024
+#define GPIO_MF_ISH_GPIO_7_PAD0 0x4808
+
+#define USB3_CAMERA 0
+#define MIPI_CAMERA 1
+#define DISABLE 0
+#define NO_PULL_UP 0
+#define SECURE_NFC_ENABLE 1
+
+#define GPIO_SOC_RUNTIME_SCI_N 0x4850
+
+/// *****************************************************************************************************************************************
+/// *****************************************************************************************************************************************
+/// *****************************************************************************************************************************************
+/// *************************************************** CHERRYVIEW GPIO CONFIGURATION *************************************************
+/// *****************************************************************************************************************************************
+/// *****************************************************************************************************************************************
+/// *****************************************************************************************************************************************
+
+#define ENABLE 1
+#define DISABLE 0
+
+#endif
diff --git a/BraswellPlatformPkg/Common/Library/MultiPlatformLib/MultiPlatformLib.c b/BraswellPlatformPkg/Common/Library/MultiPlatformLib/MultiPlatformLib.c new file mode 100644 index 0000000000..d548a968fe --- /dev/null +++ b/BraswellPlatformPkg/Common/Library/MultiPlatformLib/MultiPlatformLib.c @@ -0,0 +1,115 @@ +/** @file
+ Multiplatform initialization.
+
+ Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <MultiPlatformLib.h>
+
+
+/**
+ MultiPlatform initialization
+
+ @param[in] PeiServices General purpose services available to every PEIM.
+ @param[in] PlatformInfoHob The Hob of platform information
+
+ @retval EFI_SUCCESS Platform initialization completed successfully.
+ @retval Others All other error conditions encountered result in an ASSERT.
+
+**/
+EFI_STATUS
+MultiPlatformInfoInit (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN OUT EFI_PLATFORM_INFO_HOB *PlatformInfoHob
+ )
+{
+ UINT32 PcieLength;
+ EFI_STATUS Status;
+
+ //
+ // Calculate PCIe length based on user defined range
+ //
+ switch (PLATFORM_PCIE_BASE_SIZE) {
+ case 64:
+ //64MB
+ PcieLength = 0x04000000;
+ break;
+ case 128:
+ //128MB
+ PcieLength = 0x08000000;
+ break;
+ default:
+ // 256MB
+ PcieLength = 0x10000000;
+ break;
+ }
+
+ //
+ // Don't support BASE above 4GB currently
+ //
+ PlatformInfoHob->PciData.PciExpressSize = PcieLength;
+ PlatformInfoHob->PciData.PciExpressBase = PLATFORM_PCIE_BASE;
+
+ PlatformInfoHob->PciData.PciResourceMem32Base = (UINT32) (PlatformInfoHob->PciData.PciExpressBase - RES_MEM32_MIN_LEN);
+ PlatformInfoHob->PciData.PciResourceMem32Limit = (UINT32) (PlatformInfoHob->PciData.PciExpressBase -1);
+
+ PlatformInfoHob->PciData.PciResourceMem64Base = RES_MEM64_36_BASE;
+ PlatformInfoHob->PciData.PciResourceMem64Limit = RES_MEM64_36_LIMIT;
+ PlatformInfoHob->CpuData.CpuAddressWidth = 36;
+
+ PlatformInfoHob->MemData.MemMir0 = PlatformInfoHob->PciData.PciResourceMem64Base;
+ PlatformInfoHob->MemData.MemMir1 = PlatformInfoHob->PciData.PciResourceMem64Limit + 1;
+
+ PlatformInfoHob->PciData.PciResourceMinSecBus = 1; //can be changed by SystemConfiguration->PciMinSecondaryBus;
+
+ //
+ // Set MemMaxTolm to the lowest address between PCIe Base and PCI32 Base
+ //
+ if (PlatformInfoHob->PciData.PciExpressBase > PlatformInfoHob->PciData.PciResourceMem32Base ) {
+ PlatformInfoHob->MemData.MemMaxTolm = (UINT32) PlatformInfoHob->PciData.PciResourceMem32Base;
+ } else {
+ PlatformInfoHob->MemData.MemMaxTolm = (UINT32) PlatformInfoHob->PciData.PciExpressBase;
+ }
+ PlatformInfoHob->MemData.MemTolm = PlatformInfoHob->MemData.MemMaxTolm;
+
+ //
+ // Platform PCI MMIO Size in unit of 1MB
+ //
+ PlatformInfoHob->MemData.MmioSize = 0x1000 - (UINT16)(PlatformInfoHob->MemData.MemMaxTolm >> 20);
+
+ //
+ // Update Memory Config HOB size which will be used by SaveMemoryConfig
+ //
+ // bugbug PlatformInfoHob->MemData.MemConfigSize = sizeof(MRC_PARAMS_SAVE_RESTORE);
+
+ //
+ // Enable ICH IOAPIC
+ //
+ PlatformInfoHob->SysData.SysIoApicEnable = ICH_IOAPIC;
+
+ DEBUG ((EFI_D_ERROR, "PlatformFlavor: %x (%x=tablet,%x=mobile,%x=desktop)\n", PlatformInfoHob->PlatformFlavor,FlavorTablet,FlavorMobile,FlavorDesktop));
+
+ //
+ // Get Platform Info and fill the Hob
+ //
+ PlatformInfoHob->RevisonId = PLATFORM_INFO_HOB_REVISION;
+
+ //
+ // Get GPIO table
+ //
+ //
+ // Program GPIO
+ //
+ Status = MultiPlatformGpioProgram (PeiServices, PlatformInfoHob);
+
+ return EFI_SUCCESS;
+}
diff --git a/BraswellPlatformPkg/Common/Library/MultiPlatformLib/MultiPlatformLib.h b/BraswellPlatformPkg/Common/Library/MultiPlatformLib/MultiPlatformLib.h new file mode 100644 index 0000000000..abf07049e6 --- /dev/null +++ b/BraswellPlatformPkg/Common/Library/MultiPlatformLib/MultiPlatformLib.h @@ -0,0 +1,81 @@ +/** @file
+ Multiplatform initialization header file.
+ This file includes package header files, library classes.
+
+ Copyright (c) 2013 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _MULTIPLATFORM_LIB_H_
+#define _MULTIPLATFORM_LIB_H_
+
+//////////////////////////////////////////////////////////////////////
+#define LEN_64M 0x4000000
+//
+// Default PCI32 resource size
+//
+#define RES_MEM32_MIN_LEN 0x38000000
+
+#define RES_IO_BASE 0x0D00
+#define RES_IO_LIMIT 0xFFFF
+#define MRC_DATA_REQUIRED_FROM_OUTSIDE
+//////////////////////////////////////////////////////////////////////
+#include <PiDxe.h>
+#include <Library/BaseLib.h>
+#include <FrameworkPei.h>
+
+#include "PlatformBaseAddresses.h"
+#include "PchAccess.h"
+#include "CpuRegs.h"
+#include "Platform.h"
+
+#include <Ppi/Stall.h>
+#include <Guid/SetupVariable.h>
+#include <Ppi/AtaController.h>
+#include <Ppi/FindFv.h>
+#include <Ppi/BootInRecoveryMode.h>
+#include <Ppi/ReadOnlyVariable2.h>
+#include <Ppi/Capsule.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/PcdLib.h>
+#include <Library/IoLib.h>
+#include <Library/HobLib.h>
+#include <Library/BaseLib.h>
+#include <IndustryStandard/Pci22.h>
+#include <Guid/FirmwareFileSystem.h>
+#include <Guid/MemoryTypeInformation.h>
+#include <Ppi/Cache.h>
+#include <Ppi/Reset.h>
+#include <Ppi/EndOfPeiPhase.h>
+#include <Ppi/MemoryDiscovered.h>
+#include <Guid/GlobalVariable.h>
+#include <Ppi/RecoveryModule.h>
+#include <Ppi/DeviceRecoveryModulePei.h>
+#include <Guid/Capsule.h>
+#include <Guid/RecoveryDevice.h>
+#include <Ppi/MasterBootMode.h>
+#include <Guid/PlatformInfo.h>
+#include <Library/I2CLib.h>
+
+EFI_STATUS
+MultiPlatformGpioTableInit (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PLATFORM_INFO_HOB *PlatformInfoHob
+ );
+
+EFI_STATUS
+MultiPlatformGpioProgram (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PLATFORM_INFO_HOB *PlatformInfoHob
+ );
+
+#endif
diff --git a/BraswellPlatformPkg/Common/Library/MultiPlatformLib/MultiPlatformLib.inf b/BraswellPlatformPkg/Common/Library/MultiPlatformLib/MultiPlatformLib.inf new file mode 100644 index 0000000000..dffa148d9d --- /dev/null +++ b/BraswellPlatformPkg/Common/Library/MultiPlatformLib/MultiPlatformLib.inf @@ -0,0 +1,62 @@ +## @file
+# Platform configuration detail infomation.
+#
+# Getting/setting platform info, such as GPIO, Clkgen, Jumper, OEMID, SSID/SVID.
+#
+# Copyright (c) 2013 - 2015, Intel Corporation. All rights reserved.<BR>
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php.
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = MultiPlatformLib
+ FILE_GUID = AB83A52B-B44A-462c-B099-444CC0ED274D
+ MODULE_TYPE = PEIM
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = MultiPlatformLib
+ PI_SPECIFICATION_VERSION = 0x0001000A
+
+[Sources]
+ MultiPlatformLib.c
+ MultiPlatformLib.h
+ BoardIdentify.c
+
+#GPIO
+ BswBoardGpios/BoardGpios.c
+ BswBoardGpios/BoardGpios.h
+
+[Guids]
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ BraswellPlatformPkg/BraswellPlatformPkg.dec
+ IntelFrameworkPkg/IntelFrameworkPkg.dec
+ ChvRefCodePkg/ChvRefCodePkg.dec
+
+
+[LibraryClasses]
+ DebugLib
+ HobLib
+ IoLib
+ PeiKscLib
+ I2CLibPei
+ GpioLib
+
+[Ppis]
+ gEfiPeiReadOnlyVariable2PpiGuid ## CONSUMES
+ gEfiPeiSmbus2PpiGuid ## NOTIFY
+
+[Pcd.common]
+ gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## CONSUMES
+
+ gEfiEdkIIPlatformTokenSpaceGuid.PcdPlatformInfo
+ gEfiEdkIIPlatformTokenSpaceGuid.PcdGpioInitFunc
diff --git a/BraswellPlatformPkg/Common/Library/PchSmmLib/CommonHeader.h b/BraswellPlatformPkg/Common/Library/PchSmmLib/CommonHeader.h new file mode 100644 index 0000000000..63a4147438 --- /dev/null +++ b/BraswellPlatformPkg/Common/Library/PchSmmLib/CommonHeader.h @@ -0,0 +1,35 @@ +/** @file
+ Common header file shared by all source files.
+ This file includes package header files, library classes and protocol, PPI & GUID definitions.
+
+ Copyright (c) 2007 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __COMMON_HEADER_H_
+#define __COMMON_HEADER_H_
+
+#include <Base.h>
+
+#include <Library/TimerLib.h>
+#include <Library/BaseLib.h>
+#include <Library/IoLib.h>
+#include <Library/PcdLib.h>
+#include <Library/DebugLib.h>
+
+#define R_PCH_ACPI_SMI_EN 0x30
+#define B_PCH_ACPI_APMC_EN 0x00000020
+#define B_PCH_ACPI_EOS 0x00000002
+#define B_PCH_ACPI_GBL_SMI_EN 0x00000001
+#define R_PCH_ACPI_SMI_STS 0x34
+#define B_PCH_ACPI_APM_STS 0x00000020
+
+#endif
diff --git a/BraswellPlatformPkg/Common/Library/PchSmmLib/PchSmmLib.c b/BraswellPlatformPkg/Common/Library/PchSmmLib/PchSmmLib.c new file mode 100644 index 0000000000..987f40b0d8 --- /dev/null +++ b/BraswellPlatformPkg/Common/Library/PchSmmLib/PchSmmLib.c @@ -0,0 +1,148 @@ +/** @file
+ PCH Smm Library Services that implements both S/W SMI generation and detection.
+
+ Copyright (c) 2007 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "CommonHeader.h"
+
+/**
+ Triggers a run time or boot time SMI.
+ This function triggers a software SMM interrupt and set the APMC status with an 8-bit Data.
+
+ @param Data The value to set the APMC status.
+
+**/
+VOID
+InternalTriggerSmi (
+ IN UINT8 Data
+ )
+{
+ ASSERT(FALSE);
+}
+
+/**
+ Triggers an SMI at boot time.
+ This function triggers a software SMM interrupt at boot time.
+
+**/
+VOID
+EFIAPI
+TriggerBootServiceSoftwareSmi (
+ VOID
+ )
+{
+ ASSERT(FALSE);
+}
+
+/**
+ Triggers an SMI at run time.
+ This function triggers a software SMM interrupt at run time.
+
+**/
+VOID
+EFIAPI
+TriggerRuntimeSoftwareSmi (
+ VOID
+ )
+{
+ ASSERT(FALSE);
+}
+
+/**
+ Gets the software SMI data.
+
+ This function tests if a software SMM interrupt happens. If a software SMI happens,
+ it retrieves the SMM data and returns it as a non-negative value; otherwise a negative
+ value is returned.
+
+ @return Data The data retrieved from SMM data port in case of a software SMI;
+ otherwise a negative value.
+
+**/
+INTN
+InternalGetSwSmiData (
+ VOID
+ )
+{
+ ASSERT(FALSE);
+ return -1;
+}
+
+/**
+ Test if a boot time software SMI happened.
+
+ This function tests if a software SMM interrupt happened. If a software SMM interrupt happened and
+ it was triggered at boot time, it returns TRUE. Otherwise, it returns FALSE.
+
+ @retval TRUE A software SMI triggered at boot time happened.
+ @retval FLASE No software SMI happened or the software SMI was triggered at run time.
+
+**/
+BOOLEAN
+EFIAPI
+IsBootServiceSoftwareSmi (
+ VOID
+ )
+{
+ ASSERT(FALSE);
+ return FALSE;
+}
+
+/**
+ Test if a run time software SMI happened.
+
+ This function tests if a software SMM interrupt happened. If a software SMM interrupt happened and
+ it was triggered at run time, it returns TRUE. Otherwise, it returns FALSE.
+
+ @retval TRUE A software SMI triggered at run time happened.
+ @retval FLASE No software SMI happened or the software SMI was triggered at boot time.
+
+**/
+BOOLEAN
+EFIAPI
+IsRuntimeSoftwareSmi (
+ VOID
+ )
+{
+ ASSERT(FALSE);
+ return FALSE;
+}
+
+/**
+ Clear APM SMI Status Bit; Set the EOS bit.
+
+**/
+VOID
+EFIAPI
+ClearSmi (
+ VOID
+ )
+{
+ UINT16 PmBase;
+
+ //
+ // Get PMBase
+ //
+ PmBase = PcdGet16 (PcdPchAcpiIoPortBaseAddress);
+
+ //
+ // Clear the APM SMI Status Bit
+ //
+ IoWrite16 (PmBase + R_PCH_ACPI_SMI_STS, B_PCH_ACPI_APM_STS);
+
+ //
+ // Set the EOS Bit
+ //
+ IoOr32 (PmBase + R_PCH_ACPI_SMI_EN, B_PCH_ACPI_EOS);
+}
+
diff --git a/BraswellPlatformPkg/Common/Library/PchSmmLib/PchSmmLib.inf b/BraswellPlatformPkg/Common/Library/PchSmmLib/PchSmmLib.inf new file mode 100644 index 0000000000..63a837f7f4 --- /dev/null +++ b/BraswellPlatformPkg/Common/Library/PchSmmLib/PchSmmLib.inf @@ -0,0 +1,49 @@ +## @file
+# Component description file for Intel Ich7 SMM Library.
+#
+# ICH SMM Library that layers on top of the I/O Library to directly
+# access SMM power management registers.
+#
+# Copyright (c) 2007 - 2015, Intel Corporation. All rights reserved.<BR>
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php.
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = PchSmmLib
+ FILE_GUID = A6A16CCB-91B0-42f4-B4F3-D17D7A5662E6
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = SmmLib
+
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = IA32 X64 IPF EBC
+#
+
+[Sources]
+ PchSmmLib.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ ChvRefCodePkg/ChvRefCodePkg.dec
+ BraswellPlatformPkg/BraswellPlatformPkg.dec
+
+[LibraryClasses]
+ PcdLib
+ IoLib
+
+[Pcd]
+ gEfiPchTokenSpaceGuid.PcdPchAcpiIoPortBaseAddress ## CONSUMES
+
+
diff --git a/BraswellPlatformPkg/Common/Library/PlatformBdsLib/BdsPlatform.c b/BraswellPlatformPkg/Common/Library/PlatformBdsLib/BdsPlatform.c new file mode 100644 index 0000000000..db0778417b --- /dev/null +++ b/BraswellPlatformPkg/Common/Library/PlatformBdsLib/BdsPlatform.c @@ -0,0 +1,2927 @@ +/** @file
+ This file include all platform action which can be customized by IBV/OEM.
+
+ Copyright (c) 2004 - 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "BdsPlatform.h"
+#include <Guid/SetupVariable.h>
+#include <Library/TcgPhysicalPresenceLib.h>
+#include <Library/TrEEPhysicalPresenceLib.h>
+#include <TianoApi.h>
+#include <PlatformBaseAddresses.h>
+#include <Protocol/GlobalNvsArea.h>
+#include <Library/DxeServicesTableLib.h>
+#include <Protocol/BlockIo.h>
+#include <PchRegs/PchRegsPcu.h>
+#include <Library/S3BootScriptLib.h>
+#include "PchAccess.h"
+#include "PchRegs/PchRegsSata.h"
+#include <Library/SerialPortLib.h>
+#include <Library/DebugLib.h>
+#include <Library/GenericBdsLib/InternalBdsLib.h>
+#include <Library/GenericBdsLib/String.h>
+#include <Library/NetLib.h>
+
+EFI_GUID *ConnectDriverTable[] = {
+ &gEfiMmioDeviceProtocolGuid,
+};
+
+//
+// Memory Mapped PCI Access macros
+//
+#define PCH_PCI_EXPRESS_BASE_ADDRESS ((UINTN)PcdGet64(PcdPciExpressBaseAddress))
+
+#define SHELL_ENVIRONMENT_INTERFACE_PROTOCOL \
+ { \
+ 0x47c7b221, 0xc42a, 0x11d2, 0x8e, 0x57, 0x0, 0xa0, 0xc9, 0x69, 0x72, 0x3b \
+ }
+VOID *mShellImageCallbackReg = NULL;
+
+EFI_USER_PROFILE_HANDLE mCurrentUser = NULL;
+EFI_EVENT mHotKeyTimerEvent = NULL;
+EFI_EVENT mHitHotkeyEvent = NULL;
+EFI_EVENT mUsbKeyboardConnectEvent = NULL;
+BOOLEAN mHotKeyPressed = FALSE;
+VOID *mHitHotkeyRegistration;
+
+#define KEYBOARD_TIMER_INTERVAL 20000 // 0.02s
+
+VOID
+ConnectUSBController (
+ VOID
+ );
+
+EFI_STATUS
+PlatformBdsConnectSimpleConsole (
+ IN BDS_CONSOLE_CONNECT_ENTRY *PlatformConsole
+);
+
+VOID
+BootIntoFirmwareInterface(
+ VOID
+ );
+
+VOID
+EFIAPI
+PlatformBdsInitHotKeyEvent (
+ VOID
+ );
+
+VOID
+EFIAPI
+InternalBdsEmptyCallbackFuntion (
+ IN EFI_EVENT Event,
+ IN VOID *Context
+ )
+{
+ return;
+}
+
+
+VOID
+EFIAPI
+DisableAhciCtlr (
+ IN EFI_EVENT Event,
+ IN VOID *Context
+ )
+{
+ UINT32 PmcDisableAddress;
+ UINT8 SataStorageAmount;
+ UINT32 SataBase;
+ UINT16 SataPortStatus;
+
+ DEBUG ((EFI_D_INFO, "Disable AHCI event is signalled\n"));
+ SataStorageAmount = 0;
+ SataBase = *(UINT32*) Context;
+
+ //
+ // BayTrail-M EDS chapter 16 ---- PCI IO Register Offset 92 (SATA Port Control and Status)
+ //
+ SataPortStatus = MmioRead16 (SataBase + R_PCH_SATA_PCS);
+
+ //
+ // Bit 8 EN: Port 0 Present
+ //
+ if ((SataPortStatus & 0x100) == 0x100) {
+ SataStorageAmount++;
+ }
+
+ //
+ // Bit 9 EN: Port 1 Present
+ //
+ if ((SataPortStatus & 0x200) == 0x200) {
+ SataStorageAmount++;
+ }
+
+ //
+ // Disable SATA controller when it sets to AHCI mode without carrying any devices
+ // in order to prevent AHCI yellow bang under Win device manager.
+ //
+ if (SataStorageAmount == 0) {
+ PmcDisableAddress = (MmioRead32 ((PCH_PCI_EXPRESS_BASE_ADDRESS + (UINT32) (31 << 15)) + R_PCH_LPC_PMC_BASE) & B_PCH_LPC_PMC_BASE_BAR) + R_PCH_PMC_FUNC_DIS;
+ MmioOr32 (PmcDisableAddress, B_PCH_PMC_FUNC_DIS_SATA);
+ S3BootScriptSaveMemWrite (
+ EfiBootScriptWidthUint32,
+ (UINTN) PmcDisableAddress,
+ 1,
+ (VOID *) (UINTN) PmcDisableAddress
+ );
+ }
+}
+
+VOID
+InstallReadyToLock (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+ EFI_HANDLE Handle;
+ EFI_SMM_ACCESS2_PROTOCOL *SmmAccess;
+ EFI_ACPI_S3_SAVE_PROTOCOL *AcpiS3Save;
+ EFI_EVENT EndOfDxeEvent;
+
+ //
+ // Install DxeSmmReadyToLock protocol prior to the processing of boot options
+ //
+ Status = gBS->LocateProtocol (
+ &gEfiSmmAccess2ProtocolGuid,
+ NULL,
+ (VOID **) &SmmAccess
+ );
+ if (!EFI_ERROR (Status)) {
+
+ //
+ // Prepare S3 information, this MUST be done before DxeSmmReadyToLock
+ //
+ Status = gBS->LocateProtocol (
+ &gEfiAcpiS3SaveProtocolGuid,
+ NULL,
+ (VOID **) &AcpiS3Save
+ );
+ if (!EFI_ERROR (Status)) {
+ AcpiS3Save->S3Save (AcpiS3Save, NULL);
+ }
+
+ Handle = NULL;
+ Status = gBS->InstallProtocolInterface (
+ &Handle,
+ &gExitPmAuthProtocolGuid,
+ EFI_NATIVE_INTERFACE,
+ NULL
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // For code which follows PI 1.2.1, callback created for gExitPmAuthProtocolGuid
+ // is now replaced by/registered on gEfiEndOfDxeEventGroupGuid event
+ //
+ // keep the ExPmAuth in case there're still events on ExPmAuth
+ //
+ Status = gBS->CreateEventEx (
+ EVT_NOTIFY_SIGNAL,
+ TPL_CALLBACK,
+ InternalBdsEmptyCallbackFuntion,
+ NULL,
+ &gEfiEndOfDxeEventGroupGuid,
+ &EndOfDxeEvent
+ );
+ ASSERT_EFI_ERROR (Status);
+ gBS->SignalEvent (EndOfDxeEvent);
+ gBS->CloseEvent (EndOfDxeEvent);
+ DEBUG((EFI_D_INFO,"All EndOfDxe callbacks have returned successfully\n"));
+
+ Handle = NULL;
+ Status = gBS->InstallProtocolInterface (
+ &Handle,
+ &gEfiDxeSmmReadyToLockProtocolGuid,
+ EFI_NATIVE_INTERFACE,
+ NULL
+ );
+ ASSERT_EFI_ERROR (Status);
+ }
+
+ return ;
+}
+
+VOID
+EFIAPI
+ShellImageCallback (
+ IN EFI_EVENT Event,
+ IN VOID *Context
+ )
+{
+ BdsSetConsoleMode (TRUE);
+ DEBUG ((EFI_D_INFO, "BdsEntry ShellImageCallback \n"));
+}
+
+//
+// BDS Platform Functions
+//
+/**
+ Platform Bds init. Incude the platform firmware vendor, revision
+ and so crc check.
+
+ @param VOID
+
+ @retval None.
+
+**/
+VOID
+EFIAPI
+PlatformBdsInit (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+ EFI_EVENT ShellImageEvent;
+ EFI_GUID ShellEnvProtocol = SHELL_ENVIRONMENT_INTERFACE_PROTOCOL;
+
+ #ifdef __GNUC__
+ SerialPortWrite((UINT8 *)">>>>BdsEntry[GCC]\r\n", 19);
+ #else
+ SerialPortWrite((UINT8 *)">>>>BdsEntry\r\n", 14);
+ #endif
+ BdsLibSaveMemoryTypeInformation ();
+
+ //
+ // Before user authentication, the user identification devices need be connected
+ // from the platform customized device paths
+ //
+ PlatformBdsConnectAuthDevice ();
+
+ //
+ // As console is not ready, the auto logon user will be identified.
+ //
+ BdsLibUserIdentify (&mCurrentUser);
+
+ //
+ // Change Gop mode when boot into Shell
+ //
+ if (mShellImageCallbackReg == NULL) {
+ Status = gBS->CreateEvent (
+ EFI_EVENT_NOTIFY_SIGNAL,
+ EFI_TPL_CALLBACK,
+ ShellImageCallback,
+ NULL,
+ &ShellImageEvent
+ );
+ if (!EFI_ERROR (Status)) {
+ Status = gBS->RegisterProtocolNotify (
+ &ShellEnvProtocol,
+ ShellImageEvent,
+ &mShellImageCallbackReg
+ );
+
+ DEBUG ((EFI_D_INFO, "BdsEntry ShellImageCallback \n"));
+ }
+ }
+}
+
+EFI_STATUS
+GetGopDevicePath (
+ IN EFI_DEVICE_PATH_PROTOCOL *PciDevicePath,
+ OUT EFI_DEVICE_PATH_PROTOCOL **GopDevicePath
+ )
+{
+ UINTN Index;
+ EFI_STATUS Status;
+ EFI_HANDLE PciDeviceHandle;
+ EFI_DEVICE_PATH_PROTOCOL *TempDevicePath;
+ EFI_DEVICE_PATH_PROTOCOL *TempPciDevicePath;
+ UINTN GopHandleCount;
+ EFI_HANDLE *GopHandleBuffer;
+
+ SYSTEM_CONFIGURATION mSystemConfiguration;
+
+ if (PciDevicePath == NULL || GopDevicePath == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ //
+ // Initialize the GopDevicePath to be PciDevicePath
+ //
+ *GopDevicePath = PciDevicePath;
+ TempPciDevicePath = PciDevicePath;
+
+ Status = gBS->LocateDevicePath (
+ &gEfiDevicePathProtocolGuid,
+ &TempPciDevicePath,
+ &PciDeviceHandle
+ );
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ //
+ // Try to connect this handle, so that GOP dirver could start on this
+ // device and create child handles with GraphicsOutput Protocol installed
+ // on them, then we get device paths of these child handles and select
+ // them as possible console device.
+ //
+
+ //
+ // Select display devices
+ //
+ CopyMem (&mSystemConfiguration, PcdGetPtr (PcdSystemConfiguration), sizeof(SYSTEM_CONFIGURATION));
+
+ if (mSystemConfiguration.BootDisplayDevice != 0x0) {
+ ACPI_ADR_DEVICE_PATH AcpiAdr;
+ EFI_DEVICE_PATH_PROTOCOL *MyDevicePath = NULL;
+
+ AcpiAdr.Header.Type = ACPI_DEVICE_PATH;
+ AcpiAdr.Header.SubType = ACPI_ADR_DP;
+
+ switch (mSystemConfiguration.BootDisplayDevice) {
+ case 1:
+ AcpiAdr.ADR= ACPI_DISPLAY_ADR (1, 0, 0, 1, 0, ACPI_ADR_DISPLAY_TYPE_VGA, PORT_CRT, 0); //CRT Device
+ break;
+ case 2:
+ AcpiAdr.ADR= ACPI_DISPLAY_ADR (1, 0, 0, 1, 0, ACPI_ADR_DISPLAY_TYPE_EXTERNAL_DIGITAL, PORT_B_HDMI, 0); //HDMI Device Port B
+ break;
+ case 3:
+ AcpiAdr.ADR= ACPI_DISPLAY_ADR (1, 0, 0, 1, 0, ACPI_ADR_DISPLAY_TYPE_EXTERNAL_DIGITAL, PORT_B_DP, 0); //DP PortB
+ break;
+ case 4:
+ AcpiAdr.ADR= ACPI_DISPLAY_ADR (1, 0, 0, 1, 0, ACPI_ADR_DISPLAY_TYPE_EXTERNAL_DIGITAL, PORT_C_DP, 0); //DP PortC
+ break;
+ case 5:
+ AcpiAdr.ADR= ACPI_DISPLAY_ADR (1, 0, 0, 1, 0, ACPI_ADR_DISPLAY_TYPE_INTERNAL_DIGITAL, PORT_C_DP, 0); //eDP Port C
+ break;
+ case 6:
+ AcpiAdr.ADR= ACPI_DISPLAY_ADR (1, 0, 0, 1, 0, ACPI_ADR_DISPLAY_TYPE_INTERNAL_DIGITAL, PORT_MIPI_A, 0); //DSI Port A
+ break;
+ case 7:
+ AcpiAdr.ADR= ACPI_DISPLAY_ADR (1, 0, 0, 1, 0, ACPI_ADR_DISPLAY_TYPE_INTERNAL_DIGITAL, PORT_MIPI_C, 0); //DSI Port C
+ break;
+ default:
+ AcpiAdr.ADR= ACPI_DISPLAY_ADR (1, 0, 0, 1, 0, ACPI_ADR_DISPLAY_TYPE_VGA, PORT_CRT, 0);
+ break;
+ }
+
+ SetDevicePathNodeLength (&AcpiAdr.Header, sizeof (ACPI_ADR_DEVICE_PATH));
+
+ MyDevicePath = AppendDevicePathNode(MyDevicePath, (EFI_DEVICE_PATH_PROTOCOL*)&AcpiAdr);
+
+ gBS->ConnectController (
+ PciDeviceHandle,
+ NULL,
+ MyDevicePath,
+ FALSE
+ );
+
+ FreePool(MyDevicePath);
+ }
+ else
+ {
+ gBS->ConnectController (
+ PciDeviceHandle,
+ NULL,
+ NULL,
+ FALSE
+ );
+ }
+
+ Status = gBS->LocateHandleBuffer (
+ ByProtocol,
+ &gEfiGraphicsOutputProtocolGuid,
+ NULL,
+ &GopHandleCount,
+ &GopHandleBuffer
+ );
+ if (!EFI_ERROR (Status)) {
+ //
+ // Add all the child handles as possible Console Device
+ //
+ for (Index = 0; Index < GopHandleCount; Index++) {
+ Status = gBS->HandleProtocol (
+ GopHandleBuffer[Index],
+ &gEfiDevicePathProtocolGuid,
+ (VOID**)&TempDevicePath
+ );
+ if (EFI_ERROR (Status)) {
+ continue;
+ }
+ if (CompareMem (
+ PciDevicePath,
+ TempDevicePath,
+ GetDevicePathSize (PciDevicePath) - END_DEVICE_PATH_LENGTH
+ ) == 0) {
+ //
+ // In current implementation, we only enable one of the child handles
+ // as console device, i.e. sotre one of the child handle's device
+ // path to variable "ConOut"
+ // In futhure, we could select all child handles to be console device
+ //
+ *GopDevicePath = TempDevicePath;
+ }
+ }
+ gBS->FreePool (GopHandleBuffer);
+ }
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Search out all the platform pci or agp video device. The function may will
+ find multiple video device, and return all enabled device path.
+
+ @param PlugInPciVgaDevicePath Return the platform plug in pci video device
+ path if the system have plug in pci video device.
+ @param OnboardPciVgaDevicePath Return the platform active agp video device path
+ if the system have plug in agp video device or on
+ chip agp device.
+
+ @retval EFI_SUCCSS Get all platform active video device path.
+ @retval EFI_STATUS Return the status of gBS->LocateDevicePath (),
+ gBS->ConnectController (),
+ and gBS->LocateHandleBuffer ().
+
+**/
+EFI_STATUS
+GetPlugInPciVgaDevicePath (
+ IN OUT EFI_DEVICE_PATH_PROTOCOL **PlugInPciVgaDevicePath,
+ IN OUT EFI_DEVICE_PATH_PROTOCOL **OnboardPciVgaDevicePath
+ )
+{
+ EFI_STATUS Status;
+ EFI_HANDLE RootHandle;
+ UINTN HandleCount;
+ EFI_HANDLE *HandleBuffer;
+ UINTN Index;
+ UINTN Index1;
+ EFI_DEVICE_PATH_PROTOCOL *DevicePath;
+ BOOLEAN PlugInPciVga;
+ EFI_PCI_IO_PROTOCOL *PciIo;
+ PCI_TYPE00 Pci;
+
+ DevicePath = NULL;
+ PlugInPciVga = TRUE;
+ HandleCount = 0;
+ HandleBuffer = NULL;
+
+ //
+ // Make all the PCI_IO protocols on PCI Seg 0 show up
+ //
+ BdsLibConnectDevicePath (gPlatformRootBridges[0]);
+
+ Status = gBS->LocateDevicePath (
+ &gEfiDevicePathProtocolGuid,
+ &gPlatformRootBridges[0],
+ &RootHandle
+ );
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ Status = gBS->ConnectController (
+ RootHandle,
+ NULL,
+ NULL,
+ FALSE
+ );
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ //
+ // Start to check all the pci io to find all possible VGA device
+ //
+ HandleCount = 0;
+ HandleBuffer = NULL;
+ Status = gBS->LocateHandleBuffer (
+ ByProtocol,
+ &gEfiPciIoProtocolGuid,
+ NULL,
+ &HandleCount,
+ &HandleBuffer
+ );
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ for (Index = 0; Index < HandleCount; Index++) {
+ Status = gBS->HandleProtocol (
+ HandleBuffer[Index],
+ &gEfiPciIoProtocolGuid,
+ (VOID**)&PciIo
+ );
+ if (!EFI_ERROR (Status)) {
+
+ //
+ // Check for all VGA device
+ //
+ Status = PciIo->Pci.Read (
+ PciIo,
+ EfiPciIoWidthUint32,
+ 0,
+ sizeof (Pci) / sizeof (UINT32),
+ &Pci
+ );
+ if (EFI_ERROR (Status)) {
+ continue;
+ }
+
+ //
+ // Here we decide which VGA device to enable in PCI bus
+ //
+ // The first plugin PCI VGA card device will be present as PCI VGA
+ // The onchip AGP or AGP card will be present as AGP VGA
+ //
+ if (!IS_PCI_VGA (&Pci)) {
+ continue;
+ }
+
+ //
+ // Set the device as the possible console out device,
+ //
+ // Below code will make every VGA device to be one
+ // of the possibe console out device
+ //
+ PlugInPciVga = TRUE;
+ gBS->HandleProtocol (
+ HandleBuffer[Index],
+ &gEfiDevicePathProtocolGuid,
+ (VOID**)&DevicePath
+ );
+
+ Index1 = 0;
+
+ while (gPlatformAllPossiblePciVgaConsole[Index1] != NULL) {
+ if (CompareMem (
+ DevicePath,
+ gPlatformAllPossiblePciVgaConsole[Index1],
+ GetDevicePathSize (gPlatformAllPossiblePciVgaConsole[Index1])
+ ) == 0) {
+
+ //
+ // This device is an AGP device
+ //
+ *OnboardPciVgaDevicePath = DevicePath;
+ PlugInPciVga = FALSE;
+ break;
+ }
+
+ Index1 ++;
+ }
+
+ if (PlugInPciVga) {
+ *PlugInPciVgaDevicePath = DevicePath;
+ }
+ }
+ }
+
+ FreePool (HandleBuffer);
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Find the platform active vga, and base on the policy to enable the vga as
+ the console out device. The policy is driven by one setup variable "VBIOS".
+
+ None.
+
+ @param EFI_UNSUPPORTED There is no active vga device
+
+ @retval EFI_STATUS Return the status of BdsLibGetVariableAndSize ()
+
+**/
+EFI_STATUS
+PlatformBdsForceActiveVga (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+ EFI_DEVICE_PATH_PROTOCOL *PlugInPciVgaDevicePath;
+ EFI_DEVICE_PATH_PROTOCOL *OnboardPciVgaDevicePath;
+ EFI_DEVICE_PATH_PROTOCOL *DevicePathFirst;
+ EFI_DEVICE_PATH_PROTOCOL *DevicePathSecond;
+ EFI_DEVICE_PATH_PROTOCOL *GopDevicePath;
+ SYSTEM_CONFIGURATION mSystemConfiguration;
+
+ Status = EFI_SUCCESS;
+ PlugInPciVgaDevicePath = NULL;
+ OnboardPciVgaDevicePath = NULL;
+
+ //
+ // Check the policy which is the first enabled VGA
+ //
+ GetPlugInPciVgaDevicePath (&PlugInPciVgaDevicePath, &OnboardPciVgaDevicePath);
+
+ if (PlugInPciVgaDevicePath == NULL && OnboardPciVgaDevicePath == NULL) {
+ return EFI_UNSUPPORTED;
+ }
+
+ CopyMem (&mSystemConfiguration, PcdGetPtr (PcdSystemConfiguration), sizeof(SYSTEM_CONFIGURATION));
+
+ if ((PlugInPciVgaDevicePath == NULL && OnboardPciVgaDevicePath != NULL) ) {
+ DEBUG ((EFI_D_ERROR,"Update onboard PCI VGA ...\n"));
+ DevicePathFirst = OnboardPciVgaDevicePath;
+ DevicePathSecond = PlugInPciVgaDevicePath;
+ goto UpdateConOut;
+ }
+ if(OnboardPciVgaDevicePath != NULL && mSystemConfiguration.PrimaryVideoAdaptor == 0) {
+ DEBUG ((EFI_D_ERROR,"Update onboard PCI VGA When set primary!!!...\n"));
+ DevicePathFirst = OnboardPciVgaDevicePath;
+ DevicePathSecond = PlugInPciVgaDevicePath;
+ goto UpdateConOut;
+ }
+
+ DEBUG ((EFI_D_ERROR,"Update plug in PCI VGA ...\n"));
+ DevicePathFirst = PlugInPciVgaDevicePath;
+ DevicePathSecond = OnboardPciVgaDevicePath;
+
+UpdateConOut:
+ GetGopDevicePath (DevicePathFirst, &GopDevicePath);
+ DevicePathFirst = GopDevicePath;
+
+ Status = BdsLibUpdateConsoleVariable (
+ L"ConOut",
+ DevicePathFirst,
+ DevicePathSecond
+ );
+
+ return Status;
+}
+
+VOID
+UpdateConsoleResolution (
+ VOID
+ )
+{
+ UINT32 HorizontalResolution;
+ UINT32 VerticalResolution;
+ SYSTEM_CONFIGURATION SystemConfiguration;
+
+ HorizontalResolution = PcdGet32 (PcdSetupVideoHorizontalResolution);
+ VerticalResolution = PcdGet32 (PcdSetupVideoVerticalResolution);
+
+ CopyMem (&SystemConfiguration, PcdGetPtr (PcdSystemConfiguration), sizeof(SYSTEM_CONFIGURATION));
+
+ switch (SystemConfiguration.IgdFlatPanel) {
+
+ case 0:
+ //
+ // Use the detault PCD values.
+ //
+ break;
+
+ case 1:
+ HorizontalResolution = 640;
+ VerticalResolution = 480;
+ break;
+
+ case 2:
+ HorizontalResolution = 800;
+ VerticalResolution = 600;
+ break;
+
+ case 3:
+ HorizontalResolution = 1024;
+ VerticalResolution = 768;
+ break;
+
+ case 4:
+ HorizontalResolution = 1280;
+ VerticalResolution = 1024;
+ break;
+
+ case 5:
+ HorizontalResolution = 1366;
+ VerticalResolution = 768;
+ break;
+
+ case 6:
+ HorizontalResolution = 1680;
+ VerticalResolution = 1050;
+ break;
+
+ case 7:
+ HorizontalResolution = 1920;
+ VerticalResolution = 1200;
+ break;
+
+ case 8:
+ HorizontalResolution = 1280;
+ VerticalResolution = 800;
+ break;
+ }
+
+ PcdSet32 (PcdSetupVideoHorizontalResolution, HorizontalResolution);
+ PcdSet32 (PcdSetupVideoVerticalResolution, VerticalResolution);
+ DEBUG ((EFI_D_ERROR, "HorizontalResolution = %x; VerticalResolution = %x", HorizontalResolution, VerticalResolution));
+
+ return;
+}
+
+/**
+ Connect the predefined platform default console device. Always try to find
+ and enable the vga device if have.
+
+ @param PlatformConsole Predfined platform default console device array.
+
+ @retval EFI_SUCCESS Success connect at least one ConIn and ConOut
+ device, there must have one ConOut device is
+ active vga device.
+
+ @retval EFI_STATUS Return the status of
+ BdsLibConnectAllDefaultConsoles ()
+
+**/
+EFI_STATUS
+PlatformBdsConnectConsole (
+ IN BDS_CONSOLE_CONNECT_ENTRY *PlatformConsole
+)
+{
+ EFI_STATUS Status;
+ UINTN Index;
+ EFI_DEVICE_PATH_PROTOCOL *VarConout;
+ EFI_DEVICE_PATH_PROTOCOL *VarConin;
+ UINTN DevicePathSize;
+
+ UpdateConsoleResolution();
+
+ Index = 0;
+ Status = EFI_SUCCESS;
+ DevicePathSize = 0;
+ VarConout = BdsLibGetVariableAndSize (
+ L"ConOut",
+ &gEfiGlobalVariableGuid,
+ &DevicePathSize
+ );
+ VarConin = BdsLibGetVariableAndSize (
+ L"ConIn",
+ &gEfiGlobalVariableGuid,
+ &DevicePathSize
+ );
+ if (VarConout == NULL || VarConin == NULL) {
+ //
+ // Have chance to connect the platform default console,
+ // the platform default console is the minimue device group
+ // the platform should support
+ //
+ while (PlatformConsole[Index].DevicePath != NULL) {
+
+ //
+ // Update the console variable with the connect type
+ //
+ if ((PlatformConsole[Index].ConnectType & CONSOLE_IN) == CONSOLE_IN) {
+ BdsLibUpdateConsoleVariable (L"ConIn", PlatformConsole[Index].DevicePath, NULL);
+ }
+
+ if ((PlatformConsole[Index].ConnectType & CONSOLE_OUT) == CONSOLE_OUT) {
+ BdsLibUpdateConsoleVariable (L"ConOut", PlatformConsole[Index].DevicePath, NULL);
+ }
+
+ if ((PlatformConsole[Index].ConnectType & STD_ERROR) == STD_ERROR) {
+ BdsLibUpdateConsoleVariable (L"ErrOut", PlatformConsole[Index].DevicePath, NULL);
+ }
+
+ Index ++;
+ }
+ }
+
+ //
+ // Make sure we have at least one active VGA, and have the right
+ // active VGA in console variable
+ //
+ Status = PlatformBdsForceActiveVga ();
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ DEBUG ((EFI_D_INFO, "DISPLAY INIT DONE\n"));
+
+ //
+ // Connect the all the default console with current console variable
+ //
+ Status = BdsLibConnectAllDefaultConsoles ();
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Connect with predeined platform connect sequence,
+ the OEM/IBV can customize with their own connect sequence.
+
+ @param None.
+
+ @retval None.
+
+**/
+VOID
+PlatformBdsConnectSequence (
+ VOID
+ )
+{
+ UINTN Index;
+
+ Index = 0;
+
+ //
+ // Here we can get the customized platform connect sequence
+ // Notes: we can connect with new variable which record the
+ // last time boots connect device path sequence
+ //
+ while (gPlatformConnectSequence[Index] != NULL) {
+
+ //
+ // Build the platform boot option
+ //
+ BdsLibConnectDevicePath (gPlatformConnectSequence[Index]);
+ Index ++;
+ }
+
+ //
+ // Just use the simple policy to connect all devices
+ // There should be no difference between debug tip and release tip, or it will be extremely hard to debug.
+ //
+ // There is case that IdeController driver will write boot script in driver model Start() function. It will be rejected by boot script save.
+ // It is only found when DEBUG disabled, because we are using BdsLibConnectAll() when DEBUG enabled.
+ //
+ // So we use BdsLibConnectAll() here to make sure IdeController.Start() is invoked before InstallReadyToLock().
+ // We may also consider to connect SataController only later if needed.
+ //
+ BdsLibConnectAll ();
+}
+
+/**
+ Load the predefined driver option, OEM/IBV can customize this
+ to load their own drivers
+
+ @param BdsDriverLists The header of the driver option link list.
+
+ @retval None.
+
+**/
+VOID
+PlatformBdsGetDriverOption (
+ IN OUT LIST_ENTRY *BdsDriverLists
+ )
+{
+ UINTN Index;
+
+ Index = 0;
+
+ //
+ // Here we can get the customized platform driver option
+ //
+ while (gPlatformDriverOption[Index] != NULL) {
+
+ //
+ // Build the platform boot option
+ //
+ BdsLibRegisterNewOption (BdsDriverLists, gPlatformDriverOption[Index], NULL, L"DriverOrder");
+ Index ++;
+ }
+
+}
+
+/**
+ This function is used for some critical time if the the system
+ have no any boot option, and there is no time out for user to add
+ the new boot option. This can also treat as the platform default
+ boot option.
+
+ @param BdsBootOptionList The header of the boot option link list.
+
+ @retval None.
+
+**/
+VOID
+PlatformBdsPredictBootOption (
+ IN OUT LIST_ENTRY *BdsBootOptionList
+ )
+{
+ UINTN Index;
+
+ Index = 0;
+
+ //
+ // Here give chance to get platform boot option data
+ //
+ while (gPlatformBootOption[Index] != NULL) {
+
+ //
+ // Build the platform boot option
+ //
+ BdsLibRegisterNewOption (BdsBootOptionList, gPlatformBootOption[Index], NULL, L"BootOrder");
+ Index ++;
+ }
+}
+
+/**
+ Perform the platform diagnostic, such like test memory. OEM/IBV also
+ can customize this fuction to support specific platform diagnostic.
+
+ @param MemoryTestLevel The memory test intensive level
+ @param QuietBoot Indicate if need to enable the quiet boot
+ @param BaseMemoryTest A pointer to BdsMemoryTest()
+
+ @retval None.
+
+**/
+VOID
+PlatformBdsDiagnostics (
+ IN EXTENDMEM_COVERAGE_LEVEL MemoryTestLevel,
+ IN BOOLEAN QuietBoot,
+ IN BASEM_MEMORY_TEST BaseMemoryTest
+ )
+{
+ EFI_STATUS Status;
+
+ //
+ // Here we can decide if we need to show
+ // the diagnostics screen
+ // Notes: this quiet boot code should be remove
+ // from the graphic lib
+ //
+ if (QuietBoot) {
+ EnableQuietBoot (PcdGetPtr(PcdLogoFile));
+
+ //
+ // Perform system diagnostic
+ //
+ Status = BaseMemoryTest (MemoryTestLevel);
+ if (EFI_ERROR (Status)) {
+ DisableQuietBoot ();
+ }
+
+ return;
+ }
+
+ //
+ // Perform system diagnostic
+ //
+ Status = BaseMemoryTest (MemoryTestLevel);
+}
+
+/**
+ For EFI boot option, BDS separate them as six types:
+ 1. Network - The boot option points to the SimpleNetworkProtocol device.
+ Bds will try to automatically create this type boot option when enumerate.
+ 2. Shell - The boot option points to internal flash shell.
+ Bds will try to automatically create this type boot option when enumerate.
+ 3. Removable BlockIo - The boot option only points to the removable media
+ device, like USB flash disk, DVD, Floppy etc.
+ These device should contain a *removable* blockIo
+ protocol in their device handle.
+ Bds will try to automatically create this type boot option
+ when enumerate.
+ 4. Fixed BlockIo - The boot option only points to a Fixed blockIo device,
+ like HardDisk.
+ These device should contain a *fixed* blockIo
+ protocol in their device handle.
+ BDS will skip fixed blockIo devices, and NOT
+ automatically create boot option for them. But BDS
+ will help to delete those fixed blockIo boot option,
+ whose description rule conflict with other auto-created
+ boot options.
+ 5. Non-BlockIo Simplefile - The boot option points to a device whose handle
+ has SimpleFileSystem Protocol, but has no blockio
+ protocol. These devices do not offer blockIo
+ protocol, but BDS still can get the
+ \EFI\BOOT\boot{machinename}.EFI by SimpleFileSystem
+ Protocol.
+ 6. File - The boot option points to a file. These boot options are usually
+ created by user manually or OS loader. BDS will not delete or modify
+ these boot options.
+
+ This function will enumerate all possible boot device in the system, and
+ automatically create boot options for Network, Shell, Removable BlockIo,
+ and Non-BlockIo Simplefile devices.
+ It will only execute once of every boot.
+
+ @param BdsBootOptionList The header of the link list which indexed all
+ current boot options
+
+ @retval EFI_SUCCESS Finished all the boot device enumerate and create
+ the boot option base on that boot device
+
+ @retval EFI_OUT_OF_RESOURCES Failed to enumerate the boot device and create the boot option list
+**/
+EFI_STATUS
+EFIAPI
+PlatformBdsLibEnumerateAllBootOption (
+ IN OUT LIST_ENTRY *BdsBootOptionList
+ )
+{
+ EFI_STATUS Status;
+ UINT16 FloppyNumber;
+ UINT16 HarddriveNumber;
+ UINT16 CdromNumber;
+ UINT16 UsbNumber;
+ UINT16 MiscNumber;
+ UINT16 ScsiNumber;
+ UINT16 NonBlockNumber;
+ UINTN NumberBlockIoHandles;
+ EFI_HANDLE *BlockIoHandles;
+ EFI_BLOCK_IO_PROTOCOL *BlkIo;
+ BOOLEAN Removable[2];
+ UINTN RemovableIndex;
+ UINTN Index;
+ UINTN NumOfLoadFileHandles;
+ EFI_HANDLE *LoadFileHandles;
+ UINTN FvHandleCount;
+ EFI_HANDLE *FvHandleBuffer;
+ EFI_FV_FILETYPE Type;
+ UINTN Size;
+ EFI_FV_FILE_ATTRIBUTES Attributes;
+ UINT32 AuthenticationStatus;
+ EFI_FIRMWARE_VOLUME2_PROTOCOL *Fv;
+ EFI_DEVICE_PATH_PROTOCOL *DevicePath;
+ UINTN DevicePathType;
+ CHAR16 Buffer[40];
+ EFI_HANDLE *FileSystemHandles;
+ UINTN NumberFileSystemHandles;
+ BOOLEAN NeedDelete;
+ EFI_IMAGE_DOS_HEADER DosHeader;
+ CHAR8 *PlatLang;
+ CHAR8 *LastLang;
+ EFI_IMAGE_OPTIONAL_HEADER_UNION HdrData;
+ EFI_IMAGE_OPTIONAL_HEADER_PTR_UNION Hdr;
+ CHAR16 *MacStr;
+ CHAR16 *IPverStr;
+ EFI_HANDLE *NetworkHandles;
+ UINTN BufferSize;
+
+ FloppyNumber = 0;
+ HarddriveNumber = 0;
+ CdromNumber = 0;
+ UsbNumber = 0;
+ MiscNumber = 0;
+ ScsiNumber = 0;
+ PlatLang = NULL;
+ LastLang = NULL;
+ ZeroMem (Buffer, sizeof (Buffer));
+
+ //
+ // If the boot device enumerate happened, just get the boot
+ // device from the boot order variable
+ //
+ if (mEnumBootDevice) {
+ GetVariable2 (LAST_ENUM_LANGUAGE_VARIABLE_NAME, &gLastEnumLangGuid, (VOID**)&LastLang, NULL);
+ GetEfiGlobalVariable2 (L"PlatformLang", (VOID**)&PlatLang, NULL);
+ ASSERT (PlatLang != NULL);
+ if ((LastLang != NULL) && (AsciiStrCmp (LastLang, PlatLang) == 0)) {
+ Status = BdsLibBuildOptionFromVar (BdsBootOptionList, L"BootOrder");
+ FreePool (LastLang);
+ FreePool (PlatLang);
+ return Status;
+ } else {
+ Status = gRT->SetVariable (
+ LAST_ENUM_LANGUAGE_VARIABLE_NAME,
+ &gLastEnumLangGuid,
+ EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_NON_VOLATILE,
+ AsciiStrSize (PlatLang),
+ PlatLang
+ );
+ //
+ // Failure to set the variable only impacts the performance next time enumerating the boot options.
+ //
+
+ if (LastLang != NULL) {
+ FreePool (LastLang);
+ }
+ FreePool (PlatLang);
+ }
+ }
+
+ //
+ // Notes: this dirty code is to get the legacy boot option from the
+ // BBS table and create to variable as the EFI boot option, it should
+ // be removed after the CSM can provide legacy boot option directly
+ //
+ REFRESH_LEGACY_BOOT_OPTIONS;
+
+ //
+ // Delete invalid boot option
+ //
+ BdsDeleteAllInvalidEfiBootOption ();
+
+ //
+ // Parse removable media followed by fixed media.
+ // The Removable[] array is used by the for-loop below to create removable media boot options
+ // at first, and then to create fixed media boot options.
+ //
+ Removable[0] = FALSE;
+ Removable[1] = TRUE;
+
+ gBS->LocateHandleBuffer (
+ ByProtocol,
+ &gEfiBlockIoProtocolGuid,
+ NULL,
+ &NumberBlockIoHandles,
+ &BlockIoHandles
+ );
+
+ for (RemovableIndex = 0; RemovableIndex < 2; RemovableIndex++) {
+ for (Index = 0; Index < NumberBlockIoHandles; Index++) {
+ Status = gBS->HandleProtocol (
+ BlockIoHandles[Index],
+ &gEfiBlockIoProtocolGuid,
+ (VOID **) &BlkIo
+ );
+ //
+ // skip the logical partition
+ //
+ if (EFI_ERROR (Status) || BlkIo->Media->LogicalPartition) {
+ continue;
+ }
+
+ //
+ // firstly fixed block io then the removable block io
+ //
+ if (BlkIo->Media->RemovableMedia == Removable[RemovableIndex]) {
+ continue;
+ }
+ DevicePath = DevicePathFromHandle (BlockIoHandles[Index]);
+ DevicePathType = BdsGetBootTypeFromDevicePath (DevicePath);
+
+ switch (DevicePathType) {
+ case BDS_EFI_ACPI_FLOPPY_BOOT:
+ if (FloppyNumber != 0) {
+ UnicodeSPrint (Buffer, sizeof (Buffer), L"%s %d", BdsLibGetStringById (STRING_TOKEN (STR_DESCRIPTION_FLOPPY)), FloppyNumber);
+ } else {
+ UnicodeSPrint (Buffer, sizeof (Buffer), L"%s", BdsLibGetStringById (STRING_TOKEN (STR_DESCRIPTION_FLOPPY)));
+ }
+ BdsLibBuildOptionFromHandle (BlockIoHandles[Index], BdsBootOptionList, Buffer);
+ FloppyNumber++;
+ break;
+
+ //
+ // Assume a removable SATA device should be the DVD/CD device, a fixed SATA device should be the Hard Drive device.
+ //
+ case BDS_EFI_MESSAGE_ATAPI_BOOT:
+ case BDS_EFI_MESSAGE_SATA_BOOT:
+ if (BlkIo->Media->RemovableMedia) {
+ if (CdromNumber != 0) {
+ UnicodeSPrint (Buffer, sizeof (Buffer), L"%s %d", BdsLibGetStringById (STRING_TOKEN (STR_DESCRIPTION_CD_DVD)), CdromNumber);
+ } else {
+ UnicodeSPrint (Buffer, sizeof (Buffer), L"%s", BdsLibGetStringById (STRING_TOKEN (STR_DESCRIPTION_CD_DVD)));
+ }
+ CdromNumber++;
+ } else {
+ if (HarddriveNumber != 0) {
+ UnicodeSPrint (Buffer, sizeof (Buffer), L"%s %d", BdsLibGetStringById (STRING_TOKEN (STR_DESCRIPTION_HARDDRIVE)), HarddriveNumber);
+ } else {
+ UnicodeSPrint (Buffer, sizeof (Buffer), L"%s", BdsLibGetStringById (STRING_TOKEN (STR_DESCRIPTION_HARDDRIVE)));
+ }
+ HarddriveNumber++;
+ }
+ DEBUG ((DEBUG_INFO | DEBUG_LOAD, "Buffer: %S\n", Buffer));
+ BdsLibBuildOptionFromHandle (BlockIoHandles[Index], BdsBootOptionList, Buffer);
+ break;
+
+ case BDS_EFI_MESSAGE_USB_DEVICE_BOOT:
+ if (UsbNumber != 0) {
+ UnicodeSPrint (Buffer, sizeof (Buffer), L"%s %d", BdsLibGetStringById (STRING_TOKEN (STR_DESCRIPTION_USB)), UsbNumber);
+ } else {
+ UnicodeSPrint (Buffer, sizeof (Buffer), L"%s", BdsLibGetStringById (STRING_TOKEN (STR_DESCRIPTION_USB)));
+ }
+ BdsLibBuildOptionFromHandle (BlockIoHandles[Index], BdsBootOptionList, Buffer);
+ UsbNumber++;
+ break;
+
+ case BDS_EFI_MESSAGE_SCSI_BOOT:
+ if (ScsiNumber != 0) {
+ UnicodeSPrint (Buffer, sizeof (Buffer), L"%s %d", BdsLibGetStringById (STRING_TOKEN (STR_DESCRIPTION_SCSI)), ScsiNumber);
+ } else {
+ UnicodeSPrint (Buffer, sizeof (Buffer), L"%s", BdsLibGetStringById (STRING_TOKEN (STR_DESCRIPTION_SCSI)));
+ }
+ BdsLibBuildOptionFromHandle (BlockIoHandles[Index], BdsBootOptionList, Buffer);
+ ScsiNumber++;
+ break;
+
+ case BDS_EFI_MESSAGE_MISC_BOOT:
+ default:
+ if (MiscNumber != 0) {
+ UnicodeSPrint (Buffer, sizeof (Buffer), L"%s %d", BdsLibGetStringById (STRING_TOKEN (STR_DESCRIPTION_MISC)), MiscNumber);
+ } else {
+ UnicodeSPrint (Buffer, sizeof (Buffer), L"%s", BdsLibGetStringById (STRING_TOKEN (STR_DESCRIPTION_MISC)));
+ }
+ BdsLibBuildOptionFromHandle (BlockIoHandles[Index], BdsBootOptionList, Buffer);
+ MiscNumber++;
+ break;
+ }
+ }
+ }
+
+ if (NumberBlockIoHandles != 0) {
+ FreePool (BlockIoHandles);
+ }
+
+ //
+ // If there is simple file protocol which does not consume block Io protocol, create a boot option for it here.
+ //
+ NonBlockNumber = 0;
+ gBS->LocateHandleBuffer (
+ ByProtocol,
+ &gEfiSimpleFileSystemProtocolGuid,
+ NULL,
+ &NumberFileSystemHandles,
+ &FileSystemHandles
+ );
+ for (Index = 0; Index < NumberFileSystemHandles; Index++) {
+ Status = gBS->HandleProtocol (
+ FileSystemHandles[Index],
+ &gEfiBlockIoProtocolGuid,
+ (VOID **) &BlkIo
+ );
+ if (!EFI_ERROR (Status)) {
+ //
+ // Skip if the file system handle supports a BlkIo protocol,
+ //
+ continue;
+ }
+
+ //
+ // Do the removable Media thing. \EFI\BOOT\boot{machinename}.EFI
+ // machinename is ia32, ia64, x64, ...
+ //
+ Hdr.Union = &HdrData;
+ NeedDelete = TRUE;
+ Status = BdsLibGetImageHeader (
+ FileSystemHandles[Index],
+ EFI_REMOVABLE_MEDIA_FILE_NAME,
+ &DosHeader,
+ Hdr
+ );
+ if (!EFI_ERROR (Status) &&
+ EFI_IMAGE_MACHINE_TYPE_SUPPORTED (Hdr.Pe32->FileHeader.Machine) &&
+ Hdr.Pe32->OptionalHeader.Subsystem == EFI_IMAGE_SUBSYSTEM_EFI_APPLICATION) {
+ NeedDelete = FALSE;
+ }
+
+ if (NeedDelete) {
+ //
+ // No such file or the file is not a EFI application, delete this boot option
+ //
+ BdsLibDeleteOptionFromHandle (FileSystemHandles[Index]);
+ } else {
+ if (NonBlockNumber != 0) {
+ UnicodeSPrint (Buffer, sizeof (Buffer), L"%s %d", BdsLibGetStringById (STRING_TOKEN (STR_DESCRIPTION_NON_BLOCK)), NonBlockNumber);
+ } else {
+ UnicodeSPrint (Buffer, sizeof (Buffer), L"%s", BdsLibGetStringById (STRING_TOKEN (STR_DESCRIPTION_NON_BLOCK)));
+ }
+ BdsLibBuildOptionFromHandle (FileSystemHandles[Index], BdsBootOptionList, Buffer);
+ NonBlockNumber++;
+ }
+ }
+
+ if (NumberFileSystemHandles != 0) {
+ FreePool (FileSystemHandles);
+ }
+
+ //
+ // Check if we have on flash shell
+ //
+ gBS->LocateHandleBuffer (
+ ByProtocol,
+ &gEfiFirmwareVolume2ProtocolGuid,
+ NULL,
+ &FvHandleCount,
+ &FvHandleBuffer
+ );
+ for (Index = 0; Index < FvHandleCount; Index++) {
+ gBS->HandleProtocol (
+ FvHandleBuffer[Index],
+ &gEfiFirmwareVolume2ProtocolGuid,
+ (VOID **) &Fv
+ );
+
+ Status = Fv->ReadFile (
+ Fv,
+ PcdGetPtr(PcdShellFile),
+ NULL,
+ &Size,
+ &Type,
+ &Attributes,
+ &AuthenticationStatus
+ );
+ if (EFI_ERROR (Status)) {
+ //
+ // Skip if no shell file in the FV
+ //
+ continue;
+ }
+ //
+ // Build the shell boot option
+ //
+ BdsLibBuildOptionFromShell (FvHandleBuffer[Index], BdsBootOptionList);
+ }
+
+ if (FvHandleCount != 0) {
+ FreePool (FvHandleBuffer);
+ }
+
+ //
+ // Parse Network Boot Device
+ //
+ NumOfLoadFileHandles = 0;
+ //
+ // Search Load File protocol for PXE boot option.
+ //
+ gBS->LocateHandleBuffer (
+ ByProtocol,
+ &gEfiLoadFileProtocolGuid,
+ NULL,
+ &NumOfLoadFileHandles,
+ &LoadFileHandles
+ );
+
+ for (Index = 0; Index < NumOfLoadFileHandles; Index++) {
+
+//
+//Locate EFI_DEVICE_PATH_PROTOCOL to dynamically get IPv4/IPv6 protocol information.
+//
+
+ Status = gBS->HandleProtocol (
+ LoadFileHandles[Index],
+ &gEfiDevicePathProtocolGuid,
+ (VOID **) &DevicePath
+ );
+
+ ASSERT_EFI_ERROR (Status);
+
+ while (!IsDevicePathEnd (DevicePath)) {
+ if ((DevicePath->Type == MESSAGING_DEVICE_PATH) &&
+ (DevicePath->SubType == MSG_IPv4_DP)) {
+
+ //
+ //Get handle infomation
+ //
+ BufferSize = 0;
+ NetworkHandles = NULL;
+ Status = gBS->LocateHandle (
+ ByProtocol,
+ &gEfiSimpleNetworkProtocolGuid,
+ NULL,
+ &BufferSize,
+ NetworkHandles
+ );
+
+ if (Status == EFI_BUFFER_TOO_SMALL) {
+ NetworkHandles = AllocateZeroPool(BufferSize);
+ if (NetworkHandles == NULL) {
+ return (EFI_OUT_OF_RESOURCES);
+ }
+ Status = gBS->LocateHandle(
+ ByProtocol,
+ &gEfiSimpleNetworkProtocolGuid,
+ NULL,
+ &BufferSize,
+ NetworkHandles
+ );
+ }
+
+ //
+ //Get the MAC string
+ //
+ Status = NetLibGetMacString (
+ *NetworkHandles,
+ NULL,
+ &MacStr
+ );
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+ IPverStr = L" IPv4";
+ UnicodeSPrint (Buffer, sizeof (Buffer), L"%s%s%s", BdsLibGetStringById (STRING_TOKEN (STR_DESCRIPTION_NETWORK)),MacStr,IPverStr);
+ break;
+ }
+ if((DevicePath->Type == MESSAGING_DEVICE_PATH) &&
+ (DevicePath->SubType == MSG_IPv6_DP)) {
+
+ //
+ //Get handle infomation
+ //
+ BufferSize = 0;
+ NetworkHandles = NULL;
+ Status = gBS->LocateHandle (
+ ByProtocol,
+ &gEfiSimpleNetworkProtocolGuid,
+ NULL,
+ &BufferSize,
+ NetworkHandles
+ );
+
+ if (Status == EFI_BUFFER_TOO_SMALL) {
+ NetworkHandles = AllocateZeroPool(BufferSize);
+ if (NetworkHandles == NULL) {
+ return (EFI_OUT_OF_RESOURCES);
+ }
+ Status = gBS->LocateHandle(
+ ByProtocol,
+ &gEfiSimpleNetworkProtocolGuid,
+ NULL,
+ &BufferSize,
+ NetworkHandles
+ );
+ }
+
+ //
+ //Get the MAC string
+ //
+ Status = NetLibGetMacString (
+ *NetworkHandles,
+ NULL,
+ &MacStr
+ );
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+ IPverStr = L" IPv6";
+ UnicodeSPrint (Buffer, sizeof (Buffer), L"%s%s%s", BdsLibGetStringById (STRING_TOKEN (STR_DESCRIPTION_NETWORK)),MacStr,IPverStr);
+ break;
+ }
+ DevicePath = NextDevicePathNode (DevicePath);
+ }
+
+ BdsLibBuildOptionFromHandle (LoadFileHandles[Index], BdsBootOptionList, Buffer);
+ }
+
+ if (NumOfLoadFileHandles != 0) {
+ FreePool (LoadFileHandles);
+ }
+
+ //
+ // Check if we have on flash shell
+ //
+ /* gBS->LocateHandleBuffer (
+ ByProtocol,
+ &gEfiFirmwareVolume2ProtocolGuid,
+ NULL,
+ &FvHandleCount,
+ &FvHandleBuffer
+ );
+ for (Index = 0; Index < FvHandleCount; Index++) {
+ gBS->HandleProtocol (
+ FvHandleBuffer[Index],
+ &gEfiFirmwareVolume2ProtocolGuid,
+ (VOID **) &Fv
+ );
+
+ Status = Fv->ReadFile (
+ Fv,
+ PcdGetPtr(PcdShellFile),
+ NULL,
+ &Size,
+ &Type,
+ &Attributes,
+ &AuthenticationStatus
+ );
+ if (EFI_ERROR (Status)) {
+ //
+ // Skip if no shell file in the FV
+ //
+ continue;
+ }
+ //
+ // Build the shell boot option
+ //
+ BdsLibBuildOptionFromShell (FvHandleBuffer[Index], BdsBootOptionList);
+ }
+
+ if (FvHandleCount != 0) {
+ FreePool (FvHandleBuffer);
+ } */
+
+ //
+ // Make sure every boot only have one time
+ // boot device enumerate
+ //
+ Status = BdsLibBuildOptionFromVar (BdsBootOptionList, L"BootOrder");
+ mEnumBootDevice = TRUE;
+
+ return Status;
+}
+
+/**
+ The function will excute with as the platform policy, current policy
+ is driven by boot mode. IBV/OEM can customize this code for their specific
+ policy action.
+
+ @param DriverOptionList - The header of the driver option link list
+ @param BootOptionList - The header of the boot option link list
+ @param ProcessCapsules - A pointer to ProcessCapsules()
+ @param BaseMemoryTest - A pointer to BaseMemoryTest()
+
+ @retval None.
+
+**/
+VOID
+EFIAPI
+PlatformBdsPolicyBehavior (
+ IN OUT LIST_ENTRY *DriverOptionList,
+ IN OUT LIST_ENTRY *BootOptionList,
+ IN PROCESS_CAPSULES ProcessCapsules,
+ IN BASEM_MEMORY_TEST BaseMemoryTest
+ )
+{
+ EFI_STATUS Status;
+ UINT16 Timeout;
+ EFI_BOOT_MODE BootMode;
+ BOOLEAN DeferredImageExist;
+ UINTN Index;
+ CHAR16 CapsuleVarName[36];
+ CHAR16 *TempVarName;
+ SYSTEM_CONFIGURATION SystemConfiguration;
+ BOOLEAN SetVariableFlag;
+ PLATFORM_PCI_DEVICE_PATH *EmmcBootDevPath;
+ EFI_GLOBAL_NVS_AREA_PROTOCOL *GlobalNvsArea;
+ EFI_HANDLE FvProtocolHandle;
+ UINTN HandleCount;
+ EFI_HANDLE *HandleBuffer;
+ UINTN Index1;
+ //UINTN SataPciRegBase = 0;
+ //UINT16 SataModeSelect = 0;
+ //VOID *RegistrationExitPmAuth = NULL;
+ //EFI_EVENT Event;
+ BOOLEAN IsFirstBoot;
+ UINT16 *BootOrder;
+ UINTN BootOrderSize;
+
+ Timeout = PcdGet16 (PcdPlatformBootTimeOut);
+ if (Timeout > 10 ) {
+ //we think the Timeout variable is corrupted
+ Timeout = 10;
+ }
+
+ CopyMem (&SystemConfiguration, PcdGetPtr (PcdSystemConfiguration), sizeof(SYSTEM_CONFIGURATION));
+
+ //
+ // Load the driver option as the driver option list
+ //
+ PlatformBdsGetDriverOption (DriverOptionList);
+
+ //
+ // Get current Boot Mode
+ //
+ BootMode = GetBootModeHob();
+
+ //
+ // Clear all the capsule variables CapsuleUpdateData, CapsuleUpdateData1, CapsuleUpdateData2...
+ // as early as possible which will avoid the next time boot after the capsule update
+ // will still into the capsule loop
+ //
+ StrCpy (CapsuleVarName, EFI_CAPSULE_VARIABLE_NAME);
+ TempVarName = CapsuleVarName + StrLen (CapsuleVarName);
+ Index = 0;
+ SetVariableFlag = TRUE;
+ while (SetVariableFlag) {
+ if (Index > 0) {
+ UnicodeValueToString (TempVarName, 0, Index, 0);
+ }
+ Status = gRT->SetVariable (
+ CapsuleVarName,
+ &gEfiCapsuleVendorGuid,
+ EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_RUNTIME_ACCESS |
+ EFI_VARIABLE_BOOTSERVICE_ACCESS,
+ 0,
+ (VOID *)NULL
+ );
+ if (EFI_ERROR (Status)) {
+ //
+ // There is no capsule variables, quit
+ //
+ SetVariableFlag = FALSE;
+ continue;
+ }
+ Index++;
+ }
+
+ //
+ // No deferred images exist by default
+ //
+ DeferredImageExist = FALSE;
+ if ((BootMode != BOOT_WITH_MINIMAL_CONFIGURATION) && (PcdGet32(PcdFlashFvShellSize) > 0)){
+ gDS->ProcessFirmwareVolume (
+ (VOID *)(UINTN)PcdGet32(PcdFlashFvShellBase),
+ PcdGet32(PcdFlashFvShellSize),
+ &FvProtocolHandle
+ );
+ }
+
+ if (SystemConfiguration.FastBoot == 1) {
+ BootOrder = BdsLibGetVariableAndSize (
+ L"BootOrder",
+ &gEfiGlobalVariableGuid,
+ &BootOrderSize
+ );
+ if ((BootOrder != NULL) && (BootMode != BOOT_ON_FLASH_UPDATE)) {
+ //
+ // BootOrder exist, it means system has boot before. We can do fast boot.
+ //
+ BootMode = BOOT_WITH_MINIMAL_CONFIGURATION;
+ }
+ }
+
+ //
+ // Use eMMC to boot OS and turn on AHCI, when SATA HDD is diconnected,
+ // SATA AHCI CTLR device will show yellow bang, implement this solution to solve it.
+ //
+ /*SataPciRegBase = MmPciAddress (0, 0, PCI_DEVICE_NUMBER_PCH_SATA, 0, 0);
+ SataModeSelect = MmioRead16 (SataPciRegBase + R_PCH_SATA_MAP) & B_PCH_SATA_MAP_SMS_MASK;
+ Status = EFI_SUCCESS;
+ if (SataModeSelect != V_PCH_SATA_MAP_SMS_IDE) {
+ Status = gBS->CreateEvent (
+ EVT_NOTIFY_SIGNAL,
+ TPL_CALLBACK,
+ DisableAhciCtlr,
+ &SataPciRegBase,
+ &Event
+ );
+ if (!EFI_ERROR (Status)) {
+ Status = gBS->RegisterProtocolNotify (
+ &gExitPmAuthProtocolGuid,
+ Event,
+ &RegistrationExitPmAuth
+ );
+ }
+ } BUGBUG ZWEI4 */
+
+ switch (BootMode) {
+
+ case BOOT_WITH_MINIMAL_CONFIGURATION:
+ PlatformBdsInitHotKeyEvent ();
+ PlatformBdsConnectSimpleConsole (gPlatformSimpleConsole);
+
+ //
+ // Check to see if it's needed to dispatch more DXE drivers.
+ //
+ for (Index = 0; Index < sizeof(ConnectDriverTable)/sizeof(EFI_GUID *); Index++) {
+ Status = gBS->LocateHandleBuffer (
+ ByProtocol,
+ ConnectDriverTable[Index],
+ NULL,
+ &HandleCount,
+ &HandleBuffer
+ );
+ if (!EFI_ERROR (Status)) {
+ for (Index1 = 0; Index1 < HandleCount; Index1++) {
+ gBS->ConnectController (
+ HandleBuffer[Index1],
+ NULL,
+ NULL,
+ TRUE
+ );
+ }
+ }
+
+ if (HandleBuffer != NULL) {
+ FreePool (HandleBuffer);
+ }
+
+ gDS->Dispatch ();
+ }
+
+ //
+ // Locate the Global NVS Protocol.
+ //
+ Status = gBS->LocateProtocol (
+ &gEfiGlobalNvsAreaProtocolGuid,
+ NULL,
+ (void **)&GlobalNvsArea
+ );
+ if (GlobalNvsArea->Area->emmcVersion == 0){
+ EmmcBootDevPath = (PLATFORM_PCI_DEVICE_PATH *)gPlatformSimpleBootOption[0];
+ EmmcBootDevPath->PciDevice.Device = 0x10;
+ }
+
+ //
+ // Connect boot device here to give time to read keyboard.
+ //
+ BdsLibConnectDevicePath (gPlatformSimpleBootOption[0]);
+
+ //
+ // This is a workround for dectecting hotkey from USB keyboard.
+ //
+ gBS->Stall(KEYBOARD_TIMER_INTERVAL);
+
+ if (mHotKeyTimerEvent != NULL) {
+ gBS->SetTimer (
+ mHotKeyTimerEvent,
+ TimerCancel,
+ 0
+ );
+ gBS->CloseEvent (mHotKeyTimerEvent);
+ mHotKeyTimerEvent = NULL;
+ }
+ if (mHotKeyPressed) {
+ //
+ // Skip show progress count down
+ //
+ Timeout = 0xFFFF;
+ goto FULL_CONFIGURATION;
+ }
+
+ if (SystemConfiguration.QuietBoot) {
+ EnableQuietBoot (PcdGetPtr(PcdLogoFile));
+ } else {
+ PlatformBdsDiagnostics (IGNORE, FALSE, BaseMemoryTest);
+ }
+
+ #ifdef TPM_ENABLED
+ TcgPhysicalPresenceLibProcessRequest();
+ #endif
+ #ifdef FTPM_ENABLE
+ TrEEPhysicalPresenceLibProcessRequest(NULL);
+ #endif
+ //
+ // Close boot script and install ready to lock
+ //
+ InstallReadyToLock ();
+
+ //
+ // Give one chance to enter the setup if we
+ // select Gummiboot "Reboot Into Firmware Interface" and Fast Boot is enabled.
+ //
+ BootIntoFirmwareInterface();
+ break;
+
+ case BOOT_ASSUMING_NO_CONFIGURATION_CHANGES:
+
+ //
+ // In no-configuration boot mode, we can connect the
+ // console directly.
+ //
+ BdsLibConnectAllDefaultConsoles ();
+ PlatformBdsDiagnostics (IGNORE, TRUE, BaseMemoryTest);
+
+ //
+ // Perform some platform specific connect sequence
+ //
+ PlatformBdsConnectSequence ();
+
+ //
+ // As console is ready, perform user identification again.
+ //
+ if (mCurrentUser == NULL) {
+ PlatformBdsUserIdentify (&mCurrentUser, &DeferredImageExist);
+ if (DeferredImageExist) {
+ //
+ // After user authentication, the deferred drivers was loaded again.
+ // Here, need to ensure the deferred images are connected.
+ //
+ BdsLibConnectAllDefaultConsoles ();
+ PlatformBdsConnectSequence ();
+ }
+ }
+
+ //
+ // Close boot script and install ready to lock
+ //
+ InstallReadyToLock ();
+
+ //
+ // Notes: current time out = 0 can not enter the
+ // front page
+ //
+ //PlatformBdsEnterFrontPageWithHotKey (Timeout, FALSE);
+
+ //
+ // Check the boot option with the boot option list
+ //
+ BdsLibBuildOptionFromVar (BootOptionList, L"BootOrder");
+ break;
+
+ case BOOT_ON_FLASH_UPDATE:
+
+ //
+ // Boot with the specific configuration
+ //
+ PlatformBdsConnectConsole (gPlatformConsole);
+ PlatformBdsDiagnostics (EXTENSIVE, FALSE, BaseMemoryTest);
+ BdsLibConnectAll ();
+
+ //
+ // Perform user identification
+ //
+ if (mCurrentUser == NULL) {
+ PlatformBdsUserIdentify (&mCurrentUser, &DeferredImageExist);
+ if (DeferredImageExist) {
+ //
+ // After user authentication, the deferred drivers was loaded again.
+ // Here, need to ensure the deferred images are connected.
+ //
+ BdsLibConnectAll ();
+ }
+ }
+
+ //
+ // Close boot script and install ready to lock
+ //
+ InstallReadyToLock ();
+
+ ProcessCapsules (BOOT_ON_FLASH_UPDATE);
+ break;
+
+ case BOOT_IN_RECOVERY_MODE:
+
+ //
+ // In recovery mode, just connect platform console
+ // and show up the front page
+ //
+ PlatformBdsConnectConsole (gPlatformConsole);
+ PlatformBdsDiagnostics (EXTENSIVE, FALSE, BaseMemoryTest);
+ BdsLibConnectAll ();
+
+ //
+ // Perform user identification
+ //
+ if (mCurrentUser == NULL) {
+ PlatformBdsUserIdentify (&mCurrentUser, &DeferredImageExist);
+ if (DeferredImageExist) {
+ //
+ // After user authentication, the deferred drivers was loaded again.
+ // Here, need to ensure the deferred drivers are connected.
+ //
+ BdsLibConnectAll ();
+ }
+ }
+
+ //
+ // Close boot script and install ready to lock
+ //
+ InstallReadyToLock ();
+
+ //
+ // In recovery boot mode, we still enter to the
+ // frong page now
+ //
+ PlatformBdsEnterFrontPageWithHotKey (Timeout, FALSE);
+ break;
+
+FULL_CONFIGURATION:
+ case BOOT_WITH_FULL_CONFIGURATION:
+ case BOOT_WITH_FULL_CONFIGURATION_PLUS_DIAGNOSTICS:
+ case BOOT_WITH_DEFAULT_SETTINGS:
+ default:
+
+ //
+ // Connect platform console
+ //
+ Status = PlatformBdsConnectConsole (gPlatformConsole);
+ if (EFI_ERROR (Status)) {
+
+ //
+ // Here OEM/IBV can customize with defined action
+ //
+ PlatformBdsNoConsoleAction ();
+ }
+
+ //
+ // Chenyunh[TODO]: This is Workgroud to show the fs for uSDcard,
+ // Need to root cause this issue.
+ //
+
+ //
+ // Perform some platform specific connect sequence
+ //
+ PlatformBdsConnectSequence ();
+ if (SystemConfiguration.QuietBoot) {
+ EnableQuietBoot (PcdGetPtr(PcdLogoFile));
+ } else {
+ PlatformBdsDiagnostics (IGNORE, FALSE, BaseMemoryTest);
+ }
+
+ //
+ // Do a pre-delay so Hard Disk can spin up and see more logo.
+ //
+ gBS->Stall(SystemConfiguration.HddPredelay * 1000000);
+
+ //
+ // Perform user identification
+ //
+ if (mCurrentUser == NULL) {
+ PlatformBdsUserIdentify (&mCurrentUser, &DeferredImageExist);
+ if (DeferredImageExist) {
+ //
+ // After user authentication, the deferred drivers was loaded again.
+ // Here, need to ensure the deferred drivers are connected.
+ //
+ Status = PlatformBdsConnectConsole (gPlatformConsole);
+ if (EFI_ERROR (Status)) {
+ PlatformBdsNoConsoleAction ();
+ }
+ PlatformBdsConnectSequence ();
+ }
+ }
+ #ifdef TPM_ENABLED
+ TcgPhysicalPresenceLibProcessRequest();
+ #endif
+ #ifdef FTPM_ENABLE
+ TrEEPhysicalPresenceLibProcessRequest(NULL);
+ #endif
+ //
+ // Close boot script and install ready to lock
+ //
+ InstallReadyToLock ();
+
+ //
+ // Here we have enough time to do the enumeration of boot device
+ //
+ PlatformBdsLibEnumerateAllBootOption (BootOptionList);
+
+ //
+ // Give one chance to enter the setup if we
+ // have the time out
+ //
+ PlatformBdsEnterFrontPageWithHotKey (Timeout, FALSE);
+
+ //
+ // Give one chance to enter the setup if we
+ // select Gummiboot "Reboot Into Firmware Interface"
+ //
+ BootIntoFirmwareInterface();
+
+ //
+ // In default boot mode, always find all boot
+ // option and do enumerate all the default boot option
+ //
+ if (Timeout == 0) {
+ BdsLibBuildOptionFromVar (BootOptionList, L"BootOrder");
+ if (IsListEmpty(BootOptionList)) {
+ PlatformBdsPredictBootOption (BootOptionList);
+ }
+
+ return;
+ }
+
+
+ break;
+ }
+
+ IsFirstBoot = PcdGetBool(PcdBootState);
+ if (IsFirstBoot) {
+ PcdSetBool(PcdBootState, FALSE);
+ }
+ return;
+
+}
+
+/**
+ Hook point after a boot attempt succeeds. We don't expect a boot option to
+ return, so the UEFI 2.0 specification defines that you will default to an
+ interactive mode and stop processing the BootOrder list in this case. This
+ is alos a platform implementation and can be customized by IBV/OEM.
+
+ @param Option Pointer to Boot Option that succeeded to boot.
+
+ @retval None.
+
+**/
+VOID
+EFIAPI
+PlatformBdsBootSuccess (
+ IN BDS_COMMON_OPTION *Option
+ )
+{
+ CHAR16 *TmpStr;
+
+ //
+ // If Boot returned with EFI_SUCCESS and there is not in the boot device
+ // select loop then we need to pop up a UI and wait for user input.
+ //
+ TmpStr = Option->StatusString;
+ if (TmpStr != NULL) {
+ BdsLibOutputStrings (gST->ConOut, TmpStr, Option->Description, L"\n\r", NULL);
+ FreePool(TmpStr);
+ }
+}
+
+/**
+ Hook point after a boot attempt fails.
+
+ @param Option - Pointer to Boot Option that failed to boot.
+ @param Status - Status returned from failed boot.
+ @param ExitData - Exit data returned from failed boot.
+ @param ExitDataSize - Exit data size returned from failed boot.
+
+ @retval None.
+
+**/
+VOID
+EFIAPI
+PlatformBdsBootFail (
+ IN BDS_COMMON_OPTION *Option,
+ IN EFI_STATUS Status,
+ IN CHAR16 *ExitData,
+ IN UINTN ExitDataSize
+ )
+{
+ CHAR16 *TmpStr;
+ EFI_HANDLE FvProtocolHandle;
+
+ //
+ // If Boot returned with failed status then we need to pop up a UI and wait
+ // for user input.
+ //
+ TmpStr = Option->StatusString;
+ if (TmpStr != NULL) {
+ BdsLibOutputStrings (gST->ConOut, TmpStr, Option->Description, L"\n\r", NULL);
+ FreePool(TmpStr);
+ }
+ if (PcdGet32(PcdFlashFvShellSize) > 0){
+ gDS->ProcessFirmwareVolume (
+ (VOID *)(UINTN)PcdGet32(PcdFlashFvShellBase),
+ PcdGet32(PcdFlashFvShellSize),
+ &FvProtocolHandle
+ );
+ }
+ PlatformBdsConnectSequence ();
+}
+
+/**
+ This function is remained for IBV/OEM to do some platform action,
+ if there no console device can be connected.
+
+ @param None.
+
+ @retval EFI_SUCCESS Direct return success now.
+
+**/
+EFI_STATUS
+PlatformBdsNoConsoleAction (
+ VOID
+ )
+{
+ return EFI_SUCCESS;
+}
+
+/**
+ This function locks the block
+
+ @param Base The base address flash region to be locked.
+
+**/
+VOID
+BdsLockFv (
+ IN EFI_PHYSICAL_ADDRESS Base
+ )
+{
+ EFI_FV_BLOCK_MAP_ENTRY *BlockMap;
+ EFI_FIRMWARE_VOLUME_HEADER *FvHeader;
+ EFI_PHYSICAL_ADDRESS BaseAddress;
+ UINT8 Data;
+ UINT32 BlockLength;
+ UINTN Index;
+
+ BaseAddress = Base - 0x400000 + 2;
+ FvHeader = (EFI_FIRMWARE_VOLUME_HEADER *) ((UINTN) (Base));
+ BlockMap = &(FvHeader->BlockMap[0]);
+
+ while ((BlockMap->NumBlocks != 0) && (BlockMap->Length != 0)) {
+ BlockLength = BlockMap->Length;
+ for (Index = 0; Index < BlockMap->NumBlocks; Index++) {
+ Data = MmioOr8 ((UINTN) BaseAddress, 0x03);
+ BaseAddress += BlockLength;
+ }
+ BlockMap++;
+ }
+}
+
+VOID
+EFIAPI
+PlatformBdsLockNonUpdatableFlash (
+ VOID
+ )
+{
+ EFI_PHYSICAL_ADDRESS Base;
+
+ Base = (EFI_PHYSICAL_ADDRESS) PcdGet32 (PcdFlashFvMainBase);
+ if (Base > 0) {
+ BdsLockFv (Base);
+ }
+
+ Base = (EFI_PHYSICAL_ADDRESS) PcdGet32 (PcdFlashFvRecoveryBase);
+ if (Base > 0) {
+ BdsLockFv (Base);
+ }
+}
+
+/**
+ Lock the ConsoleIn device in system table. All key
+ presses will be ignored until the Password is typed in. The only way to
+ disable the password is to type it in to a ConIn device.
+
+ @param Password Password used to lock ConIn device.
+
+ @retval EFI_SUCCESS lock the Console In Spliter virtual handle successfully.
+ @retval EFI_UNSUPPORTED Password not found
+
+**/
+EFI_STATUS
+EFIAPI
+LockKeyboards (
+ IN CHAR16 *Password
+ )
+{
+ return EFI_UNSUPPORTED;
+}
+
+/**
+ Connect the predefined platform default authentication devices.
+
+ This function connects the predefined device path for authentication device,
+ and if the predefined device path has child device path, the child handle will
+ be connected too. But the child handle of the child will not be connected.
+
+**/
+VOID
+EFIAPI
+PlatformBdsConnectAuthDevice (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+ UINTN Index;
+ UINTN HandleIndex;
+ UINTN HandleCount;
+ EFI_HANDLE *HandleBuffer;
+ EFI_DEVICE_PATH_PROTOCOL *ChildDevicePath;
+ EFI_USER_MANAGER_PROTOCOL *Manager;
+
+ Status = gBS->LocateProtocol (
+ &gEfiUserManagerProtocolGuid,
+ NULL,
+ (VOID **) &Manager
+ );
+ if (EFI_ERROR (Status)) {
+ //
+ // As user manager protocol is not installed, the authentication devices
+ // should not be connected.
+ //
+ return ;
+ }
+
+ Index = 0;
+ while (gUserAuthenticationDevice[Index] != NULL) {
+ //
+ // Connect the platform customized device paths
+ //
+ BdsLibConnectDevicePath (gUserAuthenticationDevice[Index]);
+ Index++;
+ }
+
+ //
+ // Find and connect the child device paths of the platform customized device paths
+ //
+ HandleBuffer = NULL;
+ for (Index = 0; gUserAuthenticationDevice[Index] != NULL; Index++) {
+ HandleCount = 0;
+ Status = gBS->LocateHandleBuffer (
+ AllHandles,
+ NULL,
+ NULL,
+ &HandleCount,
+ &HandleBuffer
+ );
+ ASSERT (!EFI_ERROR (Status));
+
+ //
+ // Find and connect the child device paths of gUserIdentificationDevice[Index]
+ //
+ for (HandleIndex = 0; HandleIndex < HandleCount; HandleIndex++) {
+ ChildDevicePath = NULL;
+ Status = gBS->HandleProtocol (
+ HandleBuffer[HandleIndex],
+ &gEfiDevicePathProtocolGuid,
+ (VOID **) &ChildDevicePath
+ );
+ if (EFI_ERROR (Status) || ChildDevicePath == NULL) {
+ continue;
+ }
+
+ if (CompareMem (
+ ChildDevicePath,
+ gUserAuthenticationDevice[Index],
+ (GetDevicePathSize (gUserAuthenticationDevice[Index]) - sizeof (EFI_DEVICE_PATH_PROTOCOL))
+ ) != 0) {
+ continue;
+ }
+ gBS->ConnectController (
+ HandleBuffer[HandleIndex],
+ NULL,
+ NULL,
+ TRUE
+ );
+ }
+ }
+
+ if (HandleBuffer != NULL) {
+ FreePool (HandleBuffer);
+ }
+}
+
+/**
+ This function is to identify a user, and return whether deferred images exist.
+
+ @param[out] User Point to user profile handle.
+ @param[out] DeferredImageExist On return, points to TRUE if the deferred image
+ exist or FALSE if it did not exist.
+
+**/
+VOID
+EFIAPI
+PlatformBdsUserIdentify (
+ OUT EFI_USER_PROFILE_HANDLE *User,
+ OUT BOOLEAN *DeferredImageExist
+ )
+{
+ EFI_STATUS Status;
+ EFI_DEFERRED_IMAGE_LOAD_PROTOCOL *DeferredImage;
+ UINTN HandleCount;
+ EFI_HANDLE *HandleBuf;
+ UINTN Index;
+ UINTN DriverIndex;
+ EFI_DEVICE_PATH_PROTOCOL *ImageDevicePath;
+ VOID *DriverImage;
+ UINTN ImageSize;
+ BOOLEAN BootOption;
+
+ //
+ // Perform user identification
+ //
+ do {
+ Status = BdsLibUserIdentify (User);
+ } while (EFI_ERROR (Status));
+
+ //
+ // After user authentication now, try to find whether deferred image exists
+ //
+ HandleCount = 0;
+ HandleBuf = NULL;
+ *DeferredImageExist = FALSE;
+ Status = gBS->LocateHandleBuffer (
+ ByProtocol,
+ &gEfiDeferredImageLoadProtocolGuid,
+ NULL,
+ &HandleCount,
+ &HandleBuf
+ );
+ if (EFI_ERROR (Status)) {
+ return ;
+ }
+
+ for (Index = 0; Index < HandleCount; Index++) {
+ Status = gBS->HandleProtocol (
+ HandleBuf[Index],
+ &gEfiDeferredImageLoadProtocolGuid,
+ (VOID **) &DeferredImage
+ );
+ if (!EFI_ERROR (Status)) {
+ //
+ // Find whether deferred image exists in this instance.
+ //
+ DriverIndex = 0;
+ Status = DeferredImage->GetImageInfo(
+ DeferredImage,
+ DriverIndex,
+ &ImageDevicePath,
+ (VOID **) &DriverImage,
+ &ImageSize,
+ &BootOption
+ );
+ if (!EFI_ERROR (Status)) {
+ //
+ // The deferred image is found.
+ //
+ FreePool (HandleBuf);
+ *DeferredImageExist = TRUE;
+ return ;
+ }
+ }
+ }
+
+ FreePool (HandleBuf);
+}
+
+UINTN gHotKey = 0;
+
+EFI_STATUS
+ShowProgressHotKey (
+ IN UINT16 TimeoutDefault
+ )
+{
+ CHAR16 *TmpStr;
+ UINT16 TimeoutRemain;
+ EFI_STATUS Status;
+ EFI_INPUT_KEY Key;
+ EFI_GRAPHICS_OUTPUT_BLT_PIXEL Foreground;
+ EFI_GRAPHICS_OUTPUT_BLT_PIXEL Background;
+ EFI_GRAPHICS_OUTPUT_BLT_PIXEL Color;
+ UINT32 GpioValue;
+
+ if (TimeoutDefault == 0) {
+ return EFI_TIMEOUT;
+ }
+
+ gST->ConOut->SetAttribute(gST->ConOut, EFI_TEXT_ATTR (EFI_LIGHTGRAY, EFI_BLACK));
+
+ if (DebugAssertEnabled())
+ {
+ DEBUG ((EFI_D_INFO, "\n\nStart showing progress bar... Press any key to stop it, or press <F2> or <DEL> to enter setup page! ...Zzz....\n"));
+ }
+ else
+ {
+ #ifdef __GNUC__
+ SerialPortWrite((UINT8 *)"\n\n>>>>Start boot option, Press <F2> or <DEL> to enter setup page(5 Sec)[GCC]", 76);
+ #else
+ SerialPortWrite((UINT8 *)"\n\n>>>>Start boot option, Press <F2> or <DEL> to enter setup page(5 Sec)", 71);
+ #endif
+ }
+ SetMem (&Foreground, sizeof (EFI_GRAPHICS_OUTPUT_BLT_PIXEL), 0xff);
+ SetMem (&Background, sizeof (EFI_GRAPHICS_OUTPUT_BLT_PIXEL), 0x0);
+ SetMem (&Color, sizeof (EFI_GRAPHICS_OUTPUT_BLT_PIXEL), 0xff);
+
+ //
+ // Clear the progress status bar first
+ //
+ TmpStr = L"Start boot option, Press <F2> or <DEL> to enter setup page.";
+ PlatformBdsShowProgress (Foreground, Background, TmpStr, Color, 0, 0);
+
+ TimeoutRemain = TimeoutDefault;
+ while (TimeoutRemain != 0) {
+ if (DebugAssertEnabled())
+ {
+ DEBUG ((EFI_D_INFO, "Showing progress bar...Remaining %d second!\n", TimeoutRemain));
+ }
+ else
+ {
+ SerialPortWrite ((UINT8 *)".", 1);
+ }
+ Status = WaitForSingleEvent (gST->ConIn->WaitForKey, ONE_SECOND);
+ if (Status != EFI_TIMEOUT) {
+ break;
+ }
+ TimeoutRemain--;
+
+ //
+ // Show progress
+ //
+ if (TmpStr != NULL) {
+ PlatformBdsShowProgress (
+ Foreground,
+ Background,
+ TmpStr,
+ Color,
+ ((TimeoutDefault - TimeoutRemain) * 100 / TimeoutDefault),
+ 0
+ );
+ }
+ }
+
+ //
+ // Timeout expired
+ //
+ if (TimeoutRemain == 0) {
+ if (DebugAssertEnabled())
+ {
+ }
+ else
+ {
+ SerialPortWrite ((UINT8 *)"\r\n", 2);
+ }
+ return EFI_TIMEOUT;
+ }
+
+ //
+ // User pressed some key
+ //
+ Status = gST->ConIn->ReadKeyStroke (gST->ConIn, &Key);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ //
+ // Check Volume Up Key to enter Setup
+ //
+ GpioValue = MmioRead32 (IO_BASE_ADDRESS + 0x0668); // The value of GPIOC_5
+ if (((GpioValue & BIT0) == 0) && (Key.ScanCode == SCAN_UP)) {
+ gHotKey = 0;
+ return EFI_SUCCESS;
+ }
+
+ if (Key.UnicodeChar == CHAR_CARRIAGE_RETURN) {
+ //
+ // User pressed enter, equivalent to select "continue"
+ //
+ return EFI_TIMEOUT;
+ }
+
+ //
+ //F2 -- Front Page
+ //F5 -- Device Manager
+ //F7 -- Boot Manager
+ // do not use F8. generally people assume it is windows safe mode key.
+ //F9 -- Boot order
+ //
+ DEBUG ((EFI_D_INFO, "[Key Pressed]: ScanCode 0x%x\n", Key.ScanCode));
+ switch(Key.ScanCode) {
+ case SCAN_F2:
+ gHotKey = 0;
+ break;
+
+ case SCAN_DELETE:
+ gHotKey = 0;
+ break;
+
+ case SCAN_F5:
+ gHotKey = FRONT_PAGE_KEY_DEVICE_MANAGER;
+ break;
+
+ case SCAN_F7:
+ gHotKey = FRONT_PAGE_KEY_BOOT_MANAGER;
+ break;
+
+ case SCAN_F9:
+ gHotKey = FRONT_PAGE_KEY_BOOT_MAINTAIN;
+ break;
+
+ default:
+ //set gHotKey to continue so that flow will not go into CallFrontPage
+ gHotKey = FRONT_PAGE_KEY_CONTINUE;
+ return EFI_TIMEOUT;
+ break;
+ }
+
+ return EFI_SUCCESS;
+}
+
+/**
+ This function is the main entry of the platform setup entry.
+ The function will present the main menu of the system setup,
+ this is the platform reference part and can be customize.
+
+ @param TimeoutDefault The fault time out value before the system
+ continue to boot.
+ @param ConnectAllHappened The indicater to check if the connect all have
+ already happened.
+
+**/
+VOID
+PlatformBdsEnterFrontPageWithHotKey (
+ IN UINT16 TimeoutDefault,
+ IN BOOLEAN ConnectAllHappened
+ )
+{
+ EFI_STATUS Status;
+
+ EFI_GRAPHICS_OUTPUT_PROTOCOL *GraphicsOutput;
+ EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL *SimpleTextOut;
+ UINTN BootTextColumn;
+ UINTN BootTextRow;
+
+ GraphicsOutput = NULL;
+ SimpleTextOut = NULL;
+
+ PERF_START (NULL, "BdsTimeOut", "BDS", 0);
+
+ //
+ // Indicate if we need connect all in the platform setup
+ //
+ if (ConnectAllHappened) {
+ gConnectAllHappened = TRUE;
+ }
+
+ if (!mModeInitialized) {
+ //
+ // After the console is ready, get current video resolution
+ // and text mode before launching setup at first time.
+ //
+ Status = gBS->HandleProtocol (
+ gST->ConsoleOutHandle,
+ &gEfiGraphicsOutputProtocolGuid,
+ (VOID**)&GraphicsOutput
+ );
+ if (EFI_ERROR (Status)) {
+ GraphicsOutput = NULL;
+ }
+
+ Status = gBS->HandleProtocol (
+ gST->ConsoleOutHandle,
+ &gEfiSimpleTextOutProtocolGuid,
+ (VOID**)&SimpleTextOut
+ );
+ if (EFI_ERROR (Status)) {
+ SimpleTextOut = NULL;
+ }
+
+ if (GraphicsOutput != NULL) {
+ //
+ // Get current video resolution and text mode.
+ //
+ mBootHorizontalResolution = GraphicsOutput->Mode->Info->HorizontalResolution;
+ mBootVerticalResolution = GraphicsOutput->Mode->Info->VerticalResolution;
+ }
+
+ if (SimpleTextOut != NULL) {
+ Status = SimpleTextOut->QueryMode (
+ SimpleTextOut,
+ SimpleTextOut->Mode->Mode,
+ &BootTextColumn,
+ &BootTextRow
+ );
+ mBootTextModeColumn = (UINT32)BootTextColumn;
+ mBootTextModeRow = (UINT32)BootTextRow;
+ }
+
+ //
+ // Get user defined text mode for setup.
+ //
+ mSetupHorizontalResolution = PcdGet32 (PcdSetupVideoHorizontalResolution);
+ mSetupVerticalResolution = PcdGet32 (PcdSetupVideoVerticalResolution);
+ mSetupTextModeColumn = PcdGet32 (PcdSetupConOutColumn);
+ mSetupTextModeRow = PcdGet32 (PcdSetupConOutRow);
+
+ mModeInitialized = TRUE;
+ }
+
+ if (TimeoutDefault != 0xffff) {
+ Status = ShowProgressHotKey (TimeoutDefault);
+
+ //
+ // Ensure screen is clear when switch Console from Graphics mode to Text mode
+ //
+ gST->ConOut->EnableCursor (gST->ConOut, TRUE);
+ gST->ConOut->ClearScreen (gST->ConOut);
+
+ if (EFI_ERROR (Status)) {
+ //
+ // Timeout or user press enter to continue
+ //
+ goto Exit;
+ }
+ }
+ //
+ // Install BM HiiPackages.
+ // Keep BootMaint HiiPackage, so that it can be covered by global setting.
+ //
+ InitBMPackage ();
+ do {
+
+ BdsSetConsoleMode (TRUE);
+
+ InitializeFrontPage (FALSE);
+
+ //
+ // Update Front Page strings
+ //
+ UpdateFrontPageStrings ();
+
+ Status = EFI_SUCCESS;
+ gCallbackKey = 0;
+ if (gHotKey == 0) {
+ Status = CallFrontPage ();
+ } else {
+ gCallbackKey = gHotKey;
+ gHotKey = 0;
+ }
+
+ //
+ // If gCallbackKey is greater than 1 and less or equal to 5,
+ // it will launch configuration utilities.
+ // 2 = set language
+ // 3 = boot manager
+ // 4 = device manager
+ // 5 = boot maintenance manager
+ //
+ if (gCallbackKey != 0) {
+ REPORT_STATUS_CODE (
+ EFI_PROGRESS_CODE,
+ (EFI_SOFTWARE_DXE_BS_DRIVER | EFI_SW_PC_USER_SETUP)
+ );
+ }
+
+ //
+ // Based on the key that was set, we can determine what to do
+ //
+ switch (gCallbackKey) {
+ //
+ // The first 4 entries in the Front Page are to be GUARANTEED to remain constant so IHV's can
+ // describe to their customers in documentation how to find their setup information (namely
+ // under the device manager and specific buckets)
+ //
+ // These entries consist of the Continue, Select language, Boot Manager, and Device Manager
+ //
+ case FRONT_PAGE_KEY_CONTINUE:
+
+ //
+ // User hit continue
+ //
+ break;
+
+ case FRONT_PAGE_KEY_LANGUAGE:
+
+ //
+ // User made a language setting change - display front page again
+ //
+ break;
+
+ case FRONT_PAGE_KEY_BOOT_MANAGER:
+ //
+ // Remove the installed BootMaint HiiPackages when exit.
+ //
+ FreeBMPackage ();
+
+ //
+ // User chose to run the Boot Manager
+ //
+ CallBootManager ();
+
+ //
+ // Reinstall BootMaint HiiPackages after exiting from Boot Manager.
+ //
+ InitBMPackage ();
+ break;
+
+ case FRONT_PAGE_KEY_DEVICE_MANAGER:
+
+ //
+ // Display the Device Manager
+ //
+ do {
+ CallDeviceManager ();
+ } while (gCallbackKey == FRONT_PAGE_KEY_DEVICE_MANAGER);
+ break;
+
+ case FRONT_PAGE_KEY_BOOT_MAINTAIN:
+
+ //
+ // Display the Boot Maintenance Manager
+ //
+ BdsStartBootMaint ();
+ break;
+ }
+
+ } while (((UINTN)gCallbackKey) != FRONT_PAGE_KEY_CONTINUE);
+
+ //
+ //Will leave browser, check any reset required change is applied? if yes, reset system
+ //
+ SetupResetReminder ();
+ //
+ // Remove the installed BootMaint HiiPackages when exit.
+ //
+ FreeBMPackage ();
+
+Exit:
+ //
+ // Automatically load current entry
+ // Note: The following lines of code only execute when Auto boot
+ // takes affect
+ //
+ PERF_END (NULL, "BdsTimeOut", "BDS", 0);
+}
+
+VOID
+BootIntoFirmwareInterface(
+VOID
+)
+{
+ EFI_STATUS Status;
+ UINTN DataSize;
+ UINT16 Timeout;
+ UINT64 OsIndication;
+
+
+ OsIndication = 0;
+ DataSize = sizeof(UINT64);
+ Status = gRT->GetVariable (
+ L"OsIndications",
+ &gEfiGlobalVariableGuid,
+ NULL,
+ &DataSize,
+ &OsIndication
+ );
+
+ DEBUG ((EFI_D_INFO, "OSIndication Variable Value %d\n", OsIndication));
+ //
+ //Goto FrontPage directly when bit EFI_OS_INDICATIONS_BOOT_TO_FW_UI in OSIndication Variable is setted.
+ //
+ if (!EFI_ERROR(Status) && (OsIndication != 0)) {
+ Timeout = 0xffff;
+ PlatformBdsEnterFrontPage (Timeout, FALSE);
+ }
+}
+
+EFI_STATUS
+PlatformBdsConnectSimpleConsole (
+ IN BDS_CONSOLE_CONNECT_ENTRY *PlatformConsole
+)
+{
+ EFI_STATUS Status;
+ UINTN Index;
+ EFI_DEVICE_PATH_PROTOCOL *VarConout;
+ EFI_DEVICE_PATH_PROTOCOL *VarConin;
+ UINTN DevicePathSize;
+
+ Index = 0;
+ Status = EFI_SUCCESS;
+ DevicePathSize = 0;
+ VarConout = BdsLibGetVariableAndSize (
+ L"ConOut",
+ &gEfiGlobalVariableGuid,
+ &DevicePathSize
+ );
+ VarConin = BdsLibGetVariableAndSize (
+ L"ConIn",
+ &gEfiGlobalVariableGuid,
+ &DevicePathSize
+ );
+ if (VarConout == NULL || VarConin == NULL) {
+ //
+ // Have chance to connect the platform default console,
+ // the platform default console is the minimue device group
+ // the platform should support
+ //
+ while (PlatformConsole[Index].DevicePath != NULL) {
+
+ //
+ // Update the console variable with the connect type
+ //
+ if ((PlatformConsole[Index].ConnectType & CONSOLE_IN) == CONSOLE_IN) {
+ BdsLibUpdateConsoleVariable (L"ConIn", PlatformConsole[Index].DevicePath, NULL);
+ }
+
+ if ((PlatformConsole[Index].ConnectType & CONSOLE_OUT) == CONSOLE_OUT) {
+ BdsLibUpdateConsoleVariable (L"ConOut", PlatformConsole[Index].DevicePath, NULL);
+ }
+
+ if ((PlatformConsole[Index].ConnectType & STD_ERROR) == STD_ERROR) {
+ BdsLibUpdateConsoleVariable (L"ErrOut", PlatformConsole[Index].DevicePath, NULL);
+ }
+
+ Index ++;
+ }
+ }
+
+ //
+ // Connect ConIn first to give keyboard time to parse hot key event.
+ //
+ Status = BdsLibConnectConsoleVariable (L"ConIn");
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ //
+ // Make sure we have at least one active VGA, and have the right
+ // active VGA in console variable
+ //
+ Status = PlatformBdsForceActiveVga ();
+
+ //
+ // It seems impossible not to have any ConOut device on platform,
+ // so we check the status here.
+ //
+ Status = BdsLibConnectConsoleVariable (L"ConOut");
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Timer handler to convert the key from USB.
+
+ @param Event Indicates the event that invoke this function.
+ @param Context Indicates the calling context.
+**/
+VOID
+EFIAPI
+HotKeyTimerHandler (
+ IN EFI_EVENT Event,
+ IN VOID *Context
+ )
+{
+ EFI_STATUS Status;
+ EFI_INPUT_KEY Key;
+
+ Status = gST->ConIn->ReadKeyStroke (gST->ConIn, &Key);
+ if (EFI_ERROR (Status)) {
+ return;
+ }
+
+ switch(Key.ScanCode) {
+ case SCAN_F2:
+ gHotKey = 0;
+ mHotKeyPressed = TRUE;
+ break;
+
+ case SCAN_F5:
+ gHotKey = FRONT_PAGE_KEY_DEVICE_MANAGER;
+ mHotKeyPressed = TRUE;
+ break;
+
+ case SCAN_F7:
+ gHotKey = FRONT_PAGE_KEY_BOOT_MANAGER;
+ mHotKeyPressed = TRUE;
+ break;
+
+ case SCAN_F9:
+ gHotKey = FRONT_PAGE_KEY_BOOT_MAINTAIN;
+ mHotKeyPressed = TRUE;
+ break;
+ }
+
+ if (mHotKeyPressed) {
+ gBS->SetTimer (
+ mHotKeyTimerEvent,
+ TimerCancel,
+ 0
+ );
+ gBS->CloseEvent (mHotKeyTimerEvent);
+ mHotKeyTimerEvent = NULL;
+ }
+
+ return;
+}
+
+/**
+ Callback function for SimpleTextInEx protocol install events
+
+ @param Event the event that is signaled.
+ @param Context not used here.
+
+**/
+VOID
+EFIAPI
+HitHotkeyEvent (
+ IN EFI_EVENT Event,
+ IN VOID *Context
+ )
+{
+ EFI_STATUS Status;
+
+ Status = gBS->CloseEvent(mHitHotkeyEvent);
+ if (EFI_ERROR (Status)) {
+ return;
+ }
+ Status = gBS->CreateEvent (
+ EVT_TIMER | EVT_NOTIFY_SIGNAL,
+ TPL_NOTIFY,
+ HotKeyTimerHandler,
+ NULL,
+ &mHotKeyTimerEvent
+ );
+ if (EFI_ERROR (Status)) {
+ return;
+ }
+ Status = gBS->SetTimer (
+ mHotKeyTimerEvent,
+ TimerPeriodic,
+ KEYBOARD_TIMER_INTERVAL
+ );
+ if (EFI_ERROR (Status)) {
+ return;
+ }
+
+ return;
+}
+
+VOID
+EFIAPI
+PlatformBdsInitHotKeyEvent (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+
+ //
+ // Register Protocol notify for Hotkey service
+ //
+ Status = gBS->CreateEvent (
+ EVT_NOTIFY_SIGNAL,
+ TPL_CALLBACK,
+ HitHotkeyEvent,
+ NULL,
+ &mHitHotkeyEvent
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Register for protocol notifications on this event
+ //
+ Status = gBS->RegisterProtocolNotify (
+ &gEfiSimpleTextInputExProtocolGuid,
+ mHitHotkeyEvent,
+ &mHitHotkeyRegistration
+ );
+ ASSERT_EFI_ERROR (Status);
+}
diff --git a/BraswellPlatformPkg/Common/Library/PlatformBdsLib/BdsPlatform.h b/BraswellPlatformPkg/Common/Library/PlatformBdsLib/BdsPlatform.h new file mode 100644 index 0000000000..a888219416 --- /dev/null +++ b/BraswellPlatformPkg/Common/Library/PlatformBdsLib/BdsPlatform.h @@ -0,0 +1,492 @@ +/** @file
+ Head file for BDS Platform specific code
+
+ Copyright (c) 2004 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _BDS_PLATFORM_H
+#define _BDS_PLATFORM_H
+
+#include <FrameworkDxe.h>
+#include <Protocol/FirmwareVolume2.h>
+#include <Protocol/DevicePath.h>
+#include <Protocol/SimpleNetwork.h>
+#include <Protocol/PciRootBridgeIo.h>
+#include <Protocol/LoadFile.h>
+#include <Protocol/LegacyBios.h>
+#include <Protocol/PciIo.h>
+#include <Protocol/SmmAccess2.h>
+#include <Protocol/DxeSmmReadyToLock.h>
+#include <Protocol/UserManager.h>
+#include <Protocol/DeferredImageLoad.h>
+#include <Protocol/AcpiS3Save.h>
+#include <Protocol/ExitPmAuth.h>
+#include <Protocol/MmioDevice.h>
+#include <Guid/CapsuleVendor.h>
+#include <Guid/MemoryTypeInformation.h>
+#include <Guid/GlobalVariable.h>
+#include <Guid/EventGroup.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiRuntimeServicesTableLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/BaseLib.h>
+#include <Library/PcdLib.h>
+#include <Library/IoLib.h>
+#include <Library/GenericBdsLib.h>
+#include <Library/PlatformBdsLib.h>
+#include <Library/DevicePathLib.h>
+#include <Library/UefiLib.h>
+#include <Library/HobLib.h>
+#include <Library/PrintLib.h>
+#include <Library/PerformanceLib.h>
+#include <Library/ReportStatusCodeLib.h>
+#include <IndustryStandard/Pci.h>
+
+extern EFI_DEVICE_PATH_PROTOCOL *gPlatformRootBridges [];
+extern BDS_CONSOLE_CONNECT_ENTRY gPlatformConsole [];
+extern EFI_DEVICE_PATH_PROTOCOL *gPlatformAllPossiblePciVgaConsole [];
+extern EFI_DEVICE_PATH_PROTOCOL *gPlatformConnectSequence [];
+extern EFI_DEVICE_PATH_PROTOCOL *gPlatformDriverOption [];
+extern EFI_DEVICE_PATH_PROTOCOL *gPlatformBootOption [];
+extern EFI_DEVICE_PATH_PROTOCOL *gUserAuthenticationDevice[];
+extern BDS_CONSOLE_CONNECT_ENTRY gPlatformSimpleConsole [];
+extern EFI_DEVICE_PATH_PROTOCOL *gPlatformSimpleBootOption [];
+
+extern BOOLEAN mEnumBootDevice;
+
+//
+// the short form device path for Usb keyboard
+//
+#define CLASS_HID 3
+#define SUBCLASS_BOOT 1
+#define PROTOCOL_KEYBOARD 1
+
+#define PCI_DEVICE_PATH_NODE(Func, Dev) \
+ { \
+ HARDWARE_DEVICE_PATH, \
+ HW_PCI_DP, \
+ { \
+ (UINT8) (sizeof (PCI_DEVICE_PATH)), \
+ (UINT8) ((sizeof (PCI_DEVICE_PATH)) >> 8) \
+ }, \
+ (Func), \
+ (Dev) \
+ }
+
+#define PNPID_DEVICE_PATH_NODE(PnpId) \
+ { \
+ { \
+ ACPI_DEVICE_PATH, \
+ ACPI_DP, \
+ { \
+ (UINT8) (sizeof (ACPI_HID_DEVICE_PATH)), \
+ (UINT8) ((sizeof (ACPI_HID_DEVICE_PATH)) >> 8) \
+ } \
+ }, \
+ EISA_PNP_ID((PnpId)), \
+ 0 \
+ }
+
+#define gUart(BaudRate, DataBits, Parity, StopBits) \
+ { \
+ { \
+ MESSAGING_DEVICE_PATH, \
+ MSG_UART_DP, \
+ { \
+ (UINT8) (sizeof (UART_DEVICE_PATH)), \
+ (UINT8) ((sizeof (UART_DEVICE_PATH)) >> 8) \
+ } \
+ }, \
+ 0, \
+ (BaudRate), \
+ (DataBits), \
+ (Parity), \
+ (StopBits) \
+ }
+
+#define gPcAnsiTerminal \
+ { \
+ { \
+ MESSAGING_DEVICE_PATH, \
+ MSG_VENDOR_DP, \
+ { \
+ (UINT8) (sizeof (VENDOR_DEVICE_PATH)), \
+ (UINT8) ((sizeof (VENDOR_DEVICE_PATH)) >> 8) \
+ } \
+ }, \
+ DEVICE_PATH_MESSAGING_PC_ANSI \
+ }
+
+#define gUsbKeyboardMouse \
+ { \
+ { \
+ MESSAGING_DEVICE_PATH, \
+ MSG_USB_CLASS_DP, \
+ (UINT8) (sizeof (USB_CLASS_DEVICE_PATH)), \
+ (UINT8) ((sizeof (USB_CLASS_DEVICE_PATH)) >> 8) \
+ }, \
+ 0xffff, \
+ 0xffff, \
+ CLASS_HID, \
+ SUBCLASS_BOOT, \
+ PROTOCOL_KEYBOARD \
+ }
+
+#define gEndEntire \
+ { \
+ END_DEVICE_PATH_TYPE, \
+ END_ENTIRE_DEVICE_PATH_SUBTYPE, \
+ { \
+ END_DEVICE_PATH_LENGTH, \
+ 0 \
+ } \
+ }
+
+#define gPciRootBridge \
+ PNPID_DEVICE_PATH_NODE(0x0A03)
+
+#define gPnpPs2Keyboard \
+ PNPID_DEVICE_PATH_NODE(0x0303)
+
+#define gPnp16550ComPort \
+ PNPID_DEVICE_PATH_NODE(0x0501)
+
+#define gPciePort0Bridge \
+ PCI_DEVICE_PATH_NODE(0, 0x1C)
+
+#define gPciePort1Bridge \
+ PCI_DEVICE_PATH_NODE(1, 0x1C)
+
+#define gPciePort2Bridge \
+ PCI_DEVICE_PATH_NODE(2, 0x1C)
+
+#define gPciePort3Bridge \
+ PCI_DEVICE_PATH_NODE(3, 0x1C)
+
+#define gPciIsaBridge \
+ PCI_DEVICE_PATH_NODE(0, 0x1f)
+
+//
+// Platform Root Bridge
+//
+typedef struct {
+ ACPI_HID_DEVICE_PATH PciRootBridge;
+ EFI_DEVICE_PATH_PROTOCOL End;
+} PLATFORM_ROOT_BRIDGE_DEVICE_PATH;
+
+//
+// Below is the platform console device path
+//
+typedef struct {
+ ACPI_HID_DEVICE_PATH PciRootBridge;
+ PCI_DEVICE_PATH IsaBridge;
+ ACPI_HID_DEVICE_PATH Keyboard;
+ EFI_DEVICE_PATH_PROTOCOL End;
+} PLATFORM_ISA_KEYBOARD_DEVICE_PATH;
+
+typedef struct {
+ VENDOR_DEVICE_PATH VendorDevicePath;
+ EFI_DEVICE_PATH_PROTOCOL End;
+} HII_VENDOR_DEVICE_PATH;
+
+typedef struct {
+ USB_CLASS_DEVICE_PATH UsbClass;
+ EFI_DEVICE_PATH_PROTOCOL End;
+} USB_CLASS_FORMAT_DEVICE_PATH;
+
+typedef struct {
+ ACPI_HID_DEVICE_PATH PciRootBridge;
+ PCI_DEVICE_PATH OnboardVga;
+ EFI_DEVICE_PATH_PROTOCOL End;
+} PLATFORM_ONBOARD_VGA_DEVICE_PATH;
+
+typedef struct {
+ ACPI_HID_DEVICE_PATH PciRootBridge;
+ PCI_DEVICE_PATH AgpBridge;
+ PCI_DEVICE_PATH AgpDevice;
+ EFI_DEVICE_PATH_PROTOCOL End;
+} PLATFORM_OFFBOARD_VGA_DEVICE_PATH;
+
+typedef struct {
+ ACPI_HID_DEVICE_PATH PciRootBridge;
+ PCI_DEVICE_PATH IsaBridge;
+ ACPI_HID_DEVICE_PATH IsaSerial;
+ UART_DEVICE_PATH Uart;
+ VENDOR_DEVICE_PATH TerminalType;
+ EFI_DEVICE_PATH_PROTOCOL End;
+} PLATFORM_ISA_SERIAL_DEVICE_PATH;
+
+//
+// Below is the boot option device path
+//
+typedef struct {
+ BBS_BBS_DEVICE_PATH LegacyHD;
+ EFI_DEVICE_PATH_PROTOCOL End;
+} LEGACY_HD_DEVICE_PATH;
+
+//
+// Below is the platform IDE device path
+//
+typedef struct {
+ ACPI_HID_DEVICE_PATH PciRootBridge;
+ PCI_DEVICE_PATH IsaBridge;
+ ATAPI_DEVICE_PATH Ide;
+ EFI_DEVICE_PATH_PROTOCOL End;
+} PLATFORM_IDE_DEVICE_PATH;
+
+//
+// Floppy device path definition
+//
+typedef struct {
+ ACPI_HID_DEVICE_PATH PciRootBridge;
+ PCI_DEVICE_PATH IsaBridge;
+ ACPI_HID_DEVICE_PATH Floppy;
+ EFI_DEVICE_PATH_PROTOCOL End;
+} PLATFORM_FLOPPY_DEVICE_PATH;
+
+//
+// Below is the platform USB controller device path for
+// USB disk as user authentication device.
+//
+typedef struct {
+ ACPI_HID_DEVICE_PATH PciRootBridge;
+ PCI_DEVICE_PATH PciDevice;
+ EFI_DEVICE_PATH_PROTOCOL End;
+} PLATFORM_USB_DEVICE_PATH;
+
+//
+// Below is the platform PCI device path
+//
+typedef struct {
+ ACPI_HID_DEVICE_PATH PciRootBridge;
+ PCI_DEVICE_PATH PciDevice;
+ EFI_DEVICE_PATH_PROTOCOL End;
+} PLATFORM_PCI_DEVICE_PATH;
+
+typedef enum {
+ PMIC_Equal = 0, // = 0
+ PMIC_Greater_Than, // > 1
+ PMIC_Smaller_Than, // < 2
+ PMIC_Greater_Equal, // >= 3
+ PMIC_Smaller_Equal, // <= 4
+ PMIC_Any // don't care 5
+} PMIC_Condition_list;
+
+typedef enum {
+ PMIC_White_List = 0, //White list
+ PMIC_Black_List = 1 //Black list
+} PMIC_Compliance_mode;
+
+typedef struct {
+ UINT8 Cond_Choice; // PMIC_Condition_list
+ UINT8 Cond_Number; // the number
+}PMIC_Condition_Item;
+
+typedef struct {
+ PMIC_Condition_Item PMIC_BoardID;
+ PMIC_Condition_Item PMIC_FabID;
+ PMIC_Condition_Item Soc_Stepping;//define PMIC type, 1:Dialog , 2:Rohm
+ PMIC_Condition_Item PMIC_VendID;
+ PMIC_Condition_Item PMIC_RevID;
+ PMIC_Compliance_mode mode; //if 1, blacklist; if 0, white list.
+} PMIC_Compliance_Item;
+
+//
+// Platform BDS Functions
+//
+VOID
+PlatformBdsGetDriverOption (
+ IN LIST_ENTRY *BdsDriverLists
+ );
+
+VOID
+PlatformBdsPredictBootOption (
+ IN LIST_ENTRY *BdsBootOptionList
+ );
+
+EFI_STATUS
+PlatformBdsShowProgress (
+ EFI_GRAPHICS_OUTPUT_BLT_PIXEL TitleForeground,
+ EFI_GRAPHICS_OUTPUT_BLT_PIXEL TitleBackground,
+ CHAR16 *Title,
+ EFI_GRAPHICS_OUTPUT_BLT_PIXEL ProgressColor,
+ UINTN Progress,
+ UINTN PreviousValue
+ );
+
+VOID
+PlatformBdsConnectSequence (
+ VOID
+ );
+
+EFI_STATUS
+PlatformBdsConnectConsole (
+ IN BDS_CONSOLE_CONNECT_ENTRY *PlatformConsole
+ );
+
+EFI_STATUS
+PlatformBdsNoConsoleAction (
+ VOID
+ );
+
+VOID
+PlatformBdsEnterFrontPage (
+ IN UINT16 TimeoutDefault,
+ IN BOOLEAN ConnectAllHappened
+ );
+
+VOID
+EFIAPI
+PlatformBdsUserIdentify (
+ OUT EFI_USER_PROFILE_HANDLE *User,
+ OUT BOOLEAN *DeferredImage
+ );
+
+VOID
+EFIAPI
+PlatformBdsConnectAuthDevice (
+ VOID
+ );
+
+VOID
+PlatformBdsEnterFrontPageWithHotKey (
+ IN UINT16 TimeoutDefault,
+ IN BOOLEAN ConnectAllHappened
+ );
+
+EFI_STATUS
+ShowProgress (
+ IN UINT16 TimeoutDefault
+ );
+
+EFI_STATUS
+InitializeFrontPage (
+ IN BOOLEAN InitializeHiiData
+ );
+
+VOID
+UpdateFrontPageStrings (
+ VOID
+ );
+
+
+EFI_STATUS
+InitBMPackage (
+ VOID
+ );
+
+
+VOID
+FreeBMPackage (
+ VOID
+ );
+
+
+EFI_STATUS
+CallFrontPage (
+ VOID
+ );
+
+VOID
+CallBootManager (
+ VOID
+ );
+
+VOID
+CallDeviceManager (
+ VOID
+ );
+
+VOID
+BdsStartBootMaint (
+ VOID
+ );
+
+CHAR16 *
+GetStringById (
+ IN EFI_STRING_ID Id
+ );
+
+EFI_STATUS
+WaitForSingleEvent (
+ IN EFI_EVENT Event,
+ IN UINT64 Timeout OPTIONAL
+ );
+
+EFI_STATUS
+BdsLibDeleteOptionFromHandle (
+ IN EFI_HANDLE Handle
+ );
+
+EFI_STATUS
+BdsDeleteAllInvalidEfiBootOption (
+ VOID
+ );
+
+#define ONE_SECOND 10000000
+#define FRONT_PAGE_KEY_CONTINUE 0x1000
+#define FRONT_PAGE_KEY_LANGUAGE 0x1234
+#define FRONT_PAGE_KEY_BOOT_MANAGER 0x1064
+#define FRONT_PAGE_KEY_DEVICE_MANAGER 0x8567
+#define FRONT_PAGE_KEY_BOOT_MAINTAIN 0x9876
+
+#define PORT_A_DVO 0 // ; DVO A
+#define PORT_B_DVO 1 // ; DVO B
+#define PORT_C_DVO 2 // ; DVO C
+#define PORT_D_DVO 3 // ; DVO D
+#define PORT_LVDS 4 // ; Integrated LVDS port
+#define PORT_ANALOG_TV 5 // ; Integrated TV port
+#define PORT_CRT 6 // ; integrated Analog port
+#define PORT_B_DP 7 // ; DisplayPort B
+#define PORT_C_DP 8 // ; DisplayPort C
+#define PORT_D_DP 9 // ; DisplayPort D
+#define PORT_A_DP 10 // ; DisplayPort A (for eDP on ILK)
+#define PORT_B_HDMI 11 // ; HDMI B
+#define PORT_C_HDMI 12 // ; HDMI C
+#define PORT_D_HDMI 13 // ; HDMI D
+#define PORT_B_DVI 14 // ; DVI B
+#define PORT_C_DVI 15 // ; DVI C
+#define PORT_D_DVI 16 // ; DVI D
+#define PORT_MIPI_A 21 // ; MIPI
+#define PORT_MIPI_B 22
+#define PORT_MIPI_C 23
+
+extern BOOLEAN gConnectAllHappened;
+extern UINTN gCallbackKey;
+
+VOID
+BdsBootDeviceSelect (
+ VOID
+);
+VOID FastBoot(VOID);
+
+extern BOOLEAN mModeInitialized;
+
+//
+// Boot video resolution and text mode.
+//
+extern UINT32 mBootHorizontalResolution ;
+extern UINT32 mBootVerticalResolution ;
+extern UINT32 mBootTextModeColumn ;
+extern UINT32 mBootTextModeRow ;
+
+//
+// BIOS setup video resolution and text mode.
+//
+extern UINT32 mSetupTextModeColumn ;
+extern UINT32 mSetupTextModeRow ;
+extern UINT32 mSetupHorizontalResolution ;
+extern UINT32 mSetupVerticalResolution ;
+extern EFI_STATUS BdsSetConsoleMode (BOOLEAN);
+#endif // _BDS_PLATFORM_H
diff --git a/BraswellPlatformPkg/Common/Library/PlatformBdsLib/PlatformBdsLib.inf b/BraswellPlatformPkg/Common/Library/PlatformBdsLib/PlatformBdsLib.inf new file mode 100644 index 0000000000..d65aa88034 --- /dev/null +++ b/BraswellPlatformPkg/Common/Library/PlatformBdsLib/PlatformBdsLib.inf @@ -0,0 +1,110 @@ +## @file
+# Component name for module PlatformBootManagerLib
+#
+# Copyright (c) 2008 - 2015, Intel Corporation. All rights reserved.<BR>
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php.
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = PlatformBdsLib
+ FILE_GUID = A6BC385D-59E5-4b77-87D7-200ABAA83C15
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = PlatformBootManagerLib|DXE_DRIVER
+ EDK_RELEASE_VERSION = 0x00020000
+ EFI_SPECIFICATION_VERSION = 0x0002000A
+
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = IA32 X64 EBC
+#
+
+[Sources]
+ BdsPlatform.c
+ BdsPlatform.h
+ PlatformData.c
+ PlatformBdsStrings.uni
+
+[Packages]
+ BraswellPlatformPkg/BraswellPlatformPkg.dec
+ ChvRefCodePkg/ChvRefCodePkg.dec
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ IntelFrameworkPkg/IntelFrameworkPkg.dec
+ IntelFrameworkModulePkg/IntelFrameworkModulePkg.dec
+ ShellPkg/ShellPkg.dec
+ CryptoPkg/CryptoPkg.dec
+ SecurityPkg/SecurityPkg.dec
+
+[LibraryClasses]
+ DxeServicesTableLib
+ BaseLib
+ MemoryAllocationLib
+ UefiBootServicesTableLib
+ UefiRuntimeServicesTableLib
+ BaseMemoryLib
+ DebugLib
+ PcdLib
+ GenericBdsLib
+ DevicePathLib
+ NetLib
+ UefiLib
+ HobLib
+ PciLib
+ PrintLib
+ BaseCryptLib
+ TrEEPhysicalPresenceLib
+ FileHandleLib
+ S3BootScriptLib
+ SerialPortLib
+
+[Protocols]
+ gEfiFirmwareVolume2ProtocolGuid ## CONSUMES
+ gEfiSimpleNetworkProtocolGuid ## SOMETIMES_CONSUMES
+ gEfiLoadFileProtocolGuid ## CONSUMES
+ gEfiPciIoProtocolGuid ## CONSUMES
+ gEfiSmmAccess2ProtocolGuid ## CONSUMES
+ gEfiDxeSmmReadyToLockProtocolGuid ## SOMETIMES_PRODUCES
+ gEfiUserManagerProtocolGuid ## CONSUMES
+ gEfiDeferredImageLoadProtocolGuid ## CONSUMES
+ gEfiAcpiS3SaveProtocolGuid ## SOMETIMES_CONSUMES
+ gExitPmAuthProtocolGuid ## PRODUCES
+ gEfiGlobalNvsAreaProtocolGuid ## CONSUMES
+ gEfiMmioDeviceProtocolGuid ## CONSUMES
+
+[Guids]
+ gEfiCapsuleVendorGuid ## CONSUMES ## Variable Guid
+ ## CONSUMES ## Variable:L"ConOut"
+ ## CONSUMES ## Variable:L"ConIn"
+ ## SOMETIMES_CONSUMES ## Variable:L"BootOrder"
+ ## CONSUMES ## Variable:L"OsIndications"
+ gEfiGlobalVariableGuid
+ gEfiEndOfDxeEventGroupGuid ## PRODUCES ## Event
+
+[Pcd]
+ gPlatformModuleTokenSpaceGuid.PcdFlashFvMainBase ## CONSUMES
+ gPlatformModuleTokenSpaceGuid.PcdFlashFvRecoveryBase ## CONSUMES
+ gPlatformModuleTokenSpaceGuid.PcdFlashFvShellBase ## CONSUMES
+ gPlatformModuleTokenSpaceGuid.PcdFlashFvShellSize ## CONSUMES
+ gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut ## CONSUMES
+ gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdLogoFile ## CONSUMES
+ gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdShellFile ## CONSUMES
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSetupConOutColumn ## CONSUMES
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSetupConOutRow ## CONSUMES
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoHorizontalResolution ## CONSUMES
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoVerticalResolution ## CONSUMES
+ gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdBootState ## CONSUMES
+
+ gEfiEdkIIPlatformTokenSpaceGuid.PcdSystemConfiguration
+ gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## CONSUMES
diff --git a/BraswellPlatformPkg/Common/Library/PlatformBdsLib/PlatformBdsStrings.uni b/BraswellPlatformPkg/Common/Library/PlatformBdsLib/PlatformBdsStrings.uni new file mode 100644 index 0000000000..f8984da197 --- /dev/null +++ b/BraswellPlatformPkg/Common/Library/PlatformBdsLib/PlatformBdsStrings.uni @@ -0,0 +1,36 @@ +// /** @file
+// String definitions for Boot Option description.
+//
+// Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.<BR>
+//
+// This program and the accompanying materials
+// are licensed and made available under the terms and conditions of the BSD License
+// which accompanies this distribution. The full text of the license may be found at
+// http://opensource.org/licenses/bsd-license.php.
+//
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+// **/
+
+/=#
+
+#langdef en-US "English"
+#langdef fr-FR "Français"
+
+#string STR_DESCRIPTION_FLOPPY #language en-US "EFI Floppy"
+ #language fr-FR "fr-FR: EFI Floppy"
+#string STR_DESCRIPTION_CD_DVD #language en-US "EFI DVD/CDROM"
+ #language fr-FR "fr-FR: EFI DVD/CDROM"
+#string STR_DESCRIPTION_HARDDRIVE #language en-US "EFI Hard Drive"
+ #language fr-FR "fr-FR: EFI Hard Drive"
+#string STR_DESCRIPTION_USB #language en-US "EFI USB Device"
+ #language fr-FR "fr-FR: EFI USB Device"
+#string STR_DESCRIPTION_SCSI #language en-US "EFI SCSI Device"
+ #language fr-FR "fr-FR: EFI SCSI Device"
+#string STR_DESCRIPTION_MISC #language en-US "EFI Misc Device"
+ #language fr-FR "fr-FR: EFI Misc Device"
+#string STR_DESCRIPTION_NETWORK #language en-US "EFI Network"
+ #language fr-FR "fr-FR: EFI Network"
+#string STR_DESCRIPTION_NON_BLOCK #language en-US "EFI Non-Block Boot Device"
+ #language fr-FR "fr-FR: EFI Non-Block Boot Device"
diff --git a/BraswellPlatformPkg/Common/Library/PlatformBdsLib/PlatformData.c b/BraswellPlatformPkg/Common/Library/PlatformBdsLib/PlatformData.c new file mode 100644 index 0000000000..218b6e6177 --- /dev/null +++ b/BraswellPlatformPkg/Common/Library/PlatformBdsLib/PlatformData.c @@ -0,0 +1,277 @@ +/** @file
+ Defined the platform specific device path which will be used by
+ platform Bbd to perform the platform policy connect.
+
+ Copyright (c) 2004 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "BdsPlatform.h"
+
+//
+// Predefined platform default time out value
+//
+UINT16 gPlatformBootTimeOutDefault = 10;
+
+//
+// Predefined platform root bridge
+//
+PLATFORM_ROOT_BRIDGE_DEVICE_PATH gPlatformRootBridge0 = {
+ gPciRootBridge,
+ gEndEntire
+};
+
+EFI_DEVICE_PATH_PROTOCOL* gPlatformRootBridges [] = {
+ (EFI_DEVICE_PATH_PROTOCOL*)&gPlatformRootBridge0,
+ NULL
+};
+
+//
+// Platform specific ISA keyboard device path
+//
+PLATFORM_ISA_KEYBOARD_DEVICE_PATH gIsaKeyboardDevicePath = {
+ gPciRootBridge,
+ gPciIsaBridge,
+ gPnpPs2Keyboard,
+ gEndEntire
+};
+
+//
+// Platform specific on chip PCI VGA device path
+//
+PLATFORM_ONBOARD_VGA_DEVICE_PATH gOnChipPciVgaDevicePath = {
+ gPciRootBridge,
+ PCI_DEVICE_PATH_NODE(0, 0x2),
+ gEndEntire
+};
+
+//
+// Platform specific plug in PCI VGA device path
+//
+PLATFORM_OFFBOARD_VGA_DEVICE_PATH gPlugInPciVgaDevicePath = {
+ gPciRootBridge,
+ PCI_DEVICE_PATH_NODE(0, 0x1),
+ PCI_DEVICE_PATH_NODE(0, 0x0),
+ gEndEntire
+};
+
+//
+// Platform specific ISA serial device path
+//
+
+
+typedef struct {
+ UART_DEVICE_PATH Uart;
+ VENDOR_DEVICE_PATH TerminalType;
+ EFI_DEVICE_PATH_PROTOCOL End;
+} PLATFORM_PCI_SERIAL_DEVICE_PATH;
+
+//
+// Platform specific serial device path
+//
+PLATFORM_PCI_SERIAL_DEVICE_PATH mHsUartSerialIoDevicePath = {
+ {
+ MESSAGING_DEVICE_PATH,
+ MSG_UART_DP,
+ (UINT8) (sizeof (UART_DEVICE_PATH)),
+ (UINT8) ((sizeof (UART_DEVICE_PATH)) >> 8),
+ 0,
+ 115200, // default BaudRate
+ 8, // default DataBits
+ 1, // default Parity
+ 1, // default StopBits
+
+ },
+ {
+ MESSAGING_DEVICE_PATH,
+ MSG_VENDOR_DP,
+ (UINT8) (sizeof (VENDOR_DEVICE_PATH)),
+ (UINT8) ((sizeof (VENDOR_DEVICE_PATH)) >> 8),
+ DEVICE_PATH_MESSAGING_PC_ANSI
+ },
+ gEndEntire
+};
+
+//
+// Platform specific Button Array device path
+//
+HII_VENDOR_DEVICE_PATH gHiiVendorDevicePath0 = {
+ {
+ {
+ HARDWARE_DEVICE_PATH,
+ HW_VENDOR_DP,
+ {
+ (UINT8) (sizeof (VENDOR_DEVICE_PATH)),
+ (UINT8) ((sizeof (VENDOR_DEVICE_PATH)) >> 8)
+ }
+ },
+
+ //
+ // {C8752FDE-B5C8-4528-897D-6920FE771E38}
+ //
+ { 0xC8752FDE, 0xB5C8, 0x4528, { 0x89, 0x7D, 0x69, 0x20, 0xFE, 0x77, 0x1E, 0x38 } }
+ },
+ {
+ END_DEVICE_PATH_TYPE,
+ END_ENTIRE_DEVICE_PATH_SUBTYPE,
+ {
+ (UINT8) (END_DEVICE_PATH_LENGTH),
+ (UINT8) ((END_DEVICE_PATH_LENGTH) >> 8)
+ }
+ }
+};
+
+USB_CLASS_FORMAT_DEVICE_PATH gUsbClassKeyboardDevicePath = {
+ gUsbKeyboardMouse,
+ gEndEntire
+};
+
+//
+// Predefined platform default console device path
+//
+BDS_CONSOLE_CONNECT_ENTRY gPlatformConsole [] = {
+ {(EFI_DEVICE_PATH_PROTOCOL*)&mHsUartSerialIoDevicePath, CONSOLE_ALL},
+ {(EFI_DEVICE_PATH_PROTOCOL*)&gHiiVendorDevicePath0, CONSOLE_IN},
+ {(EFI_DEVICE_PATH_PROTOCOL*)&gIsaKeyboardDevicePath, CONSOLE_IN},
+ {(EFI_DEVICE_PATH_PROTOCOL*)&gUsbClassKeyboardDevicePath, CONSOLE_IN},
+ {NULL, 0}
+};
+
+//
+// All the possible platform PCI VGA device path
+//
+EFI_DEVICE_PATH_PROTOCOL* gPlatformAllPossiblePciVgaConsole [] = {
+ (EFI_DEVICE_PATH_PROTOCOL*)&gOnChipPciVgaDevicePath,
+ (EFI_DEVICE_PATH_PROTOCOL*)&gPlugInPciVgaDevicePath,
+ NULL
+};
+
+//
+// Legacy hard disk boot option
+//
+LEGACY_HD_DEVICE_PATH gLegacyHd = {
+ {
+ BBS_DEVICE_PATH,
+ BBS_BBS_DP,
+ (UINT8)(sizeof(BBS_BBS_DEVICE_PATH)),
+ (UINT8)((sizeof(BBS_BBS_DEVICE_PATH)) >> 8),
+ BBS_TYPE_HARDDRIVE,
+ 0,
+ 0
+ },
+ gEndEntire
+};
+
+//
+// Legacy cdrom boot option
+//
+LEGACY_HD_DEVICE_PATH gLegacyCdrom = {
+ {
+ BBS_DEVICE_PATH,
+ BBS_BBS_DP,
+ (UINT8)(sizeof(BBS_BBS_DEVICE_PATH)),
+ (UINT8)((sizeof(BBS_BBS_DEVICE_PATH)) >> 8),
+ BBS_TYPE_CDROM,
+ 0,
+ 0
+ },
+ gEndEntire
+};
+
+//
+// Predefined platform specific predict boot option
+//
+EFI_DEVICE_PATH_PROTOCOL* gPlatformBootOption [] = {
+ (EFI_DEVICE_PATH_PROTOCOL*)&gLegacyHd,
+ (EFI_DEVICE_PATH_PROTOCOL*)&gLegacyCdrom,
+ NULL
+};
+
+//
+// Predefined platform specific driver option
+//
+EFI_DEVICE_PATH_PROTOCOL* gPlatformDriverOption [] = {
+ NULL
+};
+
+//
+// Platform specific SATA controller device path
+//
+#ifdef SATA_SUPPORT
+PLATFORM_PCI_DEVICE_PATH gSataBootDevPath0 = {
+ gPciRootBridge,
+ PCI_DEVICE_PATH_NODE (0x00, 0x13),
+ gEndEntire
+};
+#endif
+
+//
+// Predefined platform connect sequence
+//
+EFI_DEVICE_PATH_PROTOCOL* gPlatformConnectSequence [] = {
+ (EFI_DEVICE_PATH_PROTOCOL *)&gPlatformRootBridge0, // Force PCI enumeration before Legacy OpROM shadow
+#ifdef SATA_SUPPORT
+ (EFI_DEVICE_PATH_PROTOCOL *)&gSataBootDevPath0, // Make sure disk controller is connected before S3 boot script is locked
+#endif
+ NULL
+};
+
+//
+// Platform specific USB controller device path
+//
+PLATFORM_USB_DEVICE_PATH gUsbDevicePath0 = {
+ gPciRootBridge,
+ PCI_DEVICE_PATH_NODE(0, 0x14),
+ gEndEntire
+};
+
+//
+// Predefined platform device path for user authentication
+//
+EFI_DEVICE_PATH_PROTOCOL* gUserAuthenticationDevice[] = {
+ //
+ // Predefined device path for secure card (USB disk).
+ //
+ (EFI_DEVICE_PATH_PROTOCOL*)&gUsbDevicePath0,
+ NULL
+};
+
+//
+// Predefined platform console device path
+//
+BDS_CONSOLE_CONNECT_ENTRY gPlatformSimpleConsole [] = {
+ {(EFI_DEVICE_PATH_PROTOCOL*)&gOnChipPciVgaDevicePath, CONSOLE_OUT},
+ {(EFI_DEVICE_PATH_PROTOCOL*)&mHsUartSerialIoDevicePath, CONSOLE_ALL},
+ {(EFI_DEVICE_PATH_PROTOCOL*)&gHiiVendorDevicePath0, CONSOLE_IN},
+ {(EFI_DEVICE_PATH_PROTOCOL*)&gUsbClassKeyboardDevicePath, CONSOLE_IN},
+ {NULL, 0}
+};
+
+//
+// eMMC device at BDF(0x0, 0x10, 0x0)
+//
+PLATFORM_PCI_DEVICE_PATH gEmmcBootDevPath0 = {
+ gPciRootBridge,
+ PCI_DEVICE_PATH_NODE (0x00, 0x10),
+ gEndEntire
+};
+
+//
+// Predefined platform specific predict boot option
+//
+EFI_DEVICE_PATH_PROTOCOL* gPlatformSimpleBootOption [] = {
+ (EFI_DEVICE_PATH_PROTOCOL*)&gEmmcBootDevPath0,
+#ifdef SATA_SUPPORT
+ (EFI_DEVICE_PATH_PROTOCOL *)&gSataBootDevPath0,
+#endif
+ NULL
+};
+
diff --git a/BraswellPlatformPkg/Common/Library/PlatformHookLib/PlatformHookLib.c b/BraswellPlatformPkg/Common/Library/PlatformHookLib/PlatformHookLib.c new file mode 100644 index 0000000000..223ad836d7 --- /dev/null +++ b/BraswellPlatformPkg/Common/Library/PlatformHookLib/PlatformHookLib.c @@ -0,0 +1,250 @@ +/** @file
+ Null Platform Hook Library instance.
+
+ Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Base.h>
+#include <Library/PlatformHookLib.h>
+
+#include <Library/PcdLib.h>
+#include <Library/IoLib.h>
+#include <Library/PciLib.h>
+#include <PchRegs.h>
+#include <PlatformBaseAddresses.h>
+#include <IndustryStandard/Pci.h>
+
+
+
+
+#define PCI_IDX 0xCF8
+#define PCI_DAT 0xCFC
+
+#define PCI_LPC_BASE (0x8000F800)
+#define PCI_LPC_REG(x) (PCI_LPC_BASE + (x))
+
+#define V_PCH_ILB_IRQE_UARTIRQEN_IRQ4 BIT4 // UART IRQ4 Enable
+#ifndef PCIEX_BASE_ADDRESS
+#define PCIEX_BASE_ADDRESS ((UINTN)PcdGet64(PcdPciExpressBaseAddress))
+#endif
+#define PciD31F0RegBase PCIEX_BASE_ADDRESS + (UINT32) (31 << 15)
+
+VOID
+EnableInternalUart (
+ VOID
+ )
+{
+ //
+ // Program and enable PMC Base.
+ //
+ IoWrite32 (PCI_IDX, PCI_LPC_REG(R_PCH_LPC_PMC_BASE));
+ IoWrite32 (PCI_DAT, (PMC_BASE_ADDRESS | B_PCH_LPC_PMC_BASE_EN));
+
+ //
+ // Program and enable iLB Base.
+ //
+ IoWrite32 (PCI_IDX, PCI_LPC_REG(R_PCH_LPC_ILB_BASE));
+ IoWrite32 (PCI_DAT, (ILB_BASE_ADDRESS | B_PCH_LPC_ILB_BASE_EN));
+ //
+ // Enable internal UART interrupt.
+ //
+ MmioOr32 (ILB_BASE_ADDRESS + R_PCH_ILB_IRQE, (UINT32) (B_PCH_ILB_IRQE_UARTIRQEN_IRQ4));
+ //
+ // GPIO: N67(HV_DDI2_DDC_SCL) - Setting Mode 3
+ // UART0_TXD
+ //
+ MmioWrite32 ((UINTN) (IO_BASE_ADDRESS + 0xD438), (UINT32) 0x00930300);
+ //
+ // GPIO: N62(HV_DDI2_DDC_SDA) - Setting Mode 3
+ // UART0_RXD
+ //
+ MmioWrite32 ((UINTN) (IO_BASE_ADDRESS + 0xD410), (UINT32) 0x00930300);
+ MmioOr32 (
+ (UINTN) (PciD31F0RegBase + R_PCH_LPC_UART_CTRL),
+ (UINT32) (B_PCH_LPC_UART_CTRL_COM1_EN)
+ );
+}
+
+
+#define MC_MCR 0x000000D0
+#define MC_MDR 0x000000D4
+#define MC_MCRX 0x000000D8
+#define MC_MCRXX 0x000000DC
+
+#define MSG_BUS_ENABLED 0x000000F0
+#define MSGBUS_MASKHI 0xFFFFFF00
+#define MSGBUS_MASKLO 0x000000FF
+
+#define MESSAGE_BYTE_EN BIT4
+#define MESSAGE_WORD_EN BIT4 | BIT5
+#define MESSAGE_DWORD_EN BIT4 | BIT5 | BIT6 | BIT7
+
+#define SIDEBAND_OPCODE 0x78
+#define MEMREAD_OPCODE 0x00000000
+#define MEMWRITE_OPCODE 0x01000000
+
+
+RETURN_STATUS
+PlatformPchMsgBusAndThenOrEx32 (
+ IN UINT8 PortId,
+ IN UINT32 Register,
+ IN UINT32 AndData,
+ IN UINT32 OrData,
+ IN UINT8 ReadOpCode,
+ IN UINT8 WriteOpCode,
+ IN UINT8 Bar, OPTIONAL
+ IN UINT8 Device, OPTIONAL
+ IN UINT8 Function OPTIONAL
+ )
+{
+ UINT32 Data32;
+ UINTN PciExpressBase;
+
+ PciExpressBase = (UINTN) PcdGet64 (PcdPciExpressBaseAddress);
+ //PciExpressBase = 0xE0000000;
+
+ MmioWrite32 (
+ (UINTN) (PciExpressBase + MC_MCRXX),
+ (UINT32) (((Bar & 0x07) << 8) | (((Device << 3) | (Function)) & 0xFF))
+ );
+ MmioWrite32 (
+ (UINTN) (PciExpressBase + MC_MCRX),
+ (UINT32) (Register & MSGBUS_MASKHI)
+ );
+ MmioWrite32 (
+ (UINTN) (PciExpressBase + MC_MCR),
+ (UINT32) ((ReadOpCode << 24) | (PortId << 16) | ((Register & MSGBUS_MASKLO) << 8) | MESSAGE_DWORD_EN)
+ );
+ Data32 = MmioRead32 ((UINTN) (PciExpressBase + MC_MDR));
+ Data32 = (UINT32) ((Data32 & AndData) | OrData);
+
+
+ MmioWrite32 (
+ (UINTN) (PciExpressBase + MC_MCRXX),
+ (UINT32) (((Bar & 0x07) << 8) | (((Device << 3) | (Function)) & 0xFF))
+ );
+ MmioWrite32 (
+ (UINTN) (PciExpressBase + MC_MCRX),
+ (UINT32) (Register & MSGBUS_MASKHI)
+ );
+ MmioWrite32 (
+ (UINTN) (PciExpressBase + MC_MDR),
+ (UINT32) (Data32)
+ );
+ MmioWrite32 (
+ (UINTN) (PciExpressBase + MC_MCR),
+ (UINT32) ((WriteOpCode << 24) | (PortId << 16) | ((Register & MSGBUS_MASKLO) << 8) | MESSAGE_DWORD_EN)
+ );
+
+ return RETURN_SUCCESS;
+}
+
+VOID
+EnableLpssHsUart (
+ VOID
+ )
+{
+ UINTN PciLibAddress;
+ UINT32 LpssMmioBase0;
+ UINT32 Buffer32;
+
+ //
+ //LPSS HS-UART0
+ //UART1_CTS_B 1 UART1_CTS_B IOBASE + 0x04818 [31:0] = 0x00910300
+ //UART1_RTS_B 1 UART1_RTS_B IOBASE + 0x04800 [31:0] = 0x00910300
+ //UART1_RXD 1 UART1_RXD IOBASE + 0x04808 [31:0] = 0x00910300
+ //UART1_TXD 1 UART1_TXD IOBASE + 0x04828 [31:0] = 0x00910300
+ MmioWrite32 ((UINTN) (IO_BASE_ADDRESS + 0x04818), (UINT32) 0x00910300);
+ MmioWrite32 ((UINTN) (IO_BASE_ADDRESS + 0x04800), (UINT32) 0x00910300);
+ MmioWrite32 ((UINTN) (IO_BASE_ADDRESS + 0x04808), (UINT32) 0x00910300);
+ MmioWrite32 ((UINTN) (IO_BASE_ADDRESS + 0x04828), (UINT32) 0x00910300);
+
+ PlatformPchMsgBusAndThenOrEx32(
+ 0xA0,
+ 0x258,
+ 0xFFFFFFFF,
+ (BIT27),
+ 0x06,
+ 0x07,
+ 0x00,
+ 0x00,
+ 0x00
+ );
+
+ PciLibAddress = PCI_LIB_ADDRESS (0, 30, 3, 0);
+ PciWrite32 ((PciLibAddress + PCI_BASE_ADDRESSREG_OFFSET), (UINT32)PcdGet64 (PcdSerialRegisterBase));
+ LpssMmioBase0 = (UINT32)PcdGet64 (PcdSerialRegisterBase);
+
+ PciOr16 (PciLibAddress + PCI_COMMAND_OFFSET, (EFI_PCI_COMMAND_BUS_MASTER | EFI_PCI_COMMAND_MEMORY_SPACE));
+
+ Buffer32 = (UINT32) (B_PCH_LPSS_HSUART_MEM_PCP_CLKUPDATE |
+ (0x3D09 << 16) |
+ (0x1B00 << 1) |
+ B_PCH_LPSS_HSUART_MEM_PCP_CLKEN);
+ MmioWrite32 (
+ (UINTN) (LpssMmioBase0 + R_PCH_LPSS_HSUART_MEM_PCP),
+ Buffer32
+ );
+
+ Buffer32 = (UINT32) (B_PCH_LPSS_HSUART_MEM_RESETS_FUNC | B_PCH_LPSS_HSUART_MEM_RESETS_APB);
+ MmioWrite32 (
+ (UINTN) (LpssMmioBase0 + R_PCH_LPSS_HSUART_MEM_RESETS),
+ Buffer32
+ );
+
+ PlatformPchMsgBusAndThenOrEx32 (
+ 0xA0,
+ 0x258,
+ (UINT32) ~((BIT19 | BIT18)),
+ (BIT18 | BIT1),
+ 0x06,
+ 0x07,
+ 0x00,
+ 0x00,
+ 0x00
+ );
+
+ return;
+}
+
+/**
+ Performs platform specific initialization required for the CPU to access
+ the hardware associated with a SerialPortLib instance. This function does
+ not intiailzie the serial port hardware itself. Instead, it initializes
+ hardware devices that are required for the CPU to access the serial port
+ hardware. This function may be called more than once.
+
+ @retval RETURN_SUCCESS The platform specific initialization succeeded.
+ @retval RETURN_DEVICE_ERROR The platform specific initialization could not be completed.
+
+**/
+RETURN_STATUS
+EFIAPI
+PlatformHookSerialPortInitialize (
+ VOID
+ )
+{
+ if (PcdGet64 (PcdSerialRegisterBase) == 0) {
+ return RETURN_SUCCESS;
+ }
+
+ if ((BOOLEAN)PcdGetBool (PcdSerialUseMmio) == FALSE) {
+
+ EnableInternalUart ();
+ } else {
+
+ EnableLpssHsUart();
+ }
+
+ return RETURN_SUCCESS;
+}
+
diff --git a/BraswellPlatformPkg/Common/Library/PlatformHookLib/PlatformHookLib.inf b/BraswellPlatformPkg/Common/Library/PlatformHookLib/PlatformHookLib.inf new file mode 100644 index 0000000000..7d2011cd93 --- /dev/null +++ b/BraswellPlatformPkg/Common/Library/PlatformHookLib/PlatformHookLib.inf @@ -0,0 +1,48 @@ +## @file
+# Platform Hook Library instance.
+#
+# Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.<BR>
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php.
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010018
+ BASE_NAME = PlatformHookLib
+ FILE_GUID = 6462DD47-B4E0-49CC-808D-B6B209F8C126
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = PlatformHookLib
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = IA32 X64 IPF EBC
+#
+
+[Sources]
+ PlatformHookLib.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ ChvRefCodePkg/ChvRefCodePkg.dec
+
+[LibraryClasses]
+ PcdLib
+ IoLib
+ PciLib
+
+[Pcd]
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase ## CONSUMES
+ gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## CONSUMES
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseMmio
+ gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
diff --git a/BraswellPlatformPkg/Common/Library/PlatformSecureLib/PlatformSecureLib.c b/BraswellPlatformPkg/Common/Library/PlatformSecureLib/PlatformSecureLib.c new file mode 100644 index 0000000000..bc7d83fabf --- /dev/null +++ b/BraswellPlatformPkg/Common/Library/PlatformSecureLib/PlatformSecureLib.c @@ -0,0 +1,47 @@ +/** @file
+ Provides a secure platform-specific method to clear PK(Platform Key).
+
+ Copyright (c) 2011 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Library/PcdLib.h>
+#include <Guid/SetupVariable.h>
+
+/**
+ This function provides a platform-specific method to detect whether the platform
+ is operating by a physically present user.
+
+ Programmatic changing of platform security policy (such as disable Secure Boot,
+ or switch between Standard/Custom Secure Boot mode) MUST NOT be possible during
+ Boot Services or after exiting EFI Boot Services. Only a physically present user
+ is allowed to perform these operations.
+
+ NOTE THAT: This function cannot depend on any EFI Variable Service since they are
+ not available when this function is called in AuthenticateVariable driver.
+
+ @retval TRUE The platform is operated by a physically present user.
+ @retval FALSE The platform is NOT operated by a physically present user.
+
+**/
+BOOLEAN
+EFIAPI
+UserPhysicalPresent (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+ SYSTEM_CONFIGURATION SystemConfiguration;
+
+ CopyMem (&SystemConfiguration, PcdGetPtr (PcdSystemConfiguration), sizeof(SYSTEM_CONFIGURATION));
+
+ return (SystemConfiguration->SecureBootUserPhysicalPresent == 1);
+}
diff --git a/BraswellPlatformPkg/Common/Library/PlatformSecureLib/PlatformSecureLib.inf b/BraswellPlatformPkg/Common/Library/PlatformSecureLib/PlatformSecureLib.inf new file mode 100644 index 0000000000..651c363e03 --- /dev/null +++ b/BraswellPlatformPkg/Common/Library/PlatformSecureLib/PlatformSecureLib.inf @@ -0,0 +1,40 @@ +## @file
+# Provides a secure platform-specific method to clear PK(Platform Key).
+#
+# Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php.
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = PlatformSecureLib
+ FILE_GUID = 4204D78D-EDBF-4cee-BE80-3881457CF344
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = PlatformSecureLib|DXE_RUNTIME_DRIVER DXE_SMM_DRIVER
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = IA32 X64 IPF EBC
+#
+
+[Sources]
+ PlatformSecureLib.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ BraswellPlatformPkg/BraswellPlatformPkg.dec
+
+[LibraryClasses]
+ PcdLib
+
+[Pcd]
diff --git a/BraswellPlatformPkg/Common/Library/RecoveryOemHookLib/CommonHeader.h b/BraswellPlatformPkg/Common/Library/RecoveryOemHookLib/CommonHeader.h new file mode 100644 index 0000000000..701e2ca26b --- /dev/null +++ b/BraswellPlatformPkg/Common/Library/RecoveryOemHookLib/CommonHeader.h @@ -0,0 +1,31 @@ +/** @file
+ Common header file shared by all source files.
+ This file includes package header files, library classes and protocol, PPI & GUID definitions.
+
+ Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __COMMON_HEADER_H_
+#define __COMMON_HEADER_H_
+
+
+
+#include <PiPei.h>
+
+#include <Ppi/DeviceRecoveryModule.h>
+
+#include <Library/RecoveryOemHookLib.h>
+#include <Library/DebugLib.h>
+#include <Library/PeiServicesTablePointerLib.h>
+#include <Library/PeiServicesLib.h>
+
+#endif
diff --git a/BraswellPlatformPkg/Common/Library/RecoveryOemHookLib/RecoveryOemHookLib.c b/BraswellPlatformPkg/Common/Library/RecoveryOemHookLib/RecoveryOemHookLib.c new file mode 100644 index 0000000000..4a4f61c17d --- /dev/null +++ b/BraswellPlatformPkg/Common/Library/RecoveryOemHookLib/RecoveryOemHookLib.c @@ -0,0 +1,121 @@ +/** @file
+ This file includes the function that can be customized by OEM.
+
+ Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+
+#include "CommonHeader.h"
+
+/**
+ The recovery capsule is determined by 2 factors,
+ 1. The device search order, if more than one Device Recovery Module PPI
+ was discovered
+ 2. The individual search order, if the device reported more than one recovery
+ DXE capsule was found generating a search order list.
+
+ The 2 orders are decided by the RecoveryOemHook library function OemRecoveryRankCapsule().
+
+ @param[in, out] DeviceInstance Specifies which EFI_PEI_DEVICE_RECOVERY_MODULE_PPI instance
+ to retrieve when passed out. Specifies from which EFI_PEI_DEVICE_RECOVERY_MODULE_PPI
+ instance to start when passed in. The index start from zero.
+ @param[in, out] CapsuleInstance Specifies which recovery capsule to retrieve when passed out.
+ Specifies from which recovery capsule to start when passed in. The index start from zero.
+ @param[out] DeviceRecoveryModule If it's not NULL, it's EFI_PEI_DEVICE_RECOVERY_MODULE_PPI.
+ instance specified by DeviceInstance, caller can use this instance directly. The
+ function will change DeviceRecoveryModule to NULL, if it doesn't return a PPI instance.
+ @param[out] CapsuleBuffer If it's not NULL, it contains loaded capsule, caller can use it directly.
+ The function will change Buffer to NULL, if it doesn't load a capsule.
+
+ @retval TRUE If a recovery capsule is found.
+ @retval FALSE If no recovery capsule found.
+
+**/
+BOOLEAN
+EFIAPI
+OemRecoveryRankCapsule (
+ IN OUT UINTN *DeviceInstance,
+ IN OUT UINTN *CapsuleInstance,
+ OUT EFI_PEI_DEVICE_RECOVERY_MODULE_PPI **DeviceRecoveryModule, OPTIONAL
+ OUT VOID **CapsuleBuffer OPTIONAL
+ )
+{
+ EFI_PEI_SERVICES **PeiServices;
+ UINTN NumberRecoveryCapsules;
+ EFI_STATUS DeviceFound;
+ EFI_STATUS CapsuleFound;
+
+ //
+ // Return the first found capsule.
+ // OEM can override this implementation to support complex priority.
+ //
+
+ ASSERT (DeviceRecoveryModule != NULL);
+ ASSERT (CapsuleBuffer != NULL);
+
+ if ((*DeviceInstance) != 0 || (*CapsuleInstance) != 1) {
+ return FALSE;
+ }
+
+ PeiServices = (EFI_PEI_SERVICES **) GetPeiServicesTablePointer ();
+ NumberRecoveryCapsules = 0;
+ DeviceFound = EFI_SUCCESS;
+ CapsuleFound = EFI_NOT_FOUND;
+ (*DeviceRecoveryModule) = NULL;
+ (*CapsuleBuffer) = NULL;
+
+ //
+ // If no new Device found, end search.
+ // If device has at least 1 capsule, end search.
+ //
+ while (!EFI_ERROR (DeviceFound) && NumberRecoveryCapsules == 0) {
+ DeviceFound = PeiServicesLocatePpi (
+ &gEfiPeiDeviceRecoveryModulePpiGuid,
+ *DeviceInstance,
+ NULL,
+ (VOID **) DeviceRecoveryModule
+ );
+
+ if (!EFI_ERROR (DeviceFound)) {
+ DEBUG ((EFI_D_INFO | EFI_D_LOAD, "OEM Device Recovery PPI located\n"));
+
+ CapsuleFound = (*DeviceRecoveryModule)->GetNumberRecoveryCapsules (
+ PeiServices,
+ *DeviceRecoveryModule,
+ &NumberRecoveryCapsules
+ );
+ if (NumberRecoveryCapsules == 0) {
+ (*DeviceInstance) ++;
+ } else {
+ *CapsuleInstance = 1;
+ }
+ }
+ }
+
+ return (BOOLEAN)(NumberRecoveryCapsules > 0);
+}
+
+/**
+ This function performe security check and check failure handling,
+
+ @param Buffer The caller allocated buffer that contains recovery capsule to be checked.
+
+ @retval TRUE If it's secure.
+**/
+BOOLEAN
+EFIAPI
+OemRecoverySecurityCheck (
+ VOID *Buffer
+ )
+{
+ return TRUE;
+}
diff --git a/BraswellPlatformPkg/Common/Library/RecoveryOemHookLib/RecoveryOemHookLib.inf b/BraswellPlatformPkg/Common/Library/RecoveryOemHookLib/RecoveryOemHookLib.inf new file mode 100644 index 0000000000..05be34e2a7 --- /dev/null +++ b/BraswellPlatformPkg/Common/Library/RecoveryOemHookLib/RecoveryOemHookLib.inf @@ -0,0 +1,49 @@ +## @file
+# Recovery Hook Library
+#
+# Provides a minimal implementation for capsule ranking and integrity verification.
+# This implementation returns the first capsule found and assumes all capsules
+# are valid.
+#
+# Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.<BR>
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php.
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = RecoveryOemHookLib
+ FILE_GUID = DE6D4FB9-12DB-4dbb-ACF1-92514388355F
+ MODULE_TYPE = PEIM
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = RecoveryOemHookLib|PEIM
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = IA32
+#
+
+[Sources]
+ RecoveryOemHookLib.c
+ CommonHeader.h
+
+[Packages]
+ MdePkg/MdePkg.dec
+ BraswellPlatformPkg/BraswellPlatformPkg.dec
+
+[LibraryClasses]
+ PeiServicesLib
+ PeiServicesTablePointerLib
+ DebugLib
+
+[Ppis]
+ gEfiPeiDeviceRecoveryModulePpiGuid ## SOMETIMES_CONSUMES
+
diff --git a/BraswellPlatformPkg/Common/Library/ResetSystemLib/ResetSystemLib.c b/BraswellPlatformPkg/Common/Library/ResetSystemLib/ResetSystemLib.c new file mode 100644 index 0000000000..2419968178 --- /dev/null +++ b/BraswellPlatformPkg/Common/Library/ResetSystemLib/ResetSystemLib.c @@ -0,0 +1,160 @@ +/** @file
+ System reset Library Services. This library class provides a set of
+ methods to reset whole system with manipulate ICH.
+
+ Copyright (c) 2007 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Base.h>
+#include <Library/ResetSystemLib.h>
+#include <Library/BaseLib.h>
+#include <Library/IoLib.h>
+#include <Library/DebugLib.h>
+#include <Library/PciLib.h>
+#include <PchRegs.h>
+#include <Rsci.h>
+
+#define RESET_GENERATOR_PORT R_PCH_RST_CNT
+
+VOID
+EFIAPI
+PlatformResetHook (
+ UINT8 ResetType
+ )
+{
+}
+
+/**
+ Calling this function causes a system-wide reset. This sets
+ all circuitry within the system to its initial state. This type of reset
+ is asynchronous to system operation and operates without regard to
+ cycle boundaries.
+
+ System reset should not return, if it returns, it means the system does
+ not support cold reset.
+**/
+VOID
+EFIAPI
+ResetCold (
+ VOID
+ )
+{
+ PlatformResetHook(COLD_RESET);
+ IoWrite8 (RESET_GENERATOR_PORT, 0x2);
+ IoWrite8 (RESET_GENERATOR_PORT, 0x6);
+}
+
+/**
+ Calling this function causes a system-wide initialization. The processors
+ are set to their initial state, and pending cycles are not corrupted.
+
+ System reset should not return, if it returns, it means the system does
+ not support warm reset.
+**/
+VOID
+EFIAPI
+ResetWarm (
+ VOID
+ )
+{
+ PlatformResetHook(WARM_RESET);
+ IoWrite8 (RESET_GENERATOR_PORT, 0x0);
+ IoWrite8 (RESET_GENERATOR_PORT, 0x4);
+}
+
+/**
+ Calling this function causes the system to enter a power state equivalent
+ to the ACPI G2/S5 or G3 states.
+
+ System shutdown should not return, if it returns, it means the system does
+ not support shut down reset.
+**/
+VOID
+EFIAPI
+ResetShutdown (
+ VOID
+ )
+{
+ UINT16 IchPmioBase;
+ UINT16 Data16;
+ UINT32 Data32;
+
+ //
+ // Firstly, ACPI decode must be enabled
+ //
+ PciOr8 (
+ PCI_LIB_ADDRESS(PCI_BUS_NUMBER_ICH, PCI_DEVICE_NUMBER_ICH_LPC, 0, R_ICH_LPC_ACPI_CNT),
+ (UINT8) (B_ICH_LPC_ACPI_CNT_ACPI_EN)
+ );
+
+ IchPmioBase = (UINT16) (PciRead16 (PCI_LIB_ADDRESS(PCI_BUS_NUMBER_ICH, PCI_DEVICE_NUMBER_ICH_LPC, 0, R_ICH_LPC_ACPI_BASE)) & ~BIT0);
+
+ //
+ // Then, GPE0_EN should be disabled to avoid any GPI waking up the system from S5
+ //
+ Data16 = 0;
+ IoWrite16 (
+ (UINTN)(IchPmioBase + R_ACPI_GPE0_EN),
+ (UINT16)Data16
+ );
+
+ //
+ // Secondly, PwrSts register must be cleared
+ //
+ // Write a "1" to bit[8] of power button status register at
+ // (PM_BASE + PM1_STS_OFFSET) to clear this bit
+ //
+ Data16 = B_PWRBTN_STS;
+ IoWrite16 (
+ (UINTN)(IchPmioBase + R_ACPI_PM1_STS),
+ (UINT16)Data16
+ );
+
+ //
+ // Finally, transform system into S5 sleep state
+ //
+ Data32 = IoRead32 ((UINTN)(IchPmioBase + R_ACPI_PM1_CNT));
+
+ Data32 = (UINT32) ((Data32 & ~(B_SLP_TYP + B_SLP_EN)) | V_S5);
+
+ IoWrite32 (
+ (UINTN) (IchPmioBase + R_ACPI_PM1_CNT),
+ (UINT32)Data32
+ );
+
+ Data32 = Data32 | B_SLP_EN;
+
+ IoWrite32 (
+ (UINTN) (IchPmioBase + R_ACPI_PM1_CNT),
+ (UINT32)Data32
+ );
+
+ return;
+}
+
+/**
+ Calling this function causes the system to enter a power state for capsule
+ update.
+
+ Reset update should not return, if it returns, it means the system does
+ not support capsule update.
+
+**/
+VOID
+EFIAPI
+EnterS3WithImmediateWake (
+ VOID
+ )
+{
+ ASSERT (FALSE);
+}
+
diff --git a/BraswellPlatformPkg/Common/Library/ResetSystemLib/ResetSystemLib.inf b/BraswellPlatformPkg/Common/Library/ResetSystemLib/ResetSystemLib.inf new file mode 100644 index 0000000000..0ae3d79e8f --- /dev/null +++ b/BraswellPlatformPkg/Common/Library/ResetSystemLib/ResetSystemLib.inf @@ -0,0 +1,50 @@ +## @file
+# Component description file for Intel Ich7 Reset System Library.
+#
+# Reset System Library that layers on top of the I/O Library to directly
+# access a standard SMBUS host controller.
+#
+# Copyright (c) 2007 - 2015, Intel Corporation. All rights reserved.<BR>
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php.
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = ResetSystemLib
+ FILE_GUID = D4FF05AA-3C7D-4b8a-A1EE-AA5EFA0B1732
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = ResetSystemLib
+ EDK_RELEASE_VERSION = 0x00020000
+ EFI_SPECIFICATION_VERSION = 0x00020000
+
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = IA32 X64 IPF
+#
+
+[Sources.common]
+ ResetSystemLib.c
+
+
+[Packages]
+ BraswellPlatformPkg/BraswellPlatformPkg.dec
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ ChvRefCodePkg/ChvRefCodePkg.dec
+
+[LibraryClasses]
+ IoLib
+ BaseLib
+ DebugLib
+ PciLib
diff --git a/BraswellPlatformPkg/Common/Library/SmmIo/SmmIo.c b/BraswellPlatformPkg/Common/Library/SmmIo/SmmIo.c new file mode 100644 index 0000000000..3b0d4fc45d --- /dev/null +++ b/BraswellPlatformPkg/Common/Library/SmmIo/SmmIo.c @@ -0,0 +1,355 @@ +/** @file
+ SMM I/O access utility implementation file, for Ia32
+
+ Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+//
+// Include files
+//
+#include "Library/SmmIoLib.h"
+
+/**
+ Do a one byte IO read
+
+ @param[in] Address IO address to read
+
+ @return Data read
+
+**/
+UINT8
+SmmIoRead8 (
+ IN UINT16 Address
+ )
+{
+ UINT8 Buffer;
+
+ ASSERT (mSmst);
+
+ mSmst->SmmIo.Io.Read (
+ &mSmst->SmmIo,
+ SMM_IO_UINT8,
+ Address,
+ 1,
+ &Buffer
+ );
+
+ return Buffer;
+}
+
+/**
+ Do a one byte IO write
+
+ @param[in] Address IO address to write
+ @param[in] Data Data to write
+
+**/
+VOID
+SmmIoWrite8 (
+ IN UINT16 Address,
+ IN UINT8 Data
+ )
+{
+ ASSERT (mSmst);
+
+ mSmst->SmmIo.Io.Write (
+ &mSmst->SmmIo,
+ SMM_IO_UINT8,
+ Address,
+ 1,
+ &Data
+ );
+}
+
+/**
+ Do a two byte IO read
+
+ @param[in] Address IO address to read
+
+ @return Data read
+
+**/
+UINT16
+SmmIoRead16 (
+ IN UINT16 Address
+ )
+{
+ UINT16 Buffer;
+
+ ASSERT (mSmst);
+
+ mSmst->SmmIo.Io.Read (
+ &mSmst->SmmIo,
+ SMM_IO_UINT16,
+ Address,
+ 1,
+ &Buffer
+ );
+
+ return Buffer;
+}
+
+/**
+ Do a two byte IO write
+
+ @param[in] Address IO address to write
+ @param[in] Data Data to write
+
+**/
+VOID
+SmmIoWrite16 (
+ IN UINT16 Address,
+ IN UINT16 Data
+ )
+{
+ ASSERT (mSmst);
+
+ mSmst->SmmIo.Io.Write (
+ &mSmst->SmmIo,
+ SMM_IO_UINT16,
+ Address,
+ 1,
+ &Data
+ );
+}
+
+/**
+ Do a four byte IO read
+
+ @param[in] Address IO address to read
+
+ @retval Data read
+
+**/
+UINT32
+SmmIoRead32 (
+ IN UINT16 Address
+ )
+{
+ UINT32 Buffer;
+
+ ASSERT (mSmst);
+
+ mSmst->SmmIo.Io.Read (
+ &mSmst->SmmIo,
+ SMM_IO_UINT32,
+ Address,
+ 1,
+ &Buffer
+ );
+
+ return Buffer;
+}
+
+/**
+ Do a four byte IO write
+
+ @param[in] Address IO address to write
+ @param[in] Data Data to write
+
+**/
+VOID
+SmmIoWrite32 (
+ IN UINT16 Address,
+ IN UINT32 Data
+ )
+{
+ ASSERT (mSmst);
+
+ mSmst->SmmIo.Io.Write (
+ &mSmst->SmmIo,
+ SMM_IO_UINT32,
+ Address,
+ 1,
+ &Data
+ );
+}
+
+/**
+ Do a one byte Memory write
+
+ @param[in] Dest Memory address to write
+ @param[in] Data Data to write
+
+**/
+VOID
+SmmMemWrite8 (
+ IN UINT64 Dest,
+ IN UINT8 Data
+ )
+{
+ mSmst->SmmIo.Mem.Write (
+ &mSmst->SmmIo,
+ SMM_IO_UINT8,
+ Dest,
+ 1,
+ &Data
+ );
+
+ return ;
+}
+
+/**
+ Do a one byte Memory read
+
+ @param[in] Dest Memory address to read
+
+ @Return Data read
+
+**/
+UINT8
+SmmMemRead8 (
+ IN UINT64 Dest
+ )
+{
+ UINT8 Data;
+ mSmst->SmmIo.Mem.Read (
+ &mSmst->SmmIo,
+ SMM_IO_UINT8,
+ Dest,
+ 1,
+ &Data
+ );
+
+ return Data;
+}
+
+/**
+ Do a two bytes Memory write
+
+ @param[in] Dest Memory address to write
+ @param[in] Data Data to write
+
+**/
+VOID
+SmmMemWrite16 (
+ IN UINT64 Dest,
+ IN UINT16 Data
+ )
+{
+ mSmst->SmmIo.Mem.Write (
+ &mSmst->SmmIo,
+ SMM_IO_UINT16,
+ Dest,
+ 1,
+ &Data
+ );
+
+ return ;
+}
+
+/**
+ Do a two bytes Memory read
+
+ @param[in] Dest Memory address to read
+
+ @return Data read
+
+**/
+UINT16
+SmmMemRead16 (
+ IN UINT64 Dest
+ )
+{
+ UINT16 Data;
+ mSmst->SmmIo.Mem.Read (
+ &mSmst->SmmIo,
+ SMM_IO_UINT16,
+ Dest,
+ 1,
+ &Data
+ );
+
+ return Data;
+}
+
+/**
+ Do a four bytes Memory write
+
+ @param[in] Dest Memory address to write
+ @param[in] Data Data to write
+
+**/
+VOID
+SmmMemWrite32 (
+ IN UINT64 Dest,
+ IN UINT32 Data
+ )
+{
+ mSmst->SmmIo.Mem.Write (
+ &mSmst->SmmIo,
+ SMM_IO_UINT32,
+ Dest,
+ 1,
+ &Data
+ );
+
+ return ;
+}
+
+/**
+ Do a four bytes Memory read
+
+ @param[in] Dest Memory address to read
+
+ @return Data read
+
+**/
+UINT32
+SmmMemRead32 (
+ IN UINT64 Dest
+ )
+{
+ UINT32 Data;
+ mSmst->SmmIo.Mem.Read (
+ &mSmst->SmmIo,
+ SMM_IO_UINT32,
+ Dest,
+ 1,
+ &Data
+ );
+
+ return Data;
+}
+
+/**
+ Do a four bytes Memory read, then AND with Data, then write back to the same address
+
+ @param[in] Dest Memory address to write
+ @param[in] Data Data to do AND
+
+**/
+VOID
+SmmMemAnd32 (
+ IN UINT64 Dest,
+ IN UINT32 Data
+ )
+{
+ UINT32 Data_And;
+ mSmst->SmmIo.Mem.Read (
+ &mSmst->SmmIo,
+ SMM_IO_UINT32,
+ Dest,
+ 1,
+ &Data_And
+ );
+ Data_And&=Data;
+ mSmst->SmmIo.Mem.Write (
+ &mSmst->SmmIo,
+ SMM_IO_UINT32,
+ Dest,
+ 1,
+ &Data_And
+ );
+
+ return ;
+}
diff --git a/BraswellPlatformPkg/Common/Library/SmmIo/SmmIoLib.inf b/BraswellPlatformPkg/Common/Library/SmmIo/SmmIoLib.inf new file mode 100644 index 0000000000..17b5aa5d49 --- /dev/null +++ b/BraswellPlatformPkg/Common/Library/SmmIo/SmmIoLib.inf @@ -0,0 +1,35 @@ +## @file
+# Component description file for SMM IO Library.
+#
+# Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.<BR>
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php.
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = SmmIoLib
+ FILE_GUID = A6A16CCB-91B0-42f4-B4F3-D16D7A8662E6
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = SmmIoLib
+
+[Sources]
+ SmmIo.c
+ SmmPciIo.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ BraswellPlatformPkg/BraswellPlatformPkg.dec
+
+[LibraryClasses]
+ PciLib
+ IoLib
+ BaseLib
diff --git a/BraswellPlatformPkg/Common/Library/SmmIo/SmmPciIo.c b/BraswellPlatformPkg/Common/Library/SmmIo/SmmPciIo.c new file mode 100644 index 0000000000..5af687e3b1 --- /dev/null +++ b/BraswellPlatformPkg/Common/Library/SmmIo/SmmPciIo.c @@ -0,0 +1,162 @@ +/** @file
+ SMM PCI config space I/O access utility implementation file, for Ia32
+
+ Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "Library/SmmIoLib.h"
+
+STATIC
+EFI_STATUS
+SmmSingleSegmentPciAccess (
+ IN EFI_SMM_CPU_IO2_PROTOCOL *CpuIo,
+ IN BOOLEAN IsWrite,
+ IN SMM_PCI_IO_WIDTH Width,
+ IN SMM_PCI_IO_ADDRESS *Address,
+ IN OUT VOID *Buffer
+ );
+
+/**
+ Read value from the specified PCI config space register
+
+ @param[in] Width The width (8, 16 or 32 bits) of accessed pci config space register
+ @param[in] Address The address of the accessed pci register (bus, dev, func, offset)
+ @param[in, out] Buffer The returned value
+
+ @retval EFI_SUCCESS All operations successfully
+ @retval EFI_INVALID_PARAMETER Width is not valid or dosn't match register address
+ @retval Other error code If any error occured when calling libiary functions
+
+**/
+EFI_STATUS
+SmmPciCfgRead (
+ IN SMM_PCI_IO_WIDTH Width,
+ IN SMM_PCI_IO_ADDRESS *Address,
+ IN OUT VOID *Buffer
+ )
+{
+ EFI_SMM_CPU_IO2_PROTOCOL *SmmCpuIo;
+
+ ASSERT (mSmst);
+
+ SmmCpuIo = &(mSmst->SmmIo);
+
+ return SmmSingleSegmentPciAccess (SmmCpuIo, FALSE, Width, Address, Buffer);
+}
+
+/**
+ Write value into the specified PCI config space register
+
+ @param[in] Width The width (8, 16 or 32 bits) of accessed pci config space register
+ @param[in] Address The address of the accessed pci register (bus, dev, func, offset)
+ @param[in, out] Buffer The returned value
+
+ @retval EFI_SUCCESS All operations successfully
+ @retval EFI_INVALID_PARAMETER Width is not valid or dosn't match register address
+ @retval Other error code If any error occured when calling libiary functions
+
+**/
+EFI_STATUS
+SmmPciCfgWrite (
+ IN SMM_PCI_IO_WIDTH Width,
+ IN SMM_PCI_IO_ADDRESS *Address,
+ IN OUT VOID *Buffer
+ )
+{
+ EFI_SMM_CPU_IO2_PROTOCOL *SmmCpuIo;
+
+ ASSERT (mSmst);
+
+ SmmCpuIo = &(mSmst->SmmIo);
+
+ return SmmSingleSegmentPciAccess (SmmCpuIo, TRUE, Width, Address, Buffer);
+}
+
+/**
+ Access a PCI config space address, including read and write
+
+ @param[in] CpuIo The cpu I/O accessing interface provided by EFI runtime sys table
+ @param[in] IsWrite Indicates whether this operation is a write access or read
+ @param[in] Width The width (8, 16 or 32 bits) of accessed pci config space register
+ @param[in] Address The address of the accessed pci register (bus, dev, func, offset)
+ @param[in, out] Buffer The returned value when this is a reading operation or the data
+ to be written when this is a writing one
+
+ @retval EFI_SUCCESS All operations successfully
+ @retval EFI_INVALID_PARAMETER Width is not valid or dosn't match register address
+ @retval Other error code If any error occured when calling libiary functions
+
+**/
+STATIC
+EFI_STATUS
+SmmSingleSegmentPciAccess (
+ IN EFI_SMM_CPU_IO2_PROTOCOL *CpuIo,
+ IN BOOLEAN IsWrite,
+ IN SMM_PCI_IO_WIDTH Width,
+ IN SMM_PCI_IO_ADDRESS *Address,
+ IN OUT VOID *Buffer
+ )
+{
+ EFI_STATUS Status;
+ PCI_CONFIG_ACCESS_CF8 PciCf8Data;
+ UINT64 PciDataReg;
+
+ //
+ // PCI Config access are all 32-bit alligned, but by accessing the
+ // CONFIG_DATA_REGISTER (0xcfc) with different widths more cycle types
+ // are possible on PCI.
+ //
+ // To read a byte of PCI config space you load 0xcf8 and
+ // read 0xcfc, 0xcfd, 0xcfe, 0xcff
+ //
+ // The validation of passed in arguments "Address" will be checked in the
+ // CPU IO functions, so we don't check them here
+ //
+
+ if (Width >= SmmPciWidthMaximum) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ PciCf8Data.Bits.Reg = Address->Register & 0xfc;
+ PciCf8Data.Bits.Func = Address->Function;
+ PciCf8Data.Bits.Dev = Address->Device;
+ PciCf8Data.Bits.Bus = Address->Bus;
+ PciCf8Data.Bits.Reserved = 0;
+ PciCf8Data.Bits.Enable = 1;
+
+ Status = CpuIo->Io.Write (CpuIo, SmmPciWidthUint32, 0xcf8, 1, &PciCf8Data);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ PciDataReg = 0xcfc + (Address->Register & 0x03);
+
+ if (IsWrite) {
+ //
+ // This is a Pci write operation, write data into (0xcfc + offset)
+ //
+ Status = CpuIo->Io.Write (CpuIo, Width, PciDataReg, 1, Buffer);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+ } else {
+ //
+ // This is a Pci Read operation, read returned data from (0xcfc + offset)
+ //
+ Status = CpuIo->Io.Read (CpuIo, Width, PciDataReg, 1, Buffer);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+ }
+
+ return EFI_SUCCESS;
+}
diff --git a/BraswellPlatformPkg/Common/Library/StallSmmLib/StallSmm.c b/BraswellPlatformPkg/Common/Library/StallSmmLib/StallSmm.c new file mode 100644 index 0000000000..4e90d5a07d --- /dev/null +++ b/BraswellPlatformPkg/Common/Library/StallSmmLib/StallSmm.c @@ -0,0 +1,85 @@ +/** @file
+ SMM I/O access utility implementation file, for Ia32
+
+ Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+//
+// Include files
+//
+#include "Library/StallSmmLib.h"
+#include "Pi/PiSmmCis.h"
+#include "PiDxe.h"
+#include <Library/IoLib.h>
+#include <Library/PcdLib.h>
+#include "PchAccess.h"
+
+/**
+ Delay for at least the request number of microseconds.
+ Timer used is ACPI time counter, which has 1us granularity.
+
+ @param[in] Microseconds Number of microseconds to delay.
+
+ @retval None
+
+**/
+VOID
+SmmStall (
+ IN UINTN Microseconds
+ )
+{
+ UINTN Ticks;
+ UINTN Counts;
+ UINTN CurrentTick;
+ UINTN OriginalTick;
+ UINTN RemainingTick;
+ UINT16 AcpiBaseAddr;
+
+ if (Microseconds == 0) {
+ return;
+ }
+
+ AcpiBaseAddr = PchLpcPciCfg16 (R_PCH_LPC_ACPI_BASE) & B_PCH_LPC_ACPI_BASE_BAR;
+
+ OriginalTick = IoRead32 (AcpiBaseAddr + R_PCH_ACPI_PM1_TMR);
+ CurrentTick = OriginalTick;
+
+ //
+ // The timer frequency is 3.579545 MHz, so 1 ms corresponds 3.58 clocks
+ //
+ Ticks = Microseconds * 358 / 100 + OriginalTick + 1;
+
+ //
+ // The loops needed by timer overflow
+ //
+ Counts = Ticks / V_PCH_ACPI_PM1_TMR_MAX_VAL;
+
+ //
+ // Remaining clocks within one loop
+ //
+ RemainingTick = Ticks % V_PCH_ACPI_PM1_TMR_MAX_VAL;
+
+ //
+ // not intend to use TMROF_STS bit of register PM1_STS, because this adds extra
+ // one I/O operation, and maybe generate SMI
+ //
+ while ((Counts != 0) || (RemainingTick > CurrentTick)) {
+ CurrentTick = IoRead32 (AcpiBaseAddr + R_PCH_ACPI_PM1_TMR);
+ //
+ // Check if timer overflow
+ //
+ if (CurrentTick < OriginalTick) {
+ Counts--;
+ }
+ OriginalTick = CurrentTick;
+ }
+}
diff --git a/BraswellPlatformPkg/Common/Library/StallSmmLib/StallSmmLib.inf b/BraswellPlatformPkg/Common/Library/StallSmmLib/StallSmmLib.inf new file mode 100644 index 0000000000..700883f6cd --- /dev/null +++ b/BraswellPlatformPkg/Common/Library/StallSmmLib/StallSmmLib.inf @@ -0,0 +1,48 @@ +## @file
+# Component description file for SmmStall library
+#
+# Time stall in SMM mode
+#
+# Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.<BR>
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php.
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = StallSmmLib
+ FILE_GUID = A6A16CCB-91B0-42f4-B4F3-D16D7A8662E6
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = StallSmmLib
+
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = IA32 X64 IPF EBC
+#
+
+[Sources]
+ StallSmm.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ BraswellPlatformPkg/BraswellPlatformPkg.dec
+ ChvRefCodePkg/ChvRefCodePkg.dec
+
+[LibraryClasses]
+ PcdLib
+ IoLib
+ BaseLib
+
+[Pcd]
+ gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## CONSUMES
+
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