diff options
| author | Guo Mang <mang.guo@intel.com> | 2016-12-22 15:57:14 +0800 |
|---|---|---|
| committer | Guo Mang <mang.guo@intel.com> | 2016-12-26 19:14:41 +0800 |
| commit | 1760cf81e4b1847c6823ea3514a78dd120e19b6e (patch) | |
| tree | 64a874b14050fe24d3bbc1bc13cd293abf8ae018 /Core/MdePkg/Library/BaseLib/Arm/EnableInterrupts.S | |
| parent | 7f05fa00f73038b425002566d3afe6c3ade2ccdb (diff) | |
| download | edk2-platforms-1760cf81e4b1847c6823ea3514a78dd120e19b6e.tar.xz | |
MdePkg: Move to new location
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Guo Mang <mang.guo@intel.com>
Diffstat (limited to 'Core/MdePkg/Library/BaseLib/Arm/EnableInterrupts.S')
| -rw-r--r-- | Core/MdePkg/Library/BaseLib/Arm/EnableInterrupts.S | 36 |
1 files changed, 36 insertions, 0 deletions
diff --git a/Core/MdePkg/Library/BaseLib/Arm/EnableInterrupts.S b/Core/MdePkg/Library/BaseLib/Arm/EnableInterrupts.S new file mode 100644 index 0000000000..9f3a28af94 --- /dev/null +++ b/Core/MdePkg/Library/BaseLib/Arm/EnableInterrupts.S @@ -0,0 +1,36 @@ +#------------------------------------------------------------------------------
+#
+# EnableInterrupts() for ARM
+#
+# Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
+# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php.
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#------------------------------------------------------------------------------
+
+.text
+.p2align 2
+GCC_ASM_EXPORT(EnableInterrupts)
+
+
+#/**
+# Enables CPU interrupts.
+#
+#**/
+#VOID
+#EFIAPI
+#EnableInterrupts (
+# VOID
+# );
+#
+ASM_PFX(EnableInterrupts):
+ mrs R0,CPSR
+ bic R0,R0,#0x80 @Enable IRQ interrupts
+ msr CPSR_c,R0
+ bx LR
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