diff options
| author | Guo Mang <mang.guo@intel.com> | 2016-12-22 15:57:14 +0800 |
|---|---|---|
| committer | Guo Mang <mang.guo@intel.com> | 2016-12-26 19:14:41 +0800 |
| commit | 1760cf81e4b1847c6823ea3514a78dd120e19b6e (patch) | |
| tree | 64a874b14050fe24d3bbc1bc13cd293abf8ae018 /Core/MdePkg/Library/BaseLib/Ia32/FlushCacheLine.c | |
| parent | 7f05fa00f73038b425002566d3afe6c3ade2ccdb (diff) | |
| download | edk2-platforms-1760cf81e4b1847c6823ea3514a78dd120e19b6e.tar.xz | |
MdePkg: Move to new location
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Guo Mang <mang.guo@intel.com>
Diffstat (limited to 'Core/MdePkg/Library/BaseLib/Ia32/FlushCacheLine.c')
| -rw-r--r-- | Core/MdePkg/Library/BaseLib/Ia32/FlushCacheLine.c | 58 |
1 files changed, 58 insertions, 0 deletions
diff --git a/Core/MdePkg/Library/BaseLib/Ia32/FlushCacheLine.c b/Core/MdePkg/Library/BaseLib/Ia32/FlushCacheLine.c new file mode 100644 index 0000000000..7ac4af353f --- /dev/null +++ b/Core/MdePkg/Library/BaseLib/Ia32/FlushCacheLine.c @@ -0,0 +1,58 @@ +/** @file
+ AsmFlushCacheLine function
+
+ Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+
+
+
+/**
+ Flushes a cache line from all the instruction and data caches within the
+ coherency domain of the CPU.
+
+ Flushed the cache line specified by LinearAddress, and returns LinearAddress.
+ This function is only available on IA-32 and x64.
+
+ @param LinearAddress The address of the cache line to flush. If the CPU is
+ in a physical addressing mode, then LinearAddress is a
+ physical address. If the CPU is in a virtual
+ addressing mode, then LinearAddress is a virtual
+ address.
+
+ @return LinearAddress
+**/
+VOID *
+EFIAPI
+AsmFlushCacheLine (
+ IN VOID *LinearAddress
+ )
+{
+ //
+ // If the CPU does not support CLFLUSH instruction,
+ // then promote flush range to flush entire cache.
+ //
+ _asm {
+ mov eax, 1
+ cpuid
+ test edx, BIT19
+ jz NoClflush
+ mov eax, dword ptr [LinearAddress]
+ clflush [eax]
+ jmp Done
+NoClflush:
+ wbinvd
+Done:
+ }
+
+ return LinearAddress;
+}
+
|