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authorZhang, Chao B <chao.b.zhang@intel.com>2016-05-11 08:59:40 +0800
committerZhang, Chao B <chao.b.zhang@intel.com>2016-05-11 08:59:40 +0800
commit070827be5a5727c736acf5d645722be073640952 (patch)
tree9673cee0e32b49da9db60d43dd68f5cc2ad5c22b /CorebootModulePkg/Include
parentf1005559ec0ab65d42526313eb819f60c120eab8 (diff)
parent49effaf26ec952905bc7710587c6a58437864cdf (diff)
downloadedk2-platforms-070827be5a5727c736acf5d645722be073640952.tar.xz
Merge branch 'master' of github.com:tianocore/edk2
Diffstat (limited to 'CorebootModulePkg/Include')
-rw-r--r--CorebootModulePkg/Include/Coreboot.h17
-rw-r--r--CorebootModulePkg/Include/Library/CbParseLib.h26
2 files changed, 32 insertions, 11 deletions
diff --git a/CorebootModulePkg/Include/Coreboot.h b/CorebootModulePkg/Include/Coreboot.h
index f2f18be2cc..784e0b128a 100644
--- a/CorebootModulePkg/Include/Coreboot.h
+++ b/CorebootModulePkg/Include/Coreboot.h
@@ -80,7 +80,7 @@ struct imd_root {
UINT32 max_entries;
UINT32 num_entries;
UINT32 flags;
- UINT32 entry_align;
+ UINT32 entry_align;
UINT32 max_offset;
struct imd_entry entries[0];
};
@@ -165,6 +165,21 @@ struct cb_serial {
UINT32 type;
UINT32 baseaddr;
UINT32 baud;
+ UINT32 regwidth;
+
+ // Crystal or input frequency to the chip containing the UART.
+ // Provide the board specific details to allow the payload to
+ // initialize the chip containing the UART and make independent
+ // decisions as to which dividers to select and their values
+ // to eventually arrive at the desired console baud-rate.
+ UINT32 input_hertz;
+
+ // UART PCI address: bus, device, function
+ // 1 << 31 - Valid bit, PCI UART in use
+ // Bus << 20
+ // Device << 15
+ // Function << 12
+ UINT32 uart_pci_addr;
};
#define CB_TAG_CONSOLE 0x00010
diff --git a/CorebootModulePkg/Include/Library/CbParseLib.h b/CorebootModulePkg/Include/Library/CbParseLib.h
index 170375b365..a023246d71 100644
--- a/CorebootModulePkg/Include/Library/CbParseLib.h
+++ b/CorebootModulePkg/Include/Library/CbParseLib.h
@@ -30,7 +30,7 @@ CbParseMemoryInfo (
IN UINT64* pLowMemorySize,
IN UINT64* pHighMemorySize
);
-
+
/**
Acquire the coreboot memory table with the given table id
@@ -45,11 +45,11 @@ CbParseMemoryInfo (
**/
RETURN_STATUS
CbParseCbMemTable (
- IN UINT32 TableId,
+ IN UINT32 TableId,
IN VOID** pMemTable,
IN UINT32* pMemTableSize
);
-
+
/**
Acquire the acpi table from coreboot
@@ -66,7 +66,7 @@ CbParseAcpiTable (
IN VOID** pMemTable,
IN UINT32* pMemTableSize
);
-
+
/**
Acquire the smbios table from coreboot
@@ -83,7 +83,7 @@ CbParseSmbiosTable (
IN VOID** pMemTable,
IN UINT32* pMemTableSize
);
-
+
/**
Find the required fadt information
@@ -107,13 +107,16 @@ CbParseFadtInfo (
IN UINTN* pPmEvtReg,
IN UINTN* pPmGpeEnReg
);
-
+
/**
Find the serial port information
@param pRegBase Pointer to the base address of serial port registers
@param pRegAccessType Pointer to the access type of serial port registers
+ @param pRegWidth Pointer to the register width in bytes
@param pBaudrate Pointer to the serial port baudrate
+ @param pInputHertz Pointer to the input clock frequency
+ @param pUartPciAddr Pointer to the UART PCI bus, dev and func address
@retval RETURN_SUCCESS Successfully find the serial port information.
@retval RETURN_NOT_FOUND Failed to find the serial port information .
@@ -121,9 +124,12 @@ CbParseFadtInfo (
**/
RETURN_STATUS
CbParseSerialInfo (
- IN UINT32* pRegBase,
- IN UINT32* pRegAccessType,
- IN UINT32* pBaudrate
+ OUT UINT32 *pRegBase,
+ OUT UINT32 *pRegAccessType,
+ OUT UINT32 *pRegWidth,
+ OUT UINT32 *pBaudrate,
+ OUT UINT32 *pInputHertz,
+ OUT UINT32 *pUartPciAddr
);
/**
@@ -141,7 +147,7 @@ CbParseGetCbHeader (
IN UINTN Level,
IN VOID** HeaderPtr
);
-
+
/**
Find the video frame buffer information