diff options
| author | qwang12 <qwang12@6f19259b-4bc3-4df7-8a09-765794883524> | 2007-06-28 07:00:39 +0000 |
|---|---|---|
| committer | qwang12 <qwang12@6f19259b-4bc3-4df7-8a09-765794883524> | 2007-06-28 07:00:39 +0000 |
| commit | 3eb9473ea9a949badfe06ae61d2d3fcfa53651c7 (patch) | |
| tree | e9d8c368dbb1e58794b2c00acefe4bbad270f8c4 /EdkCompatibilityPkg/Foundation/Include/IndustryStandard | |
| parent | 30d4a0c7ec19938196b1308006b990e0945150da (diff) | |
| download | edk2-platforms-3eb9473ea9a949badfe06ae61d2d3fcfa53651c7.tar.xz | |
Add in the 1st version of ECP.
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@2832 6f19259b-4bc3-4df7-8a09-765794883524
Diffstat (limited to 'EdkCompatibilityPkg/Foundation/Include/IndustryStandard')
22 files changed, 6603 insertions, 0 deletions
diff --git a/EdkCompatibilityPkg/Foundation/Include/IndustryStandard/Acpi.h b/EdkCompatibilityPkg/Foundation/Include/IndustryStandard/Acpi.h new file mode 100644 index 0000000000..6a7246f72e --- /dev/null +++ b/EdkCompatibilityPkg/Foundation/Include/IndustryStandard/Acpi.h @@ -0,0 +1,31 @@ +/*++
+
+Copyright (c) 2004 - 2007, Intel Corporation
+All rights reserved. This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution. The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+Module Name:
+
+ Acpi.h
+
+Abstract:
+
+ This file contains some basic ACPI definitions that are consumed by drivers
+ that do not care about ACPI versions.
+
+--*/
+
+#ifndef _ACPI_H_
+#define _ACPI_H_
+
+#include "AcpiCommon.h"
+#include "Acpi1_0.h"
+#include "Acpi2_0.h"
+#include "Acpi3_0.h"
+
+#endif
diff --git a/EdkCompatibilityPkg/Foundation/Include/IndustryStandard/Acpi1_0.h b/EdkCompatibilityPkg/Foundation/Include/IndustryStandard/Acpi1_0.h new file mode 100644 index 0000000000..84c4147cc6 --- /dev/null +++ b/EdkCompatibilityPkg/Foundation/Include/IndustryStandard/Acpi1_0.h @@ -0,0 +1,299 @@ +/*++
+
+Copyright (c) 2007, Intel Corporation
+All rights reserved. This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution. The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+Module Name:
+
+ Acpi1_0.h
+
+Abstract:
+
+ ACPI 1.0b definitions from the ACPI Specification, revision 1.0b
+
+--*/
+
+#ifndef _ACPI_1_0_H_
+#define _ACPI_1_0_H_
+
+//
+// Statements that include other files
+//
+#include "AcpiCommon.h"
+
+//
+// Ensure proper structure formats
+//
+#pragma pack(1)
+//
+// ACPI 1.0b table structures
+//
+//
+// Root System Description Pointer Structure
+//
+typedef struct {
+ UINT64 Signature;
+ UINT8 Checksum;
+ UINT8 OemId[6];
+ UINT8 Reserved;
+ UINT32 RsdtAddress;
+} EFI_ACPI_1_0_ROOT_SYSTEM_DESCRIPTION_POINTER;
+
+//
+// Root System Description Table
+// No definition needed as it is a common description table header followed by a
+// variable number of UINT32 table pointers.
+//
+//
+// RSDT Revision (as defined in ACPI 1.0b spec.)
+//
+#define EFI_ACPI_1_0_ROOT_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01
+
+//
+// Fixed ACPI Description Table Structure (FADT)
+//
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 FirmwareCtrl;
+ UINT32 Dsdt;
+ UINT8 IntModel;
+ UINT8 Reserved1;
+ UINT16 SciInt;
+ UINT32 SmiCmd;
+ UINT8 AcpiEnable;
+ UINT8 AcpiDisable;
+ UINT8 S4BiosReq;
+ UINT8 Reserved2;
+ UINT32 Pm1aEvtBlk;
+ UINT32 Pm1bEvtBlk;
+ UINT32 Pm1aCntBlk;
+ UINT32 Pm1bCntBlk;
+ UINT32 Pm2CntBlk;
+ UINT32 PmTmrBlk;
+ UINT32 Gpe0Blk;
+ UINT32 Gpe1Blk;
+ UINT8 Pm1EvtLen;
+ UINT8 Pm1CntLen;
+ UINT8 Pm2CntLen;
+ UINT8 PmTmLen;
+ UINT8 Gpe0BlkLen;
+ UINT8 Gpe1BlkLen;
+ UINT8 Gpe1Base;
+ UINT8 Reserved3;
+ UINT16 PLvl2Lat;
+ UINT16 PLvl3Lat;
+ UINT16 FlushSize;
+ UINT16 FlushStride;
+ UINT8 DutyOffset;
+ UINT8 DutyWidth;
+ UINT8 DayAlrm;
+ UINT8 MonAlrm;
+ UINT8 Century;
+ UINT8 Reserved4;
+ UINT8 Reserved5;
+ UINT8 Reserved6;
+ UINT32 Flags;
+} EFI_ACPI_1_0_FIXED_ACPI_DESCRIPTION_TABLE;
+
+//
+// FADT Version (as defined in ACPI 1.0b spec.)
+//
+#define EFI_ACPI_1_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION 0x01
+
+//
+// Fixed ACPI Description Table Fixed Feature Flags
+// All other bits are reserved and must be set to 0.
+//
+#define EFI_ACPI_1_0_WBINVD (1 << 0)
+#define EFI_ACPI_1_0_WBINVD_FLUSH (1 << 1)
+#define EFI_ACPI_1_0_PROC_C1 (1 << 2)
+#define EFI_ACPI_1_0_P_LVL2_UP (1 << 3)
+#define EFI_ACPI_1_0_PWR_BUTTON (1 << 4)
+#define EFI_ACPI_1_0_SLP_BUTTON (1 << 5)
+#define EFI_ACPI_1_0_FIX_RTC (1 << 6)
+#define EFI_ACPI_1_0_RTC_S4 (1 << 7)
+#define EFI_ACPI_1_0_TMR_VAL_EXT (1 << 8)
+#define EFI_ACPI_1_0_DCK_CAP (1 << 9)
+
+//
+// Firmware ACPI Control Structure
+//
+typedef struct {
+ UINT32 Signature;
+ UINT32 Length;
+ UINT32 HardwareSignature;
+ UINT32 FirmwareWakingVector;
+ UINT32 GlobalLock;
+ UINT32 Flags;
+ UINT8 Reserved[40];
+} EFI_ACPI_1_0_FIRMWARE_ACPI_CONTROL_STRUCTURE;
+
+//
+// Firmware Control Structure Feature Flags
+// All other bits are reserved and must be set to 0.
+//
+#define EFI_ACPI_1_0_S4BIOS_F (1 << 0)
+
+//
+// Multiple APIC Description Table header definition. The rest of the table
+// must be defined in a platform specific manner.
+//
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 LocalApicAddress;
+ UINT32 Flags;
+} EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER;
+
+//
+// MADT Revision (as defined in ACPI 1.0b spec.)
+//
+#define EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION 0x01
+
+//
+// Multiple APIC Flags
+// All other bits are reserved and must be set to 0.
+//
+#define EFI_ACPI_1_0_PCAT_COMPAT (1 << 0)
+
+//
+// Multiple APIC Description Table APIC structure types
+// All other values between 0x09 an 0xFF are reserved and
+// will be ignored by OSPM.
+//
+#define EFI_ACPI_1_0_PROCESSOR_LOCAL_APIC 0x00
+#define EFI_ACPI_1_0_IO_APIC 0x01
+#define EFI_ACPI_1_0_INTERRUPT_SOURCE_OVERRIDE 0x02
+#define EFI_ACPI_1_0_NON_MASKABLE_INTERRUPT_SOURCE 0x03
+#define EFI_ACPI_1_0_LOCAL_APIC_NMI 0x04
+
+//
+// APIC Structure Definitions
+//
+//
+// Processor Local APIC Structure Definition
+//
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 AcpiProcessorId;
+ UINT8 ApicId;
+ UINT32 Flags;
+} EFI_ACPI_1_0_PROCESSOR_LOCAL_APIC_STRUCTURE;
+
+//
+// Local APIC Flags. All other bits are reserved and must be 0.
+//
+#define EFI_ACPI_1_0_LOCAL_APIC_ENABLED (1 << 0)
+
+//
+// IO APIC Structure
+//
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 IoApicId;
+ UINT8 Reserved;
+ UINT32 IoApicAddress;
+ UINT32 SystemVectorBase;
+} EFI_ACPI_1_0_IO_APIC_STRUCTURE;
+
+//
+// Interrupt Source Override Structure
+//
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 Bus;
+ UINT8 Source;
+ UINT32 GlobalSystemInterruptVector;
+ UINT16 Flags;
+} EFI_ACPI_1_0_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE;
+
+//
+// Non-Maskable Interrupt Source Structure
+//
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Flags;
+ UINT32 GlobalSystemInterruptVector;
+} EFI_ACPI_1_0_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE;
+
+//
+// Local APIC NMI Structure
+//
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 AcpiProcessorId;
+ UINT16 Flags;
+ UINT8 LocalApicInti;
+} EFI_ACPI_1_0_LOCAL_APIC_NMI_STRUCTURE;
+
+//
+// Smart Battery Description Table (SBST)
+//
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 WarningEnergyLevel;
+ UINT32 LowEnergyLevel;
+ UINT32 CriticalEnergyLevel;
+} EFI_ACPI_1_0_SMART_BATTERY_DESCRIPTION_TABLE;
+
+//
+// Known table signatures
+//
+//
+// "RSD PTR " Root System Description Pointer
+//
+#define EFI_ACPI_1_0_ROOT_SYSTEM_DESCRIPTION_POINTER_SIGNATURE 0x2052545020445352
+
+//
+// "APIC" Multiple APIC Description Table
+//
+#define EFI_ACPI_1_0_APIC_SIGNATURE 0x43495041
+
+//
+// "DSDT" Differentiated System Description Table
+//
+#define EFI_ACPI_1_0_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE 0x54445344
+
+//
+// "FACS" Firmware ACPI Control Structure
+//
+#define EFI_ACPI_1_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE 0x53434146
+
+//
+// "FACP" Fixed ACPI Description Table
+//
+#define EFI_ACPI_1_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE 0x50434146
+
+//
+// "PSDT" Persistent System Description Table
+//
+#define EFI_ACPI_1_0_PERSISTENT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE 0x54445350
+
+//
+// "RSDT" Root System Description Table
+//
+#define EFI_ACPI_1_0_ROOT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE 0x54445352
+
+//
+// "SBST" Smart Battery Specification Table
+//
+#define EFI_ACPI_1_0_SMART_BATTERY_SPECIFICATION_TABLE_SIGNATURE 0x54534253
+
+//
+// "SSDT" Secondary System Description Table
+//
+#define EFI_ACPI_1_0_SECONDARY_SYSTEM_DESCRIPTION_TABLE_SIGNATURE 0x54445353
+
+#pragma pack()
+
+#endif
diff --git a/EdkCompatibilityPkg/Foundation/Include/IndustryStandard/Acpi2_0.h b/EdkCompatibilityPkg/Foundation/Include/IndustryStandard/Acpi2_0.h new file mode 100644 index 0000000000..60c2e40e5c --- /dev/null +++ b/EdkCompatibilityPkg/Foundation/Include/IndustryStandard/Acpi2_0.h @@ -0,0 +1,513 @@ +/*++
+
+Copyright (c) 2007, Intel Corporation
+All rights reserved. This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution. The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+Module Name:
+
+ Acpi2_0.h
+
+Abstract:
+
+ ACPI 2.0 definitions from the ACPI Specification, revision 2.0
+
+--*/
+
+#ifndef _ACPI_2_0_H_
+#define _ACPI_2_0_H_
+
+//
+// Statements that include other files
+//
+#include "AcpiCommon.h"
+
+//
+// Ensure proper structure formats
+//
+#pragma pack(1)
+//
+// ACPI Specification Revision
+//
+#define EFI_ACPI_2_0_REVISION 0x02
+
+//
+// ACPI 2.0 Generic Address Space definition
+//
+typedef struct {
+ UINT8 AddressSpaceId;
+ UINT8 RegisterBitWidth;
+ UINT8 RegisterBitOffset;
+ UINT8 Reserved;
+ UINT64 Address;
+} EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE;
+
+//
+// Generic Address Space Address IDs
+//
+#define EFI_ACPI_2_0_SYSTEM_MEMORY 0
+#define EFI_ACPI_2_0_SYSTEM_IO 1
+#define EFI_ACPI_2_0_PCI_CONFIGURATION_SPACE 2
+#define EFI_ACPI_2_0_EMBEDDED_CONTROLLER 3
+#define EFI_ACPI_2_0_SMBUS 4
+#define EFI_ACPI_2_0_FUNCTIONAL_FIXED_HARDWARE 0x7F
+
+//
+// ACPI 2.0 table structures
+//
+//
+// Root System Description Pointer Structure
+//
+typedef struct {
+ UINT64 Signature;
+ UINT8 Checksum;
+ UINT8 OemId[6];
+ UINT8 Revision;
+ UINT32 RsdtAddress;
+ UINT32 Length;
+ UINT64 XsdtAddress;
+ UINT8 ExtendedChecksum;
+ UINT8 Reserved[3];
+} EFI_ACPI_2_0_ROOT_SYSTEM_DESCRIPTION_POINTER;
+
+//
+// RSD_PTR Revision (as defined in ACPI 2.0 spec.)
+//
+#define EFI_ACPI_2_0_ROOT_SYSTEM_DESCRIPTION_POINTER_REVISION 0x02
+
+//
+// Common table header, this prefaces all ACPI tables, including FACS, but
+// excluding the RSD PTR structure
+//
+typedef struct {
+ UINT32 Signature;
+ UINT32 Length;
+} EFI_ACPI_2_0_COMMON_HEADER;
+
+//
+// Root System Description Table
+// No definition needed as it is a common description table header followed by a
+// variable number of UINT32 table pointers.
+//
+//
+// RSDT Revision (as defined in ACPI 2.0 spec.)
+//
+#define EFI_ACPI_2_0_ROOT_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01
+
+//
+// Extended System Description Table
+// No definition needed as it is a common description table header followed by a
+// variable number of UINT64 table pointers.
+//
+//
+// XSDT Revision (as defined in ACPI 2.0 spec.)
+//
+#define EFI_ACPI_2_0_EXTENDED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01
+
+//
+// Fixed ACPI Description Table Structure (FADT)
+//
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 FirmwareCtrl;
+ UINT32 Dsdt;
+ UINT8 Reserved0;
+ UINT8 PreferredPmProfile;
+ UINT16 SciInt;
+ UINT32 SmiCmd;
+ UINT8 AcpiEnable;
+ UINT8 AcpiDisable;
+ UINT8 S4BiosReq;
+ UINT8 PstateCnt;
+ UINT32 Pm1aEvtBlk;
+ UINT32 Pm1bEvtBlk;
+ UINT32 Pm1aCntBlk;
+ UINT32 Pm1bCntBlk;
+ UINT32 Pm2CntBlk;
+ UINT32 PmTmrBlk;
+ UINT32 Gpe0Blk;
+ UINT32 Gpe1Blk;
+ UINT8 Pm1EvtLen;
+ UINT8 Pm1CntLen;
+ UINT8 Pm2CntLen;
+ UINT8 PmTmrLen;
+ UINT8 Gpe0BlkLen;
+ UINT8 Gpe1BlkLen;
+ UINT8 Gpe1Base;
+ UINT8 CstCnt;
+ UINT16 PLvl2Lat;
+ UINT16 PLvl3Lat;
+ UINT16 FlushSize;
+ UINT16 FlushStride;
+ UINT8 DutyOffset;
+ UINT8 DutyWidth;
+ UINT8 DayAlrm;
+ UINT8 MonAlrm;
+ UINT8 Century;
+ UINT16 IaPcBootArch;
+ UINT8 Reserved1;
+ UINT32 Flags;
+ EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE ResetReg;
+ UINT8 ResetValue;
+ UINT8 Reserved2[3];
+ UINT64 XFirmwareCtrl;
+ UINT64 XDsdt;
+ EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE XPm1aEvtBlk;
+ EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE XPm1bEvtBlk;
+ EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE XPm1aCntBlk;
+ EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE XPm1bCntBlk;
+ EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE XPm2CntBlk;
+ EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE XPmTmrBlk;
+ EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE XGpe0Blk;
+ EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE XGpe1Blk;
+} EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE;
+
+//
+// FADT Version (as defined in ACPI 2.0 spec.)
+//
+#define EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION 0x03
+
+//
+// Fixed ACPI Description Table Boot Architecture Flags
+// All other bits are reserved and must be set to 0.
+//
+#define EFI_ACPI_2_0_LEGACY_DEVICES (1 << 0)
+#define EFI_ACPI_2_0_8042 (1 << 1)
+
+//
+// Fixed ACPI Description Table Fixed Feature Flags
+// All other bits are reserved and must be set to 0.
+//
+#define EFI_ACPI_2_0_WBINVD (1 << 0)
+#define EFI_ACPI_2_0_WBINVD_FLUSH (1 << 1)
+#define EFI_ACPI_2_0_PROC_C1 (1 << 2)
+#define EFI_ACPI_2_0_P_LVL2_UP (1 << 3)
+#define EFI_ACPI_2_0_PWR_BUTTON (1 << 4)
+#define EFI_ACPI_2_0_SLP_BUTTON (1 << 5)
+#define EFI_ACPI_2_0_FIX_RTC (1 << 6)
+#define EFI_ACPI_2_0_RTC_S4 (1 << 7)
+#define EFI_ACPI_2_0_TMR_VAL_EXT (1 << 8)
+#define EFI_ACPI_2_0_DCK_CAP (1 << 9)
+#define EFI_ACPI_2_0_RESET_REG_SUP (1 << 10)
+#define EFI_ACPI_2_0_SEALED_CASE (1 << 11)
+#define EFI_ACPI_2_0_HEADLESS (1 << 12)
+#define EFI_ACPI_2_0_CPU_SW_SLP (1 << 13)
+
+//
+// Firmware ACPI Control Structure
+//
+typedef struct {
+ UINT32 Signature;
+ UINT32 Length;
+ UINT32 HardwareSignature;
+ UINT32 FirmwareWakingVector;
+ UINT32 GlobalLock;
+ UINT32 Flags;
+ UINT64 XFirmwareWakingVector;
+ UINT8 Version;
+ UINT8 Reserved[31];
+} EFI_ACPI_2_0_FIRMWARE_ACPI_CONTROL_STRUCTURE;
+
+//
+// FACS Version (as defined in ACPI 2.0 spec.)
+//
+#define EFI_ACPI_2_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_VERSION 0x01
+
+//
+// Firmware Control Structure Feature Flags
+// All other bits are reserved and must be set to 0.
+//
+#define EFI_ACPI_2_0_S4BIOS_F (1 << 0)
+
+//
+// Multiple APIC Description Table header definition. The rest of the table
+// must be defined in a platform specific manner.
+//
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 LocalApicAddress;
+ UINT32 Flags;
+} EFI_ACPI_2_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER;
+
+//
+// MADT Revision (as defined in ACPI 2.0 spec.)
+//
+#define EFI_ACPI_2_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION 0x01
+
+//
+// Multiple APIC Flags
+// All other bits are reserved and must be set to 0.
+//
+#define EFI_ACPI_2_0_PCAT_COMPAT (1 << 0)
+
+//
+// Multiple APIC Description Table APIC structure types
+// All other values between 0x09 an 0xFF are reserved and
+// will be ignored by OSPM.
+//
+#define EFI_ACPI_2_0_PROCESSOR_LOCAL_APIC 0x00
+#define EFI_ACPI_2_0_IO_APIC 0x01
+#define EFI_ACPI_2_0_INTERRUPT_SOURCE_OVERRIDE 0x02
+#define EFI_ACPI_2_0_NON_MASKABLE_INTERRUPT_SOURCE 0x03
+#define EFI_ACPI_2_0_LOCAL_APIC_NMI 0x04
+#define EFI_ACPI_2_0_LOCAL_APIC_ADDRESS_OVERRIDE 0x05
+#define EFI_ACPI_2_0_IO_SAPIC 0x06
+#define EFI_ACPI_2_0_PROCESSOR_LOCAL_SAPIC 0x07
+#define EFI_ACPI_2_0_PLATFORM_INTERRUPT_SOURCES 0x08
+
+//
+// APIC Structure Definitions
+//
+//
+// Processor Local APIC Structure Definition
+//
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 AcpiProcessorId;
+ UINT8 ApicId;
+ UINT32 Flags;
+} EFI_ACPI_2_0_PROCESSOR_LOCAL_APIC_STRUCTURE;
+
+//
+// Local APIC Flags. All other bits are reserved and must be 0.
+//
+#define EFI_ACPI_2_0_LOCAL_APIC_ENABLED (1 << 0)
+
+//
+// IO APIC Structure
+//
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 IoApicId;
+ UINT8 Reserved;
+ UINT32 IoApicAddress;
+ UINT32 GlobalSystemInterruptBase;
+} EFI_ACPI_2_0_IO_APIC_STRUCTURE;
+
+//
+// Interrupt Source Override Structure
+//
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 Bus;
+ UINT8 Source;
+ UINT32 GlobalSystemInterrupt;
+ UINT16 Flags;
+} EFI_ACPI_2_0_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE;
+
+//
+// Non-Maskable Interrupt Source Structure
+//
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Flags;
+ UINT32 GlobalSystemInterrupt;
+} EFI_ACPI_2_0_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE;
+
+//
+// Local APIC NMI Structure
+//
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 AcpiProcessorId;
+ UINT16 Flags;
+ UINT8 LocalApicLint;
+} EFI_ACPI_2_0_LOCAL_APIC_NMI_STRUCTURE;
+
+//
+// Local APIC Address Override Structure
+//
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Reserved;
+ UINT64 LocalApicAddress;
+} EFI_ACPI_2_0_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE;
+
+//
+// IO SAPIC Structure
+//
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 IoApicId;
+ UINT8 Reserved;
+ UINT32 GlobalSystemInterruptBase;
+ UINT64 IoSapicAddress;
+} EFI_ACPI_2_0_IO_SAPIC_STRUCTURE;
+
+//
+// Local SAPIC Structure
+//
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 AcpiProcessorId;
+ UINT8 LocalSapicId;
+ UINT8 LocalSapicEid;
+ UINT8 Reserved[3];
+ UINT32 Flags;
+} EFI_ACPI_2_0_PROCESSOR_LOCAL_SAPIC_STRUCTURE;
+
+//
+// Platform Interrupt Sources Structure
+//
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Flags;
+ UINT8 InterruptType;
+ UINT8 ProcessorId;
+ UINT8 ProcessorEid;
+ UINT8 IoSapicVector;
+ UINT32 GlobalSystemInterrupt;
+ UINT32 Reserved;
+} EFI_ACPI_2_0_PLATFORM_INTERRUPT_SOURCES_STRUCTURE;
+
+//
+// Smart Battery Description Table (SBST)
+//
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 WarningEnergyLevel;
+ UINT32 LowEnergyLevel;
+ UINT32 CriticalEnergyLevel;
+} EFI_ACPI_2_0_SMART_BATTERY_DESCRIPTION_TABLE;
+
+//
+// SBST Version (as defined in ACPI 2.0 spec.)
+//
+#define EFI_ACPI_2_0_SMART_BATTERY_DESCRIPTION_TABLE_REVISION 0x01
+
+//
+// Embedded Controller Boot Resources Table (ECDT)
+// The table is followed by a null terminated ASCII string that contains
+// a fully qualified reference to the name space object.
+//
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE EcControl;
+ EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE EcData;
+ UINT32 Uid;
+ UINT8 GpeBit;
+} EFI_ACPI_2_0_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE;
+
+//
+// ECDT Version (as defined in ACPI 2.0 spec.)
+//
+#define EFI_ACPI_2_0_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE_REVISION 0x01
+
+//
+// Known table signatures
+//
+//
+// "RSD PTR " Root System Description Pointer
+//
+#define EFI_ACPI_2_0_ROOT_SYSTEM_DESCRIPTION_POINTER_SIGNATURE 0x2052545020445352
+
+//
+// "SPIC" Multiple SAPIC Description Table
+//
+// BUGBUG: Don't know where this came from except SR870BN4 uses it.
+// #define EFI_ACPI_2_0_MULTIPLE_SAPIC_DESCRIPTION_TABLE_SIGNATURE 0x43495053
+//
+#define EFI_ACPI_2_0_MULTIPLE_SAPIC_DESCRIPTION_TABLE_SIGNATURE 0x43495041
+
+//
+// "BOOT" MS Simple Boot Spec
+//
+#define EFI_ACPI_2_0_SIMPLE_BOOT_FLAG_TABLE_SIGNATURE 0x544F4F42
+
+//
+// "DBGP" MS Bebug Port Spec
+//
+#define EFI_ACPI_2_0_DEBUG_PORT_TABLE_SIGNATURE 0x50474244
+
+//
+// "DSDT" Differentiated System Description Table
+//
+#define EFI_ACPI_2_0_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE 0x54445344
+
+//
+// "ECDT" Embedded Controller Boot Resources Table
+//
+#define EFI_ACPI_2_0_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE_SIGNATURE 0x54444345
+
+//
+// "ETDT" Event Timer Description Table
+//
+#define EFI_ACPI_2_0_EVENT_TIMER_DESCRIPTION_TABLE_SIGNATURE 0x54445445
+
+//
+// "FACS" Firmware ACPI Control Structure
+//
+#define EFI_ACPI_2_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE 0x53434146
+
+//
+// "FACP" Fixed ACPI Description Table
+//
+#define EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE 0x50434146
+
+//
+// "APIC" Multiple APIC Description Table
+//
+#define EFI_ACPI_2_0_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE 0x43495041
+
+//
+// "PSDT" Persistent System Description Table
+//
+#define EFI_ACPI_2_0_PERSISTENT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE 0x54445350
+
+//
+// "RSDT" Root System Description Table
+//
+#define EFI_ACPI_2_0_ROOT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE 0x54445352
+
+//
+// "SBST" Smart Battery Specification Table
+//
+#define EFI_ACPI_2_0_SMART_BATTERY_SPECIFICATION_TABLE_SIGNATURE 0x54534253
+
+//
+// "SLIT" System Locality Information Table
+//
+#define EFI_ACPI_2_0_SYSTEM_LOCALITY_INFORMATION_TABLE_SIGNATURE 0x54494C53
+
+//
+// "SPCR" Serial Port Concole Redirection Table
+//
+#define EFI_ACPI_2_0_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE 0x52435053
+
+//
+// "SRAT" Static Resource Affinity Table
+//
+#define EFI_ACPI_2_0_STATIC_RESOURCE_AFFINITY_TABLE_SIGNATURE 0x54415253
+
+//
+// "SSDT" Secondary System Description Table
+//
+#define EFI_ACPI_2_0_SECONDARY_SYSTEM_DESCRIPTION_TABLE_SIGNATURE 0x54445353
+
+//
+// "SPMI" Server Platform Management Interface Table
+//
+#define EFI_ACPI_2_0_SERVER_PLATFORM_MANAGEMENT_INTERFACE_SIGNATURE 0x494D5053
+
+//
+// "XSDT" Extended System Description Table
+//
+#define EFI_ACPI_2_0_EXTENDED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE 0x54445358
+
+#pragma pack()
+
+#endif
diff --git a/EdkCompatibilityPkg/Foundation/Include/IndustryStandard/Acpi3_0.h b/EdkCompatibilityPkg/Foundation/Include/IndustryStandard/Acpi3_0.h new file mode 100644 index 0000000000..be4483ac68 --- /dev/null +++ b/EdkCompatibilityPkg/Foundation/Include/IndustryStandard/Acpi3_0.h @@ -0,0 +1,681 @@ +/*++
+
+Copyright (c) 2007, Intel Corporation
+All rights reserved. This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution. The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+Module Name:
+
+ Acpi3_0.h
+
+Abstract:
+
+ ACPI 3.0 definitions from the ACPI Specification Revision 3.0
+
+--*/
+
+#ifndef _ACPI_3_0_H_
+#define _ACPI_3_0_H_
+
+//
+// Statements that include other files
+//
+#include "AcpiCommon.h"
+
+//
+// Ensure proper structure formats
+//
+#pragma pack(1)
+//
+// ACPI Specification Revision
+//
+#define EFI_ACPI_3_0_REVISION 0x03
+
+//
+// ACPI 3.0 Generic Address Space definition
+//
+typedef struct {
+ UINT8 AddressSpaceId;
+ UINT8 RegisterBitWidth;
+ UINT8 RegisterBitOffset;
+ UINT8 AccessSize;
+ UINT64 Address;
+} EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE;
+
+//
+// Generic Address Space Address IDs
+//
+#define EFI_ACPI_3_0_SYSTEM_MEMORY 0
+#define EFI_ACPI_3_0_SYSTEM_IO 1
+#define EFI_ACPI_3_0_PCI_CONFIGURATION_SPACE 2
+#define EFI_ACPI_3_0_EMBEDDED_CONTROLLER 3
+#define EFI_ACPI_3_0_SMBUS 4
+#define EFI_ACPI_3_0_FUNCTIONAL_FIXED_HARDWARE 0x7F
+
+//
+// Generic Address Space Access Sizes
+//
+#define EFI_ACPI_3_0_UNDEFINED 0
+#define EFI_ACPI_3_0_BYTE 1
+#define EFI_ACPI_3_0_WORD 2
+#define EFI_ACPI_3_0_DWORD 3
+#define EFI_ACPI_3_0_QWORD 4
+
+//
+// ACPI 3.0 table structures
+//
+//
+// Root System Description Pointer Structure
+//
+typedef struct {
+ UINT64 Signature;
+ UINT8 Checksum;
+ UINT8 OemId[6];
+ UINT8 Revision;
+ UINT32 RsdtAddress;
+ UINT32 Length;
+ UINT64 XsdtAddress;
+ UINT8 ExtendedChecksum;
+ UINT8 Reserved[3];
+} EFI_ACPI_3_0_ROOT_SYSTEM_DESCRIPTION_POINTER;
+
+//
+// RSD_PTR Revision (as defined in ACPI 3.0 spec.)
+//
+#define EFI_ACPI_3_0_ROOT_SYSTEM_DESCRIPTION_POINTER_REVISION 0x02 // ACPISpec30 (Revision 3.0) says current value is 2
+//
+// Common table header, this prefaces all ACPI tables, including FACS, but
+// excluding the RSD PTR structure
+//
+typedef struct {
+ UINT32 Signature;
+ UINT32 Length;
+} EFI_ACPI_3_0_COMMON_HEADER;
+
+//
+// Root System Description Table
+// No definition needed as it is a common description table header followed by a
+// variable number of UINT32 table pointers.
+//
+//
+// RSDT Revision (as defined in ACPI 3.0 spec.)
+//
+#define EFI_ACPI_3_0_ROOT_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01
+
+//
+// Extended System Description Table
+// No definition needed as it is a common description table header followed by a
+// variable number of UINT64 table pointers.
+//
+//
+// XSDT Revision (as defined in ACPI 3.0 spec.)
+//
+#define EFI_ACPI_3_0_EXTENDED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01
+
+//
+// Fixed ACPI Description Table Structure (FADT)
+//
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 FirmwareCtrl;
+ UINT32 Dsdt;
+ UINT8 Reserved0;
+ UINT8 PreferredPmProfile;
+ UINT16 SciInt;
+ UINT32 SmiCmd;
+ UINT8 AcpiEnable;
+ UINT8 AcpiDisable;
+ UINT8 S4BiosReq;
+ UINT8 PstateCnt;
+ UINT32 Pm1aEvtBlk;
+ UINT32 Pm1bEvtBlk;
+ UINT32 Pm1aCntBlk;
+ UINT32 Pm1bCntBlk;
+ UINT32 Pm2CntBlk;
+ UINT32 PmTmrBlk;
+ UINT32 Gpe0Blk;
+ UINT32 Gpe1Blk;
+ UINT8 Pm1EvtLen;
+ UINT8 Pm1CntLen;
+ UINT8 Pm2CntLen;
+ UINT8 PmTmrLen;
+ UINT8 Gpe0BlkLen;
+ UINT8 Gpe1BlkLen;
+ UINT8 Gpe1Base;
+ UINT8 CstCnt;
+ UINT16 PLvl2Lat;
+ UINT16 PLvl3Lat;
+ UINT16 FlushSize;
+ UINT16 FlushStride;
+ UINT8 DutyOffset;
+ UINT8 DutyWidth;
+ UINT8 DayAlrm;
+ UINT8 MonAlrm;
+ UINT8 Century;
+ UINT16 IaPcBootArch;
+ UINT8 Reserved1;
+ UINT32 Flags;
+ EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE ResetReg;
+ UINT8 ResetValue;
+ UINT8 Reserved2[3];
+ UINT64 XFirmwareCtrl;
+ UINT64 XDsdt;
+ EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE XPm1aEvtBlk;
+ EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE XPm1bEvtBlk;
+ EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE XPm1aCntBlk;
+ EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE XPm1bCntBlk;
+ EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE XPm2CntBlk;
+ EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE XPmTmrBlk;
+ EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE XGpe0Blk;
+ EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE XGpe1Blk;
+} EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE;
+
+//
+// FADT Version (as defined in ACPI 3.0 spec.)
+//
+#define EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION 0x04
+
+//
+// Fixed ACPI Description Table Preferred Power Management Profile
+//
+#define EFI_ACPI_3_0_PM_PROFILE_UNSPECIFIED 0
+#define EFI_ACPI_3_0_PM_PROFILE_DESKTOP 1
+#define EFI_ACPI_3_0_PM_PROFILE_MOBILE 2
+#define EFI_ACPI_3_0_PM_PROFILE_WORKSTATION 3
+#define EFI_ACPI_3_0_PM_PROFILE_ENTERPRISE_SERVER 4
+#define EFI_ACPI_3_0_PM_PROFILE_SOHO_SERVER 5
+#define EFI_ACPI_3_0_PM_PROFILE_APPLIANCE_PC 6
+#define EFI_ACPI_3_0_PM_PROFILE_PERFORMANCE_SERVER 7
+
+//
+// Fixed ACPI Description Table Boot Architecture Flags
+// All other bits are reserved and must be set to 0.
+//
+#define EFI_ACPI_3_0_LEGACY_DEVICES (1 << 0)
+#define EFI_ACPI_3_0_8042 (1 << 1)
+#define EFI_ACPI_3_0_VGA_NOT_PRESENT (1 << 2)
+#define EFI_ACPI_3_0_MSI_NOT_SUPPORTED (1 << 3)
+#define EFI_ACPI_3_0_PCIE_ASPM_CONTROLS (1 << 4)
+//
+// Fixed ACPI Description Table Fixed Feature Flags
+// All other bits are reserved and must be set to 0.
+//
+#define EFI_ACPI_3_0_WBINVD (1 << 0)
+#define EFI_ACPI_3_0_WBINVD_FLUSH (1 << 1)
+#define EFI_ACPI_3_0_PROC_C1 (1 << 2)
+#define EFI_ACPI_3_0_P_LVL2_UP (1 << 3)
+#define EFI_ACPI_3_0_PWR_BUTTON (1 << 4)
+#define EFI_ACPI_3_0_SLP_BUTTON (1 << 5)
+#define EFI_ACPI_3_0_FIX_RTC (1 << 6)
+#define EFI_ACPI_3_0_RTC_S4 (1 << 7)
+#define EFI_ACPI_3_0_TMR_VAL_EXT (1 << 8)
+#define EFI_ACPI_3_0_DCK_CAP (1 << 9)
+#define EFI_ACPI_3_0_RESET_REG_SUP (1 << 10)
+#define EFI_ACPI_3_0_SEALED_CASE (1 << 11)
+#define EFI_ACPI_3_0_HEADLESS (1 << 12)
+#define EFI_ACPI_3_0_CPU_SW_SLP (1 << 13)
+#define EFI_ACPI_3_0_PCI_EXP_WAK (1 << 14)
+#define EFI_ACPI_3_0_USE_PLATFORM_CLOCK (1 << 15)
+#define EFI_ACPI_3_0_S4_RTC_STS_VALID (1 << 16)
+#define EFI_ACPI_3_0_REMOTE_POWER_ON_CAPABLE (1 << 17)
+#define EFI_ACPI_3_0_FORCE_APIC_CLUSTER_MODEL (1 << 18)
+#define EFI_ACPI_3_0_FORCE_APIC_PHYSICAL_DESTINATION_MODE (1 << 19)
+
+//
+// Firmware ACPI Control Structure
+//
+typedef struct {
+ UINT32 Signature;
+ UINT32 Length;
+ UINT32 HardwareSignature;
+ UINT32 FirmwareWakingVector;
+ UINT32 GlobalLock;
+ UINT32 Flags;
+ UINT64 XFirmwareWakingVector;
+ UINT8 Version;
+ UINT8 Reserved[31];
+} EFI_ACPI_3_0_FIRMWARE_ACPI_CONTROL_STRUCTURE;
+
+//
+// FACS Version (as defined in ACPI 3.0 spec.)
+//
+#define EFI_ACPI_3_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_VERSION 0x01
+
+//
+// Firmware Control Structure Feature Flags
+// All other bits are reserved and must be set to 0.
+//
+#define EFI_ACPI_3_0_S4BIOS_F (1 << 0)
+
+//
+// Differentiated System Description Table,
+// Secondary System Description Table
+// and Persistent System Description Table,
+// no definition needed as they are common description table header followed by a
+// definition block.
+//
+#define EFI_ACPI_3_0_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x02
+#define EFI_ACPI_3_0_SECONDARY_SYSTEM_DESCRIPTION_TABLE_REVISION 0x02
+
+//
+// Multiple APIC Description Table header definition. The rest of the table
+// must be defined in a platform specific manner.
+//
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 LocalApicAddress;
+ UINT32 Flags;
+} EFI_ACPI_3_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER;
+
+//
+// MADT Revision (as defined in ACPI 3.0 spec.)
+//
+#define EFI_ACPI_3_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION 0x02
+
+//
+// Multiple APIC Flags
+// All other bits are reserved and must be set to 0.
+//
+#define EFI_ACPI_3_0_PCAT_COMPAT (1 << 0)
+
+//
+// Multiple APIC Description Table APIC structure types
+// All other values between 0x09 an 0xFF are reserved and
+// will be ignored by OSPM.
+//
+#define EFI_ACPI_3_0_PROCESSOR_LOCAL_APIC 0x00
+#define EFI_ACPI_3_0_IO_APIC 0x01
+#define EFI_ACPI_3_0_INTERRUPT_SOURCE_OVERRIDE 0x02
+#define EFI_ACPI_3_0_NON_MASKABLE_INTERRUPT_SOURCE 0x03
+#define EFI_ACPI_3_0_LOCAL_APIC_NMI 0x04
+#define EFI_ACPI_3_0_LOCAL_APIC_ADDRESS_OVERRIDE 0x05
+#define EFI_ACPI_3_0_IO_SAPIC 0x06
+#define EFI_ACPI_3_0_LOCAL_SAPIC 0x07
+#define EFI_ACPI_3_0_PLATFORM_INTERRUPT_SOURCES 0x08
+
+//
+// APIC Structure Definitions
+//
+//
+// Processor Local APIC Structure Definition
+//
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 AcpiProcessorId;
+ UINT8 ApicId;
+ UINT32 Flags;
+} EFI_ACPI_3_0_PROCESSOR_LOCAL_APIC_STRUCTURE;
+
+//
+// Local APIC Flags. All other bits are reserved and must be 0.
+//
+#define EFI_ACPI_3_0_LOCAL_APIC_ENABLED (1 << 0)
+
+//
+// IO APIC Structure
+//
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 IoApicId;
+ UINT8 Reserved;
+ UINT32 IoApicAddress;
+ UINT32 GlobalSystemInterruptBase;
+} EFI_ACPI_3_0_IO_APIC_STRUCTURE;
+
+//
+// Interrupt Source Override Structure
+//
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 Bus;
+ UINT8 Source;
+ UINT32 GlobalSystemInterrupt;
+ UINT16 Flags;
+} EFI_ACPI_3_0_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE;
+
+//
+// Platform Interrupt Sources Structure Definition
+//
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Flags;
+ UINT8 InterruptType;
+ UINT8 ProcessorId;
+ UINT8 ProcessorEid;
+ UINT8 IoSapicVector;
+ UINT32 GlobalSystemInterrupt;
+ UINT32 PlatformInterruptSourceFlags;
+ UINT8 CpeiProcessorOverride;
+ UINT8 Reserved[31];
+} EFI_ACPI_3_0_PLATFORM_INTERRUPT_APIC_STRUCTURE;
+
+//
+// MPS INTI flags.
+// All other bits are reserved and must be set to 0.
+//
+#define EFI_ACPI_3_0_POLARITY (3 << 0)
+#define EFI_ACPI_3_0_TRIGGER_MODE (3 << 2)
+
+//
+// Non-Maskable Interrupt Source Structure
+//
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Flags;
+ UINT32 GlobalSystemInterrupt;
+} EFI_ACPI_3_0_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE;
+
+//
+// Local APIC NMI Structure
+//
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 AcpiProcessorId;
+ UINT16 Flags;
+ UINT8 LocalApicLint;
+} EFI_ACPI_3_0_LOCAL_APIC_NMI_STRUCTURE;
+
+//
+// Local APIC Address Override Structure
+//
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Reserved;
+ UINT64 LocalApicAddress;
+} EFI_ACPI_3_0_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE;
+
+//
+// IO SAPIC Structure
+//
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 IoApicId;
+ UINT8 Reserved;
+ UINT32 GlobalSystemInterruptBase;
+ UINT64 IoSapicAddress;
+} EFI_ACPI_3_0_IO_SAPIC_STRUCTURE;
+
+//
+// Local SAPIC Structure
+// This struct followed by a null-terminated ASCII string - ACPI Processor UID String
+//
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 AcpiProcessorId;
+ UINT8 LocalSapicId;
+ UINT8 LocalSapicEid;
+ UINT8 Reserved[3];
+ UINT32 Flags;
+ UINT32 ACPIProcessorUIDValue;
+} EFI_ACPI_3_0_PROCESSOR_LOCAL_SAPIC_STRUCTURE;
+
+//
+// Platform Interrupt Sources Structure
+//
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Flags;
+ UINT8 InterruptType;
+ UINT8 ProcessorId;
+ UINT8 ProcessorEid;
+ UINT8 IoSapicVector;
+ UINT32 GlobalSystemInterrupt;
+ UINT32 PlatformInterruptSourceFlags;
+} EFI_ACPI_3_0_PLATFORM_INTERRUPT_SOURCES_STRUCTURE;
+
+//
+// Platform Interrupt Source Flags.
+// All other bits are reserved and must be set to 0.
+//
+#define EFI_ACPI_3_0_CPEI_PROCESSOR_OVERRIDE (1 << 0)
+
+//
+// Smart Battery Description Table (SBST)
+//
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 WarningEnergyLevel;
+ UINT32 LowEnergyLevel;
+ UINT32 CriticalEnergyLevel;
+} EFI_ACPI_3_0_SMART_BATTERY_DESCRIPTION_TABLE;
+
+//
+// SBST Version (as defined in ACPI 3.0 spec.)
+//
+#define EFI_ACPI_3_0_SMART_BATTERY_DESCRIPTION_TABLE_REVISION 0x01
+
+//
+// Embedded Controller Boot Resources Table (ECDT)
+// The table is followed by a null terminated ASCII string that contains
+// a fully qualified reference to the name space object.
+//
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE EcControl;
+ EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE EcData;
+ UINT32 Uid;
+ UINT8 GpeBit;
+} EFI_ACPI_3_0_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE;
+
+//
+// ECDT Version (as defined in ACPI 3.0 spec.)
+//
+#define EFI_ACPI_3_0_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE_REVISION 0x01
+
+//
+// System Resource Affinity Table (SRAT. The rest of the table
+// must be defined in a platform specific manner.
+//
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 Reserved1; // Must be set to 1
+ UINT64 Reserved2;
+} EFI_ACPI_3_0_SYSTEM_RESOURCE_AFFINITY_TABLE_HEADER;
+
+//
+// SRAT Version (as defined in ACPI 3.0 spec.)
+//
+#define EFI_ACPI_3_0_SYSTEM_RESOURCE_AFFINITY_TABLE_REVISION 0x02
+
+//
+// SRAT structure types.
+// All other values between 0x02 an 0xFF are reserved and
+// will be ignored by OSPM.
+//
+#define EFI_ACPI_3_0_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY 0x00
+#define EFI_ACPI_3_0_MEMORY_AFFINITY 0x01
+
+//
+// Processor Local APIC/SAPIC Affinity Structure Definition
+//
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 ProximityDomain7To0;
+ UINT8 ApicId;
+ UINT32 Flags;
+ UINT8 LocalSapicEid;
+ UINT8 ProximityDomain31To8[3];
+ UINT8 Reserved[4];
+} EFI_ACPI_3_0_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY_STRUCTURE;
+
+//
+// Local APIC/SAPIC Flags. All other bits are reserved and must be 0.
+//
+#define EFI_ACPI_3_0_PROCESSOR_LOCAL_APIC_SAPIC_ENABLED (1 << 0)
+
+//
+// Memory Affinity Structure Definition
+//
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT32 ProximityDomain;
+ UINT16 Reserved1;
+ UINT32 AddressBaseLow;
+ UINT32 AddressBaseHigh;
+ UINT32 LengthLow;
+ UINT32 LengthHigh;
+ UINT32 Reserved2;
+ UINT32 Flags;
+ UINT64 Reserved3;
+} EFI_ACPI_3_0_MEMORY_AFFINITY_STRUCTURE;
+
+//
+// Memory Flags. All other bits are reserved and must be 0.
+//
+#define EFI_ACPI_3_0_MEMORY_ENABLED (1 << 0)
+#define EFI_ACPI_3_0_MEMORY_HOT_PLUGGABLE (1 << 1)
+#define EFI_ACPI_3_0_MEMORY_NONVOLATILE (1 << 2)
+
+//
+// System Locality Distance Information Table (SLIT).
+// The rest of the table is a matrix.
+//
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT64 NumberOfSystemLocalities;
+} EFI_ACPI_3_0_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_HEADER;
+
+//
+// SLIT Version (as defined in ACPI 3.0 spec.)
+//
+#define EFI_ACPI_3_0_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_REVISION 0x01
+
+//
+// Known table signatures
+//
+//
+// "RSD PTR " Root System Description Pointer
+//
+#define EFI_ACPI_3_0_ROOT_SYSTEM_DESCRIPTION_POINTER_SIGNATURE 0x2052545020445352
+
+//
+// "APIC" Multiple APIC Description Table
+//
+#define EFI_ACPI_3_0_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE 0x43495041
+
+//
+// "DSDT" Differentiated System Description Table
+//
+#define EFI_ACPI_3_0_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE 0x54445344
+
+//
+// "ECDT" Embedded Controller Boot Resources Table
+//
+#define EFI_ACPI_3_0_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE_SIGNATURE 0x54444345
+
+//
+// "FACP" Fixed ACPI Description Table
+//
+#define EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE 0x50434146
+
+//
+// "FACS" Firmware ACPI Control Structure
+//
+#define EFI_ACPI_3_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE 0x53434146
+
+//
+// "PSDT" Persistent System Description Table
+//
+#define EFI_ACPI_3_0_PERSISTENT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE 0x54445350
+
+//
+// "RSDT" Root System Description Table
+//
+#define EFI_ACPI_3_0_ROOT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE 0x54445352
+
+//
+// "SBST" Smart Battery Specification Table
+//
+#define EFI_ACPI_3_0_SMART_BATTERY_SPECIFICATION_TABLE_SIGNATURE 0x54534253
+
+//
+// "SLIT" System Locality Information Table
+//
+#define EFI_ACPI_3_0_SYSTEM_LOCALITY_INFORMATION_TABLE_SIGNATURE 0x54494C53
+
+//
+// "SRAT" System Resource Affinity Table
+//
+#define EFI_ACPI_3_0_SYSTEM_RESOURCE_AFFINITY_TABLE_SIGNATURE 0x54415253
+
+//
+// "SSDT" Secondary System Description Table
+//
+#define EFI_ACPI_3_0_SECONDARY_SYSTEM_DESCRIPTION_TABLE_SIGNATURE 0x54445353
+
+//
+// "XSDT" Extended System Description Table
+//
+#define EFI_ACPI_3_0_EXTENDED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE 0x54445358
+
+//
+// "BOOT" MS Simple Boot Spec
+//
+#define EFI_ACPI_3_0_SIMPLE_BOOT_FLAG_TABLE_SIGNATURE 0x544F4F42
+
+//
+// "CPEP" Corrected Platform Error Polling Table
+// See
+//
+#define EFI_ACPI_3_0_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_SIGNATURE 0x50455043
+
+//
+// "DBGP" MS Debug Port Spec
+//
+#define EFI_ACPI_3_0_DEBUG_PORT_TABLE_SIGNATURE 0x50474244
+
+//
+// "ETDT" Event Timer Description Table
+//
+#define EFI_ACPI_3_0_EVENT_TIMER_DESCRIPTION_TABLE_SIGNATURE 0x54445445
+
+//
+// "HPET" IA-PC High Precision Event Timer Table
+//
+#define EFI_ACPI_3_0_HIGH_PRECISION_EVENT_TIMER_TABLE_SIGNATURE 0x54455048
+
+//
+// "MCFG" PCI Express Memory Mapped Configuration Space Base Address Description Table
+//
+#define EFI_ACPI_3_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE 0x4746434D
+
+//
+// "SPCR" Serial Port Concole Redirection Table
+//
+#define EFI_ACPI_3_0_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE 0x52435053
+
+//
+// "SPMI" Server Platform Management Interface Table
+//
+#define EFI_ACPI_3_0_SERVER_PLATFORM_MANAGEMENT_INTERFACE_TABLE_SIGNATURE 0x494D5053
+
+//
+// "TCPA" Trusted Computing Platform Alliance Capabilities Table
+//
+#define EFI_ACPI_3_0_TRUSTED_COMPUTING_PLATFORM_ALLIANCE_CAPABILITIES_TABLE_SIGNATURE 0x41504354
+
+//
+// "WDRT" Watchdog Resource Table
+//
+#define EFI_ACPI_3_0_WATCHDOG_RESOURCE_TABLE_SIGNATURE 0x54524457
+
+#pragma pack()
+
+#endif
diff --git a/EdkCompatibilityPkg/Foundation/Include/IndustryStandard/AcpiCommon.h b/EdkCompatibilityPkg/Foundation/Include/IndustryStandard/AcpiCommon.h new file mode 100644 index 0000000000..945e787788 --- /dev/null +++ b/EdkCompatibilityPkg/Foundation/Include/IndustryStandard/AcpiCommon.h @@ -0,0 +1,98 @@ +/*++
+
+Copyright (c) 2007, Intel Corporation
+All rights reserved. This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution. The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+Module Name:
+
+ AcpiCommon.h
+
+Abstract:
+
+ This file contains some basic ACPI definitions that are consumed by drivers
+ that do not care about ACPI versions.
+
+--*/
+
+#ifndef _ACPI_COMMON_H_
+#define _ACPI_COMMON_H_
+
+#include "Tiano.h"
+
+//
+// Common table header, this prefaces all ACPI tables, including FACS, but
+// excluding the RSD PTR structure
+//
+typedef struct {
+ UINT32 Signature;
+ UINT32 Length;
+} EFI_ACPI_COMMON_HEADER;
+
+//
+// Common ACPI description table header. This structure prefaces most ACPI tables.
+//
+#pragma pack(1)
+
+typedef struct {
+ UINT32 Signature;
+ UINT32 Length;
+ UINT8 Revision;
+ UINT8 Checksum;
+ UINT8 OemId[6];
+ UINT64 OemTableId;
+ UINT32 OemRevision;
+ UINT32 CreatorId;
+ UINT32 CreatorRevision;
+} EFI_ACPI_DESCRIPTION_HEADER;
+
+#pragma pack()
+//
+// Define for Pci Host Bridge Resource Allocation
+//
+#define ACPI_ADDRESS_SPACE_DESCRIPTOR 0x8A
+#define ACPI_END_TAG_DESCRIPTOR 0x79
+
+#define ACPI_ADDRESS_SPACE_TYPE_MEM 0x00
+#define ACPI_ADDRESS_SPACE_TYPE_IO 0x01
+#define ACPI_ADDRESS_SPACE_TYPE_BUS 0x02
+
+//
+// Make sure structures match spec
+//
+#pragma pack(1)
+
+typedef struct {
+ UINT8 Desc;
+ UINT16 Len;
+ UINT8 ResType;
+ UINT8 GenFlag;
+ UINT8 SpecificFlag;
+ UINT64 AddrSpaceGranularity;
+ UINT64 AddrRangeMin;
+ UINT64 AddrRangeMax;
+ UINT64 AddrTranslationOffset;
+ UINT64 AddrLen;
+} EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR;
+
+typedef struct {
+ UINT8 Desc;
+ UINT8 Checksum;
+} EFI_ACPI_END_TAG_DESCRIPTOR;
+
+//
+// General use definitions
+//
+#define EFI_ACPI_RESERVED_BYTE 0x00
+#define EFI_ACPI_RESERVED_WORD 0x0000
+#define EFI_ACPI_RESERVED_DWORD 0x00000000
+#define EFI_ACPI_RESERVED_QWORD 0x0000000000000000
+
+#pragma pack()
+
+#endif
diff --git a/EdkCompatibilityPkg/Foundation/Include/IndustryStandard/AlertStandardFormatTable.h b/EdkCompatibilityPkg/Foundation/Include/IndustryStandard/AlertStandardFormatTable.h new file mode 100644 index 0000000000..f750a63b40 --- /dev/null +++ b/EdkCompatibilityPkg/Foundation/Include/IndustryStandard/AlertStandardFormatTable.h @@ -0,0 +1,123 @@ +/*++
+
+Copyright (c) 2007, Intel Corporation
+All rights reserved. This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution. The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+Module Name:
+
+ AlertStandardFormatTable.h
+
+Abstract:
+
+ ACPI Alert Standard Format Description Table ASF! as described
+ in the ASF2.0 Specification
+
+--*/
+
+#ifndef _ALERT_STANDARD_FORMAT_TABLE_H
+#define _ALERT_STANDARD_FORMAT_TABLE_H
+
+#include "Acpi2_0.h"
+
+//
+// Ensure proper structure formats
+//
+#pragma pack (1)
+
+//
+// Information Record header that appears at the beginning of each record
+//
+typedef struct {
+ UINT8 Type;
+ UINT8 Reserved;
+ UINT16 RecordLength;
+} EFI_ACPI_ASF_RECORD_HEADER;
+
+//
+// This structure contains information that identifies the system type
+// and configuration
+//
+typedef struct {
+ EFI_ACPI_ASF_RECORD_HEADER RecordHeader;
+ UINT8 MinWatchDogResetValue;
+ UINT8 MinPollingInterval;
+ UINT16 SystemID;
+ UINT32 IANAManufactureID;
+ UINT8 FeatureFlags;
+ UINT8 Reserved[3];
+} EFI_ACPI_ASF_INFO;
+
+//
+// Alert sensors definition
+//
+#define ASF_ALRT_SENSOR_ARRAY_LENGTH 36
+
+typedef struct {
+ EFI_ACPI_ASF_RECORD_HEADER RecordHeader;
+ UINT8 AssertionEventBitMask;
+ UINT8 DeassertionEventBitMask;
+ UINT8 NumberOfAlerts;
+ UINT8 ArrayElementLength;
+ UINT8 DeviceArray[ASF_ALRT_SENSOR_ARRAY_LENGTH];
+} EFI_ACPI_ASF_ALRT;
+
+//
+// Alert Remote Control System Actions
+//
+#define ASF_RCTL_DEVICES_ARRAY_LENGTH 16
+typedef struct {
+ EFI_ACPI_ASF_RECORD_HEADER RecordHeader;
+ UINT8 NumberOfControls;
+ UINT8 ArrayElementLength;
+ UINT16 RctlReserved;
+ UINT8 ControlArray[ASF_RCTL_DEVICES_ARRAY_LENGTH];
+} EFI_ACPI_ASF_RCTL;
+
+//
+// Remote Control Capabilities
+//
+typedef struct {
+ EFI_ACPI_ASF_RECORD_HEADER RecordHeader;
+ UINT8 RemoteControlCapabilities[7];
+ UINT8 RMCPCompletionCode;
+ UINT32 RMCPIANA;
+ UINT8 RMCPSpecialCommand;
+ UINT8 RMCPSpecialCommandParameter[2];
+ UINT8 RMCPBootOptions[2];
+ UINT8 RMCPOEMParameters[2];
+} EFI_ACPI_ASF_RMCP;
+
+//
+// SMBus Devices with fixed addresses
+//
+#define ASF_ADDR_DEVICE_ARRAY_LENGTH 16
+typedef struct {
+ EFI_ACPI_ASF_RECORD_HEADER RecordHeader;
+ UINT8 SEEPROMAddress;
+ UINT8 NumberOfDevices;
+ UINT8 FixedSmbusAddresses[ASF_ADDR_DEVICE_ARRAY_LENGTH];
+} EFI_ACPI_ASF_ADDR;
+
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ EFI_ACPI_ASF_INFO AsfInfo;
+ EFI_ACPI_ASF_ALRT AsfAlert;
+ EFI_ACPI_ASF_RCTL AsfRctl;
+ EFI_ACPI_ASF_RMCP AsfRmcp;
+ EFI_ACPI_ASF_ADDR AsfAddr;
+} EFI_ACPI_1_0_ASF_DESCRIPTION_TABLE;
+
+//
+// "ASF!" ASF Description Table Signature
+//
+#define EFI_ACPI_1_0_ASF_DESCRIPTION_TABLE_SIGNATURE 0x21465341
+
+#pragma pack ()
+
+#endif // _ALERT_STANDARD_FORMAT_TABLE_H
diff --git a/EdkCompatibilityPkg/Foundation/Include/IndustryStandard/DMARemappingReportingTable.h b/EdkCompatibilityPkg/Foundation/Include/IndustryStandard/DMARemappingReportingTable.h new file mode 100644 index 0000000000..78162c4196 --- /dev/null +++ b/EdkCompatibilityPkg/Foundation/Include/IndustryStandard/DMARemappingReportingTable.h @@ -0,0 +1,202 @@ +/*++
+
+Copyright (c) 2007, Intel Corporation
+All rights reserved. This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution. The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+Module Name:
+
+ DMARemappingReportingTable.h
+
+Abstract:
+
+ The definition for ACPI DMA-Remapping Reporting (DMAR) Table.
+ It is defined in "Intel VT for Direct IO Architecture Specification".
+
+--*/
+
+#ifndef _EFI_DMA_REMAPPING_REPORTING_TABLE_H_
+#define _EFI_DMA_REMAPPING_REPORTING_TABLE_H_
+
+#include "AcpiCommon.h"
+
+//
+// "DMAR" DMAR Description Table Signature
+//
+#define EFI_ACPI_DMAR_DESCRIPTION_TABLE_SIGNATURE 0x52414d44
+
+//
+// DMAR Revision
+//
+#define EFI_ACPI_DMAR_DESCRIPTION_TABLE_REVISION 0x01
+
+//
+// Ensure proper structure formats
+//
+#pragma pack (1)
+
+//
+// Definition for DMA Remapping Structure Types
+//
+#define EFI_ACPI_DMA_REMAPPING_STRUCTURE_TYPE_DRHD 0
+#define EFI_ACPI_DMA_REMAPPING_STRUCTURE_TYPE_RMRR 1
+#define EFI_ACPI_DMA_REMAPPING_STRUCTURE_TYPE_ATSR 2
+
+//
+// Definition for DMA Remapping Structure Header
+//
+typedef struct {
+ UINT16 Type;
+ UINT16 Length;
+} EFI_ACPI_DMAR_STRUCTURE_HEADER;
+
+//
+// Definition for DMA-Remapping PCI Path
+//
+typedef struct {
+ UINT8 Device;
+ UINT8 Function;
+} EFI_ACPI_DMAR_PCI_PATH;
+
+//
+// Definition for DMA-Remapping Device Scope Entry Structure
+//
+#define EFI_ACPI_DEVICE_SCOPE_ENTRY_TYPE_ENDPOINT 0x01
+#define EFI_ACPI_DEVICE_SCOPE_ENTRY_TYPE_BRIDGE 0x02
+#define EFI_ACPI_DEVICE_SCOPE_ENTRY_TYPE_IOAPIC 0x03
+#define EFI_ACPI_DEVICE_SCOPE_ENTRY_TYPE_MSI_CAPABLE_HPET 0x04
+typedef struct {
+ UINT8 DeviceScopeEntryType;
+ UINT8 Length;
+ UINT16 Reserved_2;
+ UINT8 EnumerationID;
+ UINT8 StartingBusNumber;
+} EFI_ACPI_DMAR_DEVICE_SCOPE_ENTRY_STRUCTURE;
+
+//
+// Definition for DMA-Remapping Hardware Definition (DRHD) Structure
+//
+#define EFI_ACPI_DMAR_DRHD_FLAGS_INCLUDE_ALL_SET 0x1
+#define EFI_ACPI_DMAR_DRHD_FLAGS_INCLUDE_ALL_CLEAR 0x0
+typedef struct {
+ UINT16 Type;
+ UINT16 Length;
+ UINT8 Flags;
+ UINT8 Reserved_5;
+ UINT16 SegmentNumber;
+ UINT64 RegisterBaseAddress;
+} EFI_ACPI_DMAR_HARDWARE_UNIT_DEFINITION_STRUCTURE;
+
+//
+// Definition for Reserved Memory Region Reporting (RMRR) Structure
+//
+typedef struct {
+ UINT16 Type;
+ UINT16 Length;
+ UINT8 Reserved_4[2];
+ UINT16 SegmentNumber;
+ UINT64 ReservedMemoryRegionBaseAddress;
+ UINT64 ReservedMemoryRegionLimitAddress;
+} EFI_ACPI_DMAR_RESERVED_MEMORY_REGION_REPORTING_STRUCTURE;
+
+//
+// Definition for Root Port ATS Capability Reporting (ATSR) Structure
+//
+#define EFI_ACPI_DMAR_ATSR_FLAGS_ALL_PORTS_SET 0x1
+#define EFI_ACPI_DMAR_ATSR_FLAGS_ALL_PORTS_CLEAR 0x0
+typedef struct {
+ UINT16 Type;
+ UINT16 Length;
+ UINT8 Flags;
+ UINT8 Reserved_5;
+ UINT16 SegmentNumber;
+} EFI_ACPI_DMAR_ROOT_PORT_ATS_CAPABILITY_REPORTING_STRUCTURE;
+
+//
+// Definition for DMA Remapping Structure
+//
+typedef union {
+ EFI_ACPI_DMAR_STRUCTURE_HEADER DMARStructureHeader;
+ EFI_ACPI_DMAR_HARDWARE_UNIT_DEFINITION_STRUCTURE DMARHardwareUnitDefinition;
+ EFI_ACPI_DMAR_RESERVED_MEMORY_REGION_REPORTING_STRUCTURE DMARReservedMemoryRegionReporting;
+ EFI_ACPI_DMAR_ROOT_PORT_ATS_CAPABILITY_REPORTING_STRUCTURE DMARRootPortATSCapabilityReporting;
+} EFI_ACPI_DMA_REMAPPING_STRUCTURE;
+
+//
+// Definition for DMA-Remapping Reporting ACPI Table
+//
+#define EFI_ACPI_DMAR_TABLE_FLAGS_INTR_REMAP_SET 0x01
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT8 HostAddressWidth;
+ UINT8 Flags;
+ UINT8 Reserved_38[10];
+} EFI_ACPI_DMAR_DESCRIPTION_TABLE;
+
+//
+// The Platform specific definition can be as follows:
+// NOTE: we use /**/ as comment for user convenience to copy it.
+//
+
+/*
+
+//
+// Dmar.h
+//
+
+#define EFI_ACPI_MAX_NUM_PCI_PATH_ENTRIES 0x01 // user need to update
+typedef struct {
+ EFI_ACPI_DMAR_DEVICE_SCOPE_ENTRY_STRUCTURE Header;
+ EFI_ACPI_DMAR_PCI_PATH PciPath[EFI_ACPI_MAX_NUM_PCI_PATH_ENTRIES];
+} EFI_ACPI_3_0_DMAR_DEVICE_SCOPE_ENTRY_STRUCTURE;
+
+#define EFI_ACPI_MAX_NUM_OF_DEVICE_SCOPE_PER_DHRD_ENTRY 0x01 // user need to update
+typedef struct {
+ EFI_ACPI_DMAR_HARDWARE_UNIT_DEFINITION_STRUCTURE Header;
+ EFI_ACPI_3_0_DMAR_DEVICE_SCOPE_ENTRY_STRUCTURE DeviceScopeEntry[EFI_ACPI_MAX_NUM_OF_DEVICE_SCOPE_PER_DHRD_ENTRY];
+} EFI_ACPI_3_0_DMAR_HARDWARE_UNIT_DEFINITION_STRUCTURE;
+
+#define EFI_ACPI_MAX_NUM_OF_DEVICE_SCOPE_PER_RMRR_ENTRY 0x01 // user need to update
+typedef struct {
+ EFI_ACPI_DMAR_RESERVED_MEMORY_REGION_REPORTING_STRUCTURE Header;
+ EFI_ACPI_3_0_DMAR_DEVICE_SCOPE_ENTRY_STRUCTURE DeviceScopeEntry[EFI_ACPI_MAX_NUM_OF_DEVICE_SCOPE_PER_RMRR_ENTRY];
+} EFI_ACPI_3_0_DMAR_RESERVED_MEMORY_REGION_REPORTING_STRUCTURE;
+
+#define EFI_ACPI_MAX_NUM_OF_DEVICE_SCOPE_PER_ATSR_ENTRY 0x01 // user need to update
+typedef struct {
+ EFI_ACPI_DMAR_ROOT_PORT_ATS_CAPABILITY_REPORTING_STRUCTURE Header;
+ EFI_ACPI_3_0_DMAR_DEVICE_SCOPE_ENTRY_STRUCTURE DeviceScopeEntry[EFI_ACPI_MAX_NUM_OF_DEVICE_SCOPE_PER_ATSR_ENTRY];
+} EFI_ACPI_3_0_DMAR_ROOT_PORT_ATS_CAPABILITY_REPORTING_STRUCTURE;
+
+#define EFI_ACPI_DMAR_DHRD_ENTRY_COUNT 0x1 // user need to update
+#define EFI_ACPI_DMAR_RMRR_ENTRY_COUNT 0x1 // user need to update
+#define EFI_ACPI_DMAR_ATSR_ENTRY_COUNT 0x1 // user need to update
+
+typedef struct {
+ EFI_ACPI_DMAR_DESCRIPTION_TABLE Header;
+
+#if EFI_ACPI_3_0_DMAR_DHRD_ENTRY_COUNT > 0
+ EFI_ACPI_3_0_DMAR_HARDWARE_UNIT_DEFINITION_STRUCTURE Dhrd[EFI_ACPI_DMAR_DHRD_ENTRY_COUNT];
+#endif
+
+#if EFI_ACPI_3_0_DMAR_RMRR_ENTRY_COUNT > 0
+ EFI_ACPI_3_0_DMAR_RESERVED_MEMORY_REGION_REPORTING_STRUCTURE Rmrr[EFI_ACPI_DMAR_RMRR_ENTRY_COUNT];
+#endif
+
+#if EFI_ACPI_3_0_DMAR_ATSR_ENTRY_COUNT > 0
+ EFI_ACPI_3_0_DMAR_ROOT_PORT_ATS_CAPABILITY_REPORTING_STRUCTURE Atsr[EFI_ACPI_DMAR_ATSR_ENTRY_COUNT];
+#endif
+
+} EFI_ACPI_3_0_DMA_REMAPPING_REPORTING_TABLE;
+
+*/
+
+#pragma pack()
+
+#endif
+
diff --git a/EdkCompatibilityPkg/Foundation/Include/IndustryStandard/HighPrecisionEventTimerTable.h b/EdkCompatibilityPkg/Foundation/Include/IndustryStandard/HighPrecisionEventTimerTable.h new file mode 100644 index 0000000000..ee23907633 --- /dev/null +++ b/EdkCompatibilityPkg/Foundation/Include/IndustryStandard/HighPrecisionEventTimerTable.h @@ -0,0 +1,62 @@ +/*++
+
+Copyright (c) 2007, Intel Corporation
+All rights reserved. This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution. The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+Module Name:
+
+ HighPrecisionEventTimerTable.h
+
+Abstract:
+
+ ACPI high precision event timer table definition, defined at
+ Intel IA-PC HPET (High Precision Event Timers) Specification.
+
+--*/
+
+#ifndef _HIGH_PRECISION_EVENT_TIMER_TABLE_H_
+#define _HIGH_PRECISION_EVENT_TIMER_TABLE_H_
+
+//
+// Include files
+//
+#include "Acpi2_0.h"
+
+//
+// Ensure proper structure formats
+//
+#pragma pack(1)
+//
+// High Precision Event Timer Table header definition.
+//
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 EventTimerBlockId;
+ EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE BaseAddressLower32Bit;
+ UINT8 HpetNumber;
+ UINT16 MainCounterMinimumClockTickInPeriodicMode;
+ UINT8 PageProtectionAndOemAttribute;
+} EFI_ACPI_HIGH_PRECISION_EVENT_TIMER_TABLE_HEADER;
+
+//
+// HPET Revision (defined in spec)
+//
+#define EFI_ACPI_HIGH_PRECISION_EVENT_TIMER_TABLE_REVISION 0x01
+
+//
+// Page protection setting
+// Values 3 through 15 are reserved for use by the specification
+//
+#define EFI_ACPI_NO_PAGE_PROTECTION 0
+#define EFI_ACPI_4KB_PAGE_PROTECTION 1
+#define EFI_ACPI_64KB_PAGE_PROTECTION 2
+
+#pragma pack()
+
+#endif
diff --git a/EdkCompatibilityPkg/Foundation/Include/IndustryStandard/LegacyBiosMpTable.h b/EdkCompatibilityPkg/Foundation/Include/IndustryStandard/LegacyBiosMpTable.h new file mode 100644 index 0000000000..bf484a7541 --- /dev/null +++ b/EdkCompatibilityPkg/Foundation/Include/IndustryStandard/LegacyBiosMpTable.h @@ -0,0 +1,283 @@ +/*++
+
+Copyright (c) 2007, Intel Corporation
+All rights reserved. This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution. The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+Module Name:
+
+ LegacyBiosMpTable.h
+
+Abstract:
+ Defives data structures per Multi Processor Specification Ver 1.4.
+
+--*/
+
+#ifndef LEGACY_BIOS_MPTABLE_H_
+#define LEGACY_BIOS_MPTABLE_H_
+
+#include "Tiano.h"
+
+#define EFI_LEGACY_MP_TABLE_REV_1_4 0x04
+
+//
+// Define MP table structures. All are packed.
+//
+#pragma pack(push, 1)
+
+#define EFI_LEGACY_MP_TABLE_FLOATING_POINTER_SIGNATURE EFI_SIGNATURE_32 ('_', 'M', 'P', '_')
+typedef struct {
+ UINT32 Signature;
+ UINT32 PhysicalAddress;
+ UINT8 Length;
+ UINT8 SpecRev;
+ UINT8 Checksum;
+ UINT8 FeatureByte1;
+ struct {
+ UINT32 Reserved1 : 6;
+ UINT32 MutipleClk : 1;
+ UINT32 Imcr : 1;
+ UINT32 Reserved2 : 24;
+ } FeatureByte2_5;
+} EFI_LEGACY_MP_TABLE_FLOATING_POINTER;
+
+#define EFI_LEGACY_MP_TABLE_HEADER_SIGNATURE EFI_SIGNATURE_32 ('P', 'C', 'M', 'P')
+typedef struct {
+ UINT32 Signature;
+ UINT16 BaseTableLength;
+ UINT8 SpecRev;
+ UINT8 Checksum;
+ CHAR8 OemId[8];
+ CHAR8 OemProductId[12];
+ UINT32 OemTablePointer;
+ UINT16 OemTableSize;
+ UINT16 EntryCount;
+ UINT32 LocalApicAddress;
+ UINT16 ExtendedTableLength;
+ UINT8 ExtendedChecksum;
+ UINT8 Reserved;
+} EFI_LEGACY_MP_TABLE_HEADER;
+
+typedef struct {
+ UINT8 EntryType;
+} EFI_LEGACY_MP_TABLE_ENTRY_TYPE;
+
+//
+// Entry Type 0: Processor.
+//
+#define EFI_LEGACY_MP_TABLE_ENTRY_TYPE_PROCESSOR 0x00
+typedef struct {
+ UINT8 EntryType;
+ UINT8 Id;
+ UINT8 Ver;
+ struct {
+ UINT8 Enabled : 1;
+ UINT8 Bsp : 1;
+ UINT8 Reserved : 6;
+ } Flags;
+ struct {
+ UINT32 Stepping : 4;
+ UINT32 Model : 4;
+ UINT32 Family : 4;
+ UINT32 Reserved : 20;
+ } Signature;
+ struct {
+ UINT32 Fpu : 1;
+ UINT32 Reserved1 : 6;
+ UINT32 Mce : 1;
+ UINT32 Cx8 : 1;
+ UINT32 Apic : 1;
+ UINT32 Reserved2 : 22;
+ } Features;
+ UINT32 Reserved1;
+ UINT32 Reserved2;
+} EFI_LEGACY_MP_TABLE_ENTRY_PROCESSOR;
+
+//
+// Entry Type 1: Bus.
+//
+#define EFI_LEGACY_MP_TABLE_ENTRY_TYPE_BUS 0x01
+typedef struct {
+ UINT8 EntryType;
+ UINT8 Id;
+ CHAR8 TypeString[6];
+} EFI_LEGACY_MP_TABLE_ENTRY_BUS;
+
+#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_CBUS "CBUS " // Corollary CBus
+#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_CBUSII "CBUSII" // Corollary CBUS II
+#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_EISA "EISA " // Extended ISA
+#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_FUTURE "FUTURE" // IEEE FutureBus
+#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_INTERN "INTERN" // Internal bus
+#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_ISA "ISA " // Industry Standard Architecture
+#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_MBI "MBI " // Multibus I
+#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_MBII "MBII " // Multibus II
+#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_MCA "MCA " // Micro Channel Architecture
+#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_MPI "MPI " // MPI
+#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_MPSA "MPSA " // MPSA
+#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_NUBUS "NUBUS " // Apple Macintosh NuBus
+#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_PCI "PCI " // Peripheral Component Interconnect
+#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_PCMCIA "PCMCIA" // PC Memory Card International Assoc.
+#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_TC "TC " // DEC TurboChannel
+#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_VL "VL " // VESA Local Bus
+#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_VME "VME " // VMEbus
+#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_XPRESS "XPRESS" // Express System Bus
+//
+// Entry Type 2: I/O APIC.
+//
+#define EFI_LEGACY_MP_TABLE_ENTRY_TYPE_IOAPIC 0x02
+typedef struct {
+ UINT8 EntryType;
+ UINT8 Id;
+ UINT8 Ver;
+ struct {
+ UINT8 Enabled : 1;
+ UINT8 Reserved : 7;
+ } Flags;
+ UINT32 Address;
+} EFI_LEGACY_MP_TABLE_ENTRY_IOAPIC;
+
+//
+// Entry Type 3: I/O Interrupt Assignment.
+//
+#define EFI_LEGACY_MP_TABLE_ENTRY_TYPE_IO_INT 0x03
+typedef struct {
+ UINT8 EntryType;
+ UINT8 IntType;
+ struct {
+ UINT16 Polarity : 2;
+ UINT16 Trigger : 2;
+ UINT16 Reserved : 12;
+ } Flags;
+ UINT8 SourceBusId;
+ union {
+ struct {
+ UINT8 IntNo : 2;
+ UINT8 Dev : 5;
+ UINT8 Reserved : 1;
+ } fields;
+ UINT8 byte;
+ } SourceBusIrq;
+ UINT8 DestApicId;
+ UINT8 DestApicIntIn;
+} EFI_LEGACY_MP_TABLE_ENTRY_IO_INT;
+
+typedef enum {
+ EfiLegacyMpTableEntryIoIntTypeInt = 0,
+ EfiLegacyMpTableEntryIoIntTypeNmi = 1,
+ EfiLegacyMpTableEntryIoIntTypeSmi = 2,
+ EfiLegacyMpTableEntryIoIntTypeExtInt= 3,
+} EFI_LEGACY_MP_TABLE_ENTRY_IO_INT_TYPE;
+
+typedef enum {
+ EfiLegacyMpTableEntryIoIntFlagsPolaritySpec = 0x0,
+ EfiLegacyMpTableEntryIoIntFlagsPolarityActiveHigh = 0x1,
+ EfiLegacyMpTableEntryIoIntFlagsPolarityReserved = 0x2,
+ EfiLegacyMpTableEntryIoIntFlagsPolarityActiveLow = 0x3,
+} EFI_LEGACY_MP_TABLE_ENTRY_IO_INT_FLAGS_POLARITY;
+
+typedef enum {
+ EfiLegacyMpTableEntryIoIntFlagsTriggerSpec = 0x0,
+ EfiLegacyMpTableEntryIoIntFlagsTriggerEdge = 0x1,
+ EfiLegacyMpTableEntryIoIntFlagsTriggerReserved = 0x2,
+ EfiLegacyMpTableEntryIoIntFlagsTriggerLevel = 0x3,
+} EFI_LEGACY_MP_TABLE_ENTRY_IO_INT_FLAGS_TRIGGER;
+
+//
+// Entry Type 4: Local Interrupt Assignment.
+//
+#define EFI_LEGACY_MP_TABLE_ENTRY_TYPE_LOCAL_INT 0x04
+typedef struct {
+ UINT8 EntryType;
+ UINT8 IntType;
+ struct {
+ UINT16 Polarity : 2;
+ UINT16 Trigger : 2;
+ UINT16 Reserved : 12;
+ } Flags;
+ UINT8 SourceBusId;
+ UINT8 SourceBusIrq;
+ UINT8 DestApicId;
+ UINT8 DestApicIntIn;
+} EFI_LEGACY_MP_TABLE_ENTRY_LOCAL_INT;
+
+typedef enum {
+ EfiLegacyMpTableEntryLocalIntTypeInt = 0,
+ EfiLegacyMpTableEntryLocalIntTypeNmi = 1,
+ EfiLegacyMpTableEntryLocalIntTypeSmi = 2,
+ EfiLegacyMpTableEntryLocalIntTypeExtInt = 3,
+} EFI_LEGACY_MP_TABLE_ENTRY_LOCAL_INT_TYPE;
+
+typedef enum {
+ EfiLegacyMpTableEntryLocalIntFlagsPolaritySpec = 0x0,
+ EfiLegacyMpTableEntryLocalIntFlagsPolarityActiveHigh= 0x1,
+ EfiLegacyMpTableEntryLocalIntFlagsPolarityReserved = 0x2,
+ EfiLegacyMpTableEntryLocalIntFlagsPolarityActiveLow = 0x3,
+} EFI_LEGACY_MP_TABLE_ENTRY_LOCAL_INT_FLAGS_POLARITY;
+
+typedef enum {
+ EfiLegacyMpTableEntryLocalIntFlagsTriggerSpec = 0x0,
+ EfiLegacyMpTableEntryLocalIntFlagsTriggerEdge = 0x1,
+ EfiLegacyMpTableEntryLocalIntFlagsTriggerReserved = 0x2,
+ EfiLegacyMpTableEntryLocalIntFlagsTriggerLevel = 0x3,
+} EFI_LEGACY_MP_TABLE_ENTRY_LOCAL_INT_FLAGS_TRIGGER;
+
+//
+// Entry Type 128: System Address Space Mapping.
+//
+#define EFI_LEGACY_MP_TABLE_ENTRY_EXT_TYPE_SYS_ADDR_SPACE_MAPPING 0x80
+typedef struct {
+ UINT8 EntryType;
+ UINT8 Length;
+ UINT8 BusId;
+ UINT8 AddressType;
+ UINT64 AddressBase;
+ UINT64 AddressLength;
+} EFI_LEGACY_MP_TABLE_ENTRY_EXT_SYS_ADDR_SPACE_MAPPING;
+
+typedef enum {
+ EfiLegacyMpTableEntryExtSysAddrSpaceMappingIo = 0,
+ EfiLegacyMpTableEntryExtSysAddrSpaceMappingMemory = 1,
+ EfiLegacyMpTableEntryExtSysAddrSpaceMappingPrefetch = 2,
+} EFI_LEGACY_MP_TABLE_ENTRY_EXT_SYS_ADDR_SPACE_MAPPING_TYPE;
+
+//
+// Entry Type 129: Bus Hierarchy.
+//
+#define EFI_LEGACY_MP_TABLE_ENTRY_EXT_TYPE_BUS_HIERARCHY 0x81
+typedef struct {
+ UINT8 EntryType;
+ UINT8 Length;
+ UINT8 BusId;
+ struct {
+ UINT8 SubtractiveDecode : 1;
+ UINT8 Reserved : 7;
+ } BusInfo;
+ UINT8 ParentBus;
+ UINT8 Reserved1;
+ UINT8 Reserved2;
+ UINT8 Reserved3;
+} EFI_LEGACY_MP_TABLE_ENTRY_EXT_BUS_HIERARCHY;
+
+//
+// Entry Type 130: Compatibility Bus Address Space Modifier.
+//
+#define EFI_LEGACY_MP_TABLE_ENTRY_EXT_TYPE_COMPAT_BUS_ADDR_SPACE_MODIFIER 0x82
+typedef struct {
+ UINT8 EntryType;
+ UINT8 Length;
+ UINT8 BusId;
+ struct {
+ UINT8 RangeMode : 1;
+ UINT8 Reserved : 7;
+ } AddrMode;
+ UINT32 PredefinedRangeList;
+} EFI_LEGACY_MP_TABLE_ENTRY_EXT_COMPAT_BUS_ADDR_SPACE_MODIFIER;
+
+#pragma pack(pop)
+
+#endif
diff --git a/EdkCompatibilityPkg/Foundation/Include/IndustryStandard/MemoryMappedConfigurationSpaceAccessTable.h b/EdkCompatibilityPkg/Foundation/Include/IndustryStandard/MemoryMappedConfigurationSpaceAccessTable.h new file mode 100644 index 0000000000..5bbc05957e --- /dev/null +++ b/EdkCompatibilityPkg/Foundation/Include/IndustryStandard/MemoryMappedConfigurationSpaceAccessTable.h @@ -0,0 +1,56 @@ +/*++
+
+Copyright (c) 2007, Intel Corporation
+All rights reserved. This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution. The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+Module Name:
+
+ MemoryMappedConfigurationSpaceAccessTable.h
+
+Abstract:
+
+ ACPI memory mapped configuration space access table definition, defined at
+ in the PCI Firmware Specification, version 3.0.
+ Specification is available at http://www.pcisig.com.
+
+--*/
+
+#ifndef _MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_TABLE_H_
+#define _MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_TABLE_H_
+
+//
+// Include files
+//
+#include "AcpiCommon.h"
+
+//
+// Ensure proper structure formats
+//
+#pragma pack(1)
+//
+// Memory Mapped Configuration Space Access Table (MCFG)
+// This table is a basic description table header followed by
+// a number of base address allocation structures.
+//
+typedef struct {
+ UINT64 BaseAddress;
+ UINT16 PciSegmentGroupNumber;
+ UINT8 StartBusNumber;
+ UINT8 EndBusNumber;
+ UINT32 Reserved;
+} EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_SPACE_BASE_ADDRESS_ALLOCATION_STRUCTURE;
+
+//
+// MCFG Revision (defined in spec)
+//
+#define EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_TABLE_REVISION 0x01
+
+#pragma pack()
+
+#endif
diff --git a/EdkCompatibilityPkg/Foundation/Include/IndustryStandard/SdramSpd.h b/EdkCompatibilityPkg/Foundation/Include/IndustryStandard/SdramSpd.h new file mode 100644 index 0000000000..f8ca8485d4 --- /dev/null +++ b/EdkCompatibilityPkg/Foundation/Include/IndustryStandard/SdramSpd.h @@ -0,0 +1,73 @@ +/*++
+
+Copyright (c) 2007, Intel Corporation
+All rights reserved. This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution. The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+Module Name:
+
+ SdramSpd.h
+
+Abstract:
+
+ This file contains definitions for the SPD fields on an SDRAM.
+
+--*/
+
+#ifndef _SDRAM_SPD_H
+#define _SDRAM_SPD_H
+
+//
+// SDRAM SPD field definitions
+//
+#define SPD_MEMORY_TYPE 2
+#define SPD_SDRAM_ROW_ADDR 3
+#define SPD_SDRAM_COL_ADDR 4
+#define SPD_SDRAM_MODULE_ROWS 5
+#define SPD_SDRAM_MODULE_DATA_WIDTH_LSB 6
+#define SPD_SDRAM_MODULE_DATA_WIDTH_MSB 7
+#define SPD_SDRAM_ECC_SUPPORT 11
+#define SPD_SDRAM_REFRESH 12
+#define SPD_SDRAM_WIDTH 13
+#define SPD_SDRAM_ERROR_WIDTH 14
+#define SPD_SDRAM_BURST_LENGTH 16
+#define SPD_SDRAM_NO_OF_BANKS 17
+#define SPD_SDRAM_CAS_LATENCY 18
+#define SPD_SDRAM_MODULE_ATTR 21
+
+#define SPD_SDRAM_TCLK1_PULSE 9 // cycle time for highest cas latency
+#define SPD_SDRAM_TAC1_PULSE 10 // access time for highest cas latency
+#define SPD_SDRAM_TCLK2_PULSE 23 // cycle time for 2nd highest cas latency
+#define SPD_SDRAM_TAC2_PULSE 24 // access time for 2nd highest cas latency
+#define SPD_SDRAM_TCLK3_PULSE 25 // cycle time for 3rd highest cas latency
+#define SPD_SDRAM_TAC3_PULSE 26 // access time for 3rd highest cas latency
+#define SPD_SDRAM_MIN_PRECHARGE 27
+#define SPD_SDRAM_ACTIVE_MIN 28
+#define SPD_SDRAM_RAS_CAS 29
+#define SPD_SDRAM_RAS_PULSE 30
+#define SPD_SDRAM_DENSITY 31
+
+//
+// Memory Type Definitions
+//
+#define SPD_VAL_SDR_TYPE 4 // SDR SDRAM memory
+#define SPD_VAL_DDR_TYPE 7 // DDR SDRAM memory
+#define SPD_VAL_DDR2_TYPE 8 // DDR2 SDRAM memory
+//
+// ECC Type Definitions
+//
+#define SPD_ECC_TYPE_NONE 0x00 // No error checking
+#define SPD_ECC_TYPE_PARITY 0x01 // No error checking
+#define SPD_ECC_TYPE_ECC 0x02 // Error checking only
+//
+// Module Attributes (Bit positions)
+//
+#define SPD_BUFFERED 0x01
+#define SPD_REGISTERED 0x02
+
+#endif
diff --git a/EdkCompatibilityPkg/Foundation/Include/IndustryStandard/ServerProcessorManagementInterfaceTable.h b/EdkCompatibilityPkg/Foundation/Include/IndustryStandard/ServerProcessorManagementInterfaceTable.h new file mode 100644 index 0000000000..2c2a925e60 --- /dev/null +++ b/EdkCompatibilityPkg/Foundation/Include/IndustryStandard/ServerProcessorManagementInterfaceTable.h @@ -0,0 +1,80 @@ +/*++
+
+Copyright (c) 2007, Intel Corporation
+All rights reserved. This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution. The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+Module Name:
+
+ ServerProcessorManagementInterfaceTable.h
+
+Abstract:
+
+ ACPI Server Processor Management Interface Table SPMI as described
+ in the IPMI2.0 Specification Revistion 1.5
+
+--*/
+
+#ifndef _SERVER_PROCESSOR_MANAGEMENT_INTERFACE_TABLE_H_
+#define _SERVER_PROCESSOR_MANAGEMENT_INTERFACE_TABLE_H_
+
+#include "Acpi2_0.h"
+
+//
+// Ensure proper structure formats
+//
+#pragma pack (1)
+
+//
+// Server Processor Management Interface Table definition.
+//
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT8 Reserved_36;
+ UINT8 InterfaceType;
+ UINT16 SpecificationRevision;
+ UINT8 InterruptType;
+ UINT8 GPE;
+ UINT8 Reserved_42;
+ UINT8 PCIDeviceFlag;
+ UINT32 GlobalSystemInterrupt;
+ EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE BaseAddress;
+ UINT8 PCISegmentGroup_UID1;
+ UINT8 PCIBusNumber_UID2;
+ UINT8 PCIDeviceNumber_UID3;
+ UINT8 PCIFunctionNumber_UID4;
+} EFI_ACPI_SERVER_PROCESSOR_MANAGEMENT_INTERFACE_DESCRIPTION_TABLE;
+
+#pragma pack ()
+
+//
+// SPMI Revision
+//
+#define EFI_ACPI_SERVER_PROCESSOR_MANAGEMENT_INTERFACE_TABLE_REVISION 0x05
+
+//
+// Interface Type
+//
+#define EFI_ACPI_SPMI_INTERFACE_TYPE_RESERVED 0
+#define EFI_ACPI_SPMI_INTERFACE_TYPE_KCS 1
+#define EFI_ACPI_SPMI_INTERFACE_TYPE_SMIC 2
+#define EFI_ACPI_SPMI_INTERFACE_TYPE_BT 3
+#define EFI_ACPI_SPMI_INTERFACE_TYPE_SSIF 4
+
+//
+// SPMI Specfication Revision
+//
+#define EFI_ACPI_SPMI_SPECIFICATION_REVISION 0x0150
+
+//
+// SPMI Interrupt Type
+//
+#define EFI_ACPI_SPMI_INTERRUPT_TYPE_SCI 0x1
+#define EFI_ACPI_SPMI_INTERRUPT_TYPE_IOAPIC 0x2
+
+#endif
diff --git a/EdkCompatibilityPkg/Foundation/Include/IndustryStandard/Smbios.h b/EdkCompatibilityPkg/Foundation/Include/IndustryStandard/Smbios.h new file mode 100644 index 0000000000..10ef37ddf7 --- /dev/null +++ b/EdkCompatibilityPkg/Foundation/Include/IndustryStandard/Smbios.h @@ -0,0 +1,576 @@ +/*++
+
+Copyright (c) 2007, Intel Corporation
+All rights reserved. This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution. The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+Module Name:
+
+ Smbios.h
+
+Abstract:
+
+--*/
+
+#ifndef _SMBIOS_TABLE_H_
+#define _SMBIOS_TABLE_H_
+
+#include "Tiano.h"
+
+#pragma pack(1)
+
+typedef UINT8 SMBIOS_TABLE_STRING;
+
+typedef struct {
+ UINT8 AnchorString[4];
+ UINT8 EntryPointStructureChecksum;
+ UINT8 EntryPointLength;
+ UINT8 MajorVersion;
+ UINT8 MinorVersion;
+ UINT16 MaxStructureSize;
+ UINT8 EntryPointRevision;
+ UINT8 FormattedArea[5];
+ UINT8 IntermediateAnchorString[5];
+ UINT8 IntermediateChecksum;
+ UINT16 TableLength;
+ UINT32 TableAddress;
+ UINT16 NumberOfSmbiosStructures;
+ UINT8 SmbiosBcdRevision;
+} SMBIOS_TABLE_STRUCTURE;
+
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Handle;
+} SMBIOS_TABLE_HEADER;
+
+typedef struct {
+ SMBIOS_TABLE_HEADER Hdr;
+ SMBIOS_TABLE_STRING Vendor;
+ SMBIOS_TABLE_STRING BiosVersion;
+ UINT16 BiosSegment;
+ SMBIOS_TABLE_STRING BiosReleaseDate;
+ UINT8 BiosSize;
+ UINT64 BiosCharacteristics;
+ UINT8 BIOSCharacteristicsExtensionBytes[2];
+ UINT8 SystemBiosMajorRelease;
+ UINT8 SystemBiosMinorRelease;
+ UINT8 EmbeddedControllerFirmwareMajorRelease;
+ UINT8 EmbeddedControllerFirmwareMinorRelease;
+} SMBIOS_TABLE_TYPE0;
+
+typedef struct {
+ SMBIOS_TABLE_HEADER Hdr;
+ SMBIOS_TABLE_STRING Manufacturer;
+ SMBIOS_TABLE_STRING ProductName;
+ SMBIOS_TABLE_STRING Version;
+ SMBIOS_TABLE_STRING SerialNumber;
+ EFI_GUID Uuid;
+ UINT8 WakeUpType;
+ SMBIOS_TABLE_STRING SKUNumber;
+ SMBIOS_TABLE_STRING Family;
+} SMBIOS_TABLE_TYPE1;
+
+typedef struct {
+ SMBIOS_TABLE_HEADER Hdr;
+ SMBIOS_TABLE_STRING Manufacturer;
+ SMBIOS_TABLE_STRING ProductName;
+ SMBIOS_TABLE_STRING Version;
+ SMBIOS_TABLE_STRING SerialNumber;
+ SMBIOS_TABLE_STRING AssetTag;
+ UINT8 FeatureFlag;
+ SMBIOS_TABLE_STRING LocationInChassis;
+ UINT16 ChassisHandle;
+ UINT8 BoardType;
+ UINT8 NumberOfContainedObjectHandles;
+ UINT16 ContainedObjectHandles[1];
+} SMBIOS_TABLE_TYPE2;
+
+typedef struct {
+ UINT8 ContainedElementType;
+ UINT8 ContainedElementMinimum;
+ UINT8 ContainedElementMaximum;
+} CONTAINED_ELEMENT;
+
+typedef struct {
+ SMBIOS_TABLE_HEADER Hdr;
+ SMBIOS_TABLE_STRING Manufacturer;
+ UINT8 Type;
+ SMBIOS_TABLE_STRING Version;
+ SMBIOS_TABLE_STRING SerialNumber;
+ SMBIOS_TABLE_STRING AssetTag;
+ UINT8 BootupState;
+ UINT8 PowerSupplyState;
+ UINT8 ThermalState;
+ UINT8 SecurityStatus;
+ UINT8 OemDefined[4];
+ UINT8 Height;
+ UINT8 NumberofPowerCords;
+ UINT8 ContainedElementCount;
+ UINT8 ContainedElementRecordLength;
+ CONTAINED_ELEMENT ContainedElements[1];
+} SMBIOS_TABLE_TYPE3;
+
+typedef struct {
+ SMBIOS_TABLE_HEADER Hdr;
+ UINT8 Socket;
+ UINT8 ProcessorType;
+ UINT8 ProcessorFamily;
+ SMBIOS_TABLE_STRING ProcessorManufacture;
+ UINT8 ProcessorId[8];
+ SMBIOS_TABLE_STRING ProcessorVersion;
+ UINT8 Voltage;
+ UINT16 ExternalClock;
+ UINT16 MaxSpeed;
+ UINT16 CurrentSpeed;
+ UINT8 Status;
+ UINT8 ProcessorUpgrade;
+ UINT16 L1CacheHandle;
+ UINT16 L2CacheHandle;
+ UINT16 L3CacheHandle;
+ SMBIOS_TABLE_STRING SerialNumber;
+ SMBIOS_TABLE_STRING AssetTag;
+ SMBIOS_TABLE_STRING PartNumber;
+} SMBIOS_TABLE_TYPE4;
+
+typedef struct {
+ SMBIOS_TABLE_HEADER Hdr;
+ UINT8 ErrDetectMethod;
+ UINT8 ErrCorrectCapability;
+ UINT8 SupportInterleave;
+ UINT8 CurrentInterleave;
+ UINT8 MaxMemoryModuleSize;
+ UINT16 SupportSpeed;
+ UINT16 SupportMemoryType;
+ UINT8 MemoryModuleVoltage;
+ UINT8 AssociatedMemorySlotNum;
+ UINT16 MemoryModuleConfigHandles[1];
+// UINT8 EnableErrCorrectCapabilities;
+} SMBIOS_TABLE_TYPE5;
+
+typedef struct {
+ SMBIOS_TABLE_HEADER Hdr;
+ SMBIOS_TABLE_STRING SocketDesignation;
+ UINT8 BankConnections;
+ UINT8 CurrentSpeed;
+ UINT16 CurrentMemoryType;
+ UINT8 InstalledSize;
+ UINT8 EnabledSize;
+ UINT8 ErrorStatus;
+} SMBIOS_TABLE_TYPE6;
+
+typedef struct {
+ SMBIOS_TABLE_HEADER Hdr;
+ SMBIOS_TABLE_STRING SocketDesignation;
+ UINT16 CacheConfiguration;
+ UINT16 MaximumCacheSize;
+ UINT16 InstalledSize;
+ UINT16 SupportedSRAMType;
+ UINT16 CurrentSRAMType;
+ UINT8 CacheSpeed;
+ UINT8 ErrorCorrectionType;
+ UINT8 SystemCacheType;
+ UINT8 Associativity;
+} SMBIOS_TABLE_TYPE7;
+
+typedef struct {
+ SMBIOS_TABLE_HEADER Hdr;
+ SMBIOS_TABLE_STRING InternalReferenceDesignator;
+ UINT8 InternalConnectorType;
+ SMBIOS_TABLE_STRING ExternalReferenceDesignator;
+ UINT8 ExternalConnectorType;
+ UINT8 PortType;
+} SMBIOS_TABLE_TYPE8;
+
+typedef struct {
+ SMBIOS_TABLE_HEADER Hdr;
+ SMBIOS_TABLE_STRING SlotDesignation;
+ UINT8 SlotType;
+ UINT8 SlotDataBusWidth;
+ UINT8 CurrentUsage;
+ UINT8 SlotLength;
+ UINT16 SlotID;
+ UINT8 SlotCharacteristics1;
+ UINT8 SlotCharacteristics2;
+} SMBIOS_TABLE_TYPE9;
+
+typedef struct {
+ UINT8 DeviceType;
+ SMBIOS_TABLE_STRING DescriptionString;
+} DEVICE_STRUCT;
+
+typedef struct {
+ SMBIOS_TABLE_HEADER Hdr;
+ DEVICE_STRUCT Device[1];
+} SMBIOS_TABLE_TYPE10;
+
+typedef struct {
+ SMBIOS_TABLE_HEADER Hdr;
+ UINT8 StringCount;
+} SMBIOS_TABLE_TYPE11;
+
+typedef struct {
+ SMBIOS_TABLE_HEADER Hdr;
+ UINT8 StringCount;
+} SMBIOS_TABLE_TYPE12;
+
+typedef struct {
+ SMBIOS_TABLE_HEADER Hdr;
+ UINT8 InstallableLanguages;
+ UINT8 Flags;
+ UINT8 reserved[15];
+ SMBIOS_TABLE_STRING CurrentLanguages;
+} SMBIOS_TABLE_TYPE13;
+
+typedef struct {
+ UINT8 ItemType;
+ UINT16 ItemHandle;
+} GROUP_STRUCT;
+
+typedef struct {
+ SMBIOS_TABLE_HEADER Hdr;
+ SMBIOS_TABLE_STRING GroupName;
+ GROUP_STRUCT Group[1];
+} SMBIOS_TABLE_TYPE14;
+
+typedef struct {
+ UINT8 LogType;
+ UINT8 DataFormatType;
+} EVENT_LOG_TYPE;
+
+typedef struct {
+ SMBIOS_TABLE_HEADER Hdr;
+ UINT16 LogAreaLength;
+ UINT16 LogHeaderStartOffset;
+ UINT16 LogDataStartOffset;
+ UINT8 AccessMethod;
+ UINT8 LogStatus;
+ UINT32 LogChangeToken;
+ UINT32 AccessMethodAddress;
+ UINT8 LogHeaderFormat;
+ UINT8 NumberOfSupportedLogTypeDescriptors;
+ UINT8 LengthOfLogTypeDescriptor;
+ EVENT_LOG_TYPE EventLogTypeDescriptors[1];
+} SMBIOS_TABLE_TYPE15;
+
+typedef struct {
+ SMBIOS_TABLE_HEADER Hdr;
+ UINT8 Location;
+ UINT8 Use;
+ UINT8 MemoryErrorCorrection;
+ UINT32 MaximumCapacity;
+ UINT16 MemoryErrorInformationHandle;
+ UINT16 NumberOfMemoryDevices;
+} SMBIOS_TABLE_TYPE16;
+
+typedef struct {
+ SMBIOS_TABLE_HEADER Hdr;
+ UINT16 MemoryArrayHandle;
+ UINT16 MemoryErrorInformationHandle;
+ UINT16 TotalWidth;
+ UINT16 DataWidth;
+ UINT16 Size;
+ UINT8 FormFactor;
+ UINT8 DeviceSet;
+ SMBIOS_TABLE_STRING DeviceLocator;
+ SMBIOS_TABLE_STRING BankLocator;
+ UINT8 MemoryType;
+ UINT16 TypeDetail;
+ UINT16 Speed;
+ SMBIOS_TABLE_STRING Manufacturer;
+ SMBIOS_TABLE_STRING SerialNumber;
+ SMBIOS_TABLE_STRING AssetTag;
+ SMBIOS_TABLE_STRING PartNumber;
+} SMBIOS_TABLE_TYPE17;
+
+typedef struct {
+ SMBIOS_TABLE_HEADER Hdr;
+ UINT8 ErrorType;
+ UINT8 ErrorGranularity;
+ UINT8 ErrorOperation;
+ UINT32 VendorSyndrome;
+ UINT32 MemoryArrayErrorAddress;
+ UINT32 DeviceErrorAddress;
+ UINT32 ErrorResolution;
+} SMBIOS_TABLE_TYPE18;
+
+typedef struct {
+ SMBIOS_TABLE_HEADER Hdr;
+ UINT32 StartingAddress;
+ UINT32 EndingAddress;
+ UINT16 MemoryArrayHandle;
+ UINT8 PartitionWidth;
+} SMBIOS_TABLE_TYPE19;
+
+typedef struct {
+ SMBIOS_TABLE_HEADER Hdr;
+ UINT32 StartingAddress;
+ UINT32 EndingAddress;
+ UINT16 MemoryDeviceHandle;
+ UINT16 MemoryArrayMappedAddressHandle;
+ UINT8 PartitionRowPosition;
+ UINT8 InterleavePosition;
+ UINT8 InterleavedDataDepth;
+} SMBIOS_TABLE_TYPE20;
+
+typedef struct {
+ SMBIOS_TABLE_HEADER Hdr;
+ UINT8 Type;
+ UINT8 Interface;
+ UINT8 NumberOfButtons;
+} SMBIOS_TABLE_TYPE21;
+
+typedef struct {
+ SMBIOS_TABLE_HEADER Hdr;
+ SMBIOS_TABLE_STRING Location;
+ SMBIOS_TABLE_STRING Manufacturer;
+ SMBIOS_TABLE_STRING ManufactureDate;
+ SMBIOS_TABLE_STRING SerialNumber;
+ SMBIOS_TABLE_STRING DeviceName;
+ UINT8 DeviceChemistry;
+ UINT16 DeviceCapacity;
+ UINT16 DesignVoltage;
+ SMBIOS_TABLE_STRING SBDSVersionNumber;
+ UINT8 MaximumErrorInBatteryData;
+ UINT16 SBDSSerialNumber;
+ UINT16 SBDSManufactureDate;
+ SMBIOS_TABLE_STRING SBDSDeviceChemistry;
+ UINT8 DesignCapacityMultiplier;
+ UINT32 OEMSpecific;
+} SMBIOS_TABLE_TYPE22;
+
+typedef struct {
+ SMBIOS_TABLE_HEADER Hdr;
+ UINT8 Capabilities;
+ UINT16 ResetCount;
+ UINT16 ResetLimit;
+ UINT16 TimerInterval;
+ UINT16 Timeout;
+} SMBIOS_TABLE_TYPE23;
+
+typedef struct {
+ SMBIOS_TABLE_HEADER Hdr;
+ UINT8 HardwareSecuritySettings;
+} SMBIOS_TABLE_TYPE24;
+
+typedef struct {
+ SMBIOS_TABLE_HEADER Hdr;
+ UINT8 NextScheduledPowerOnMonth;
+ UINT8 NextScheduledPowerOnDayOfMonth;
+ UINT8 NextScheduledPowerOnHour;
+ UINT8 NextScheduledPowerOnMinute;
+ UINT8 NextScheduledPowerOnSecond;
+} SMBIOS_TABLE_TYPE25;
+
+typedef struct {
+ SMBIOS_TABLE_HEADER Hdr;
+ SMBIOS_TABLE_STRING Description;
+ UINT8 LocationAndStatus;
+ UINT16 MaximumValue;
+ UINT16 MinimumValue;
+ UINT16 Resolution;
+ UINT16 Tolerance;
+ UINT16 Accuracy;
+ UINT32 OEMDefined;
+ UINT16 NominalValue;
+} SMBIOS_TABLE_TYPE26;
+
+typedef struct {
+ SMBIOS_TABLE_HEADER Hdr;
+ UINT16 TemperatureProbeHandle;
+ UINT8 DeviceTypeAndStatus;
+ UINT8 CoolingUnitGroup;
+ UINT32 OEMDefined;
+ UINT16 NominalSpeed;
+} SMBIOS_TABLE_TYPE27;
+
+typedef struct {
+ SMBIOS_TABLE_HEADER Hdr;
+ SMBIOS_TABLE_STRING Description;
+ UINT8 LocationAndStatus;
+ UINT16 MaximumValue;
+ UINT16 MinimumValue;
+ UINT16 Resolution;
+ UINT16 Tolerance;
+ UINT16 Accuracy;
+ UINT32 OEMDefined;
+ UINT16 NominalValue;
+} SMBIOS_TABLE_TYPE28;
+
+typedef struct {
+ SMBIOS_TABLE_HEADER Hdr;
+ SMBIOS_TABLE_STRING Description;
+ UINT8 LocationAndStatus;
+ UINT16 MaximumValue;
+ UINT16 MinimumValue;
+ UINT16 Resolution;
+ UINT16 Tolerance;
+ UINT16 Accuracy;
+ UINT32 OEMDefined;
+ UINT16 NominalValue;
+} SMBIOS_TABLE_TYPE29;
+
+typedef struct {
+ SMBIOS_TABLE_HEADER Hdr;
+ SMBIOS_TABLE_STRING ManufacturerName;
+ UINT8 Connections;
+} SMBIOS_TABLE_TYPE30;
+
+typedef struct {
+ SMBIOS_TABLE_HEADER Hdr;
+ UINT8 Checksum;
+ UINT8 Reserved1;
+ UINT16 Reserved2;
+ UINT32 BisEntry16;
+ UINT32 BisEntry32;
+ UINT64 Reserved3;
+ UINT32 Reserved4;
+} SMBIOS_TABLE_TYPE31;
+
+typedef struct {
+ SMBIOS_TABLE_HEADER Hdr;
+ UINT8 Reserved[6];
+ UINT8 BootStatus[1];
+} SMBIOS_TABLE_TYPE32;
+
+typedef struct {
+ SMBIOS_TABLE_HEADER Hdr;
+ UINT8 ErrorType;
+ UINT8 ErrorGranularity;
+ UINT8 ErrorOperation;
+ UINT32 VendorSyndrome;
+ UINT64 MemoryArrayErrorAddress;
+ UINT64 DeviceErrorAddress;
+ UINT32 ErrorResolution;
+} SMBIOS_TABLE_TYPE33;
+
+typedef struct {
+ SMBIOS_TABLE_HEADER Hdr;
+ SMBIOS_TABLE_STRING Description;
+ UINT8 Type;
+ UINT32 Address;
+ UINT8 AddressType;
+} SMBIOS_TABLE_TYPE34;
+
+typedef struct {
+ SMBIOS_TABLE_HEADER Hdr;
+ SMBIOS_TABLE_STRING Description;
+ UINT16 ManagementDeviceHandle;
+ UINT16 ComponentHandle;
+ UINT16 ThresholdHandle;
+} SMBIOS_TABLE_TYPE35;
+
+typedef struct {
+ SMBIOS_TABLE_HEADER Hdr;
+ UINT16 LowerThresholdNonCritical;
+ UINT16 UpperThresholdNonCritical;
+ UINT16 LowerThresholdCritical;
+ UINT16 UpperThresholdCritical;
+ UINT16 LowerThresholdNonRecoverable;
+ UINT16 UpperThresholdNonRecoverable;
+} SMBIOS_TABLE_TYPE36;
+
+typedef struct {
+ UINT8 DeviceLoad;
+ UINT16 DeviceHandle;
+} MEMORY_DEVICE;
+
+typedef struct {
+ SMBIOS_TABLE_HEADER Hdr;
+ UINT8 ChannelType;
+ UINT8 MaximumChannelLoad;
+ UINT8 MemoryDeviceCount;
+ MEMORY_DEVICE MemoryDevice[1];
+} SMBIOS_TABLE_TYPE37;
+
+typedef struct {
+ SMBIOS_TABLE_HEADER Hdr;
+ UINT8 InterfaceType;
+ UINT8 IPMISpecificationRevision;
+ UINT8 I2CSlaveAddress;
+ UINT8 NVStorageDeviceAddress;
+ UINT64 BaseAddress;
+ UINT8 BaseAddressModifier_InterruptInfo;
+ UINT8 InterruptNumber;
+} SMBIOS_TABLE_TYPE38;
+
+typedef struct {
+ SMBIOS_TABLE_HEADER Hdr;
+ UINT8 PowerUnitGroup;
+ SMBIOS_TABLE_STRING Location;
+ SMBIOS_TABLE_STRING DeviceName;
+ SMBIOS_TABLE_STRING Manufacturer;
+ SMBIOS_TABLE_STRING SerialNumber;
+ SMBIOS_TABLE_STRING AssetTagNumber;
+ SMBIOS_TABLE_STRING ModelPartNumber;
+ SMBIOS_TABLE_STRING RevisionLevel;
+ UINT16 MaxPowerCapacity;
+ UINT16 PowerSupplyCharacteristics;
+ UINT16 InputVoltageProbeHandle;
+ UINT16 CoolingDeviceHandle;
+ UINT16 InputCurrentProbeHandle;
+} SMBIOS_TABLE_TYPE39;
+
+typedef struct {
+ SMBIOS_TABLE_HEADER Hdr;
+} SMBIOS_TABLE_TYPE126;
+
+typedef struct {
+ SMBIOS_TABLE_HEADER Hdr;
+} SMBIOS_TABLE_TYPE127;
+
+typedef union {
+ SMBIOS_TABLE_HEADER *Hdr;
+ SMBIOS_TABLE_TYPE0 *Type0;
+ SMBIOS_TABLE_TYPE1 *Type1;
+ SMBIOS_TABLE_TYPE2 *Type2;
+ SMBIOS_TABLE_TYPE3 *Type3;
+ SMBIOS_TABLE_TYPE4 *Type4;
+ SMBIOS_TABLE_TYPE5 *Type5;
+ SMBIOS_TABLE_TYPE6 *Type6;
+ SMBIOS_TABLE_TYPE7 *Type7;
+ SMBIOS_TABLE_TYPE8 *Type8;
+ SMBIOS_TABLE_TYPE9 *Type9;
+ SMBIOS_TABLE_TYPE10 *Type10;
+ SMBIOS_TABLE_TYPE11 *Type11;
+ SMBIOS_TABLE_TYPE12 *Type12;
+ SMBIOS_TABLE_TYPE13 *Type13;
+ SMBIOS_TABLE_TYPE14 *Type14;
+ SMBIOS_TABLE_TYPE15 *Type15;
+ SMBIOS_TABLE_TYPE16 *Type16;
+ SMBIOS_TABLE_TYPE17 *Type17;
+ SMBIOS_TABLE_TYPE18 *Type18;
+ SMBIOS_TABLE_TYPE19 *Type19;
+ SMBIOS_TABLE_TYPE20 *Type20;
+ SMBIOS_TABLE_TYPE21 *Type21;
+ SMBIOS_TABLE_TYPE22 *Type22;
+ SMBIOS_TABLE_TYPE23 *Type23;
+ SMBIOS_TABLE_TYPE24 *Type24;
+ SMBIOS_TABLE_TYPE25 *Type25;
+ SMBIOS_TABLE_TYPE26 *Type26;
+ SMBIOS_TABLE_TYPE27 *Type27;
+ SMBIOS_TABLE_TYPE28 *Type28;
+ SMBIOS_TABLE_TYPE29 *Type29;
+ SMBIOS_TABLE_TYPE30 *Type30;
+ SMBIOS_TABLE_TYPE31 *Type31;
+ SMBIOS_TABLE_TYPE32 *Type32;
+ SMBIOS_TABLE_TYPE33 *Type33;
+ SMBIOS_TABLE_TYPE34 *Type34;
+ SMBIOS_TABLE_TYPE35 *Type35;
+ SMBIOS_TABLE_TYPE36 *Type36;
+ SMBIOS_TABLE_TYPE37 *Type37;
+ SMBIOS_TABLE_TYPE38 *Type38;
+ SMBIOS_TABLE_TYPE39 *Type39;
+ SMBIOS_TABLE_TYPE126 *Type126;
+ SMBIOS_TABLE_TYPE127 *Type127;
+ UINT8 *Raw;
+} SMBIOS_STRUCTURE_POINTER;
+
+#pragma pack()
+
+#endif
diff --git a/EdkCompatibilityPkg/Foundation/Include/IndustryStandard/Tpm12.h b/EdkCompatibilityPkg/Foundation/Include/IndustryStandard/Tpm12.h new file mode 100644 index 0000000000..077498a51d --- /dev/null +++ b/EdkCompatibilityPkg/Foundation/Include/IndustryStandard/Tpm12.h @@ -0,0 +1,1847 @@ +/*++
+
+Copyright (c) 2005 - 2006, Intel Corporation
+All rights reserved. This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution. The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+Module Name:
+
+ Tpm12.h
+
+Abstract:
+
+ TPM Specification data structures (TCG TPM Specification Version 1.2 Revision 94)
+
+ See http://trustedcomputinggroup.org for latest specification updates
+
+--*/
+
+#ifndef _TPM12_H_
+#define _TPM12_H_
+
+//
+// Structures are all packed on 1-byte alignment
+//
+
+#pragma pack (push)
+#pragma pack (1)
+
+//
+// Part 2, section 2.2: Basic types & Helper redefinitions
+//
+typedef UINT8 TPM_AUTH_DATA_USAGE;
+typedef UINT8 TPM_PAYLOAD_TYPE;
+typedef UINT8 TPM_VERSION_BYTE;
+typedef UINT16 TPM_TAG;
+typedef UINT16 TPM_PROTOCOL_ID;
+typedef UINT16 TPM_STARTUP_TYPE;
+typedef UINT16 TPM_ENC_SCHEME;
+typedef UINT16 TPM_SIG_SCHEME;
+typedef UINT16 TPM_MIGRATE_SCHEME;
+typedef UINT16 TPM_PHYSICAL_PRESENCE;
+typedef UINT16 TPM_ENTITY_TYPE;
+typedef UINT16 TPM_KEY_USAGE;
+typedef UINT16 TPM_EK_TYPE;
+typedef UINT16 TPM_STRUCTURE_TAG;
+typedef UINT16 TPM_PLATFORM_SPECIFIC;
+typedef UINT32 TPM_COMMAND_CODE;
+typedef UINT32 TPM_CAPABILITY_AREA;
+typedef UINT32 TPM_KEY_FLAGS;
+typedef UINT32 TPM_ALGORITHM_ID;
+typedef UINT32 TPM_MODIFIER_INDICATOR;
+typedef UINT32 TPM_ACTUAL_COUNT;
+typedef UINT32 TPM_TRANSPORT_ATTRIBUTES;
+typedef UINT32 TPM_AUTHHANDLE;
+typedef UINT32 TPM_DIRINDEX;
+typedef UINT32 TPM_KEY_HANDLE;
+typedef UINT32 TPM_PCRINDEX;
+typedef UINT32 TPM_RESULT;
+typedef UINT32 TPM_RESOURCE_TYPE;
+typedef UINT32 TPM_KEY_CONTROL;
+typedef UINT32 TPM_NV_INDEX;
+typedef UINT32 TPM_FAMILY_ID;
+typedef UINT32 TPM_FAMILY_VERIFICATION;
+typedef UINT32 TPM_STARTUP_EFFECTS;
+typedef UINT32 TPM_SYM_MODE;
+typedef UINT32 TPM_FAMILY_FLAGS;
+typedef UINT32 TPM_DELEGATE_INDEX;
+typedef UINT32 TPM_CMK_DELEGATE;
+typedef UINT32 TPM_COUNT_ID;
+typedef UINT32 TPM_REDIT_COMMAND;
+typedef UINT32 TPM_TRANSHANDLE;
+typedef UINT32 TPM_HANDLE;
+typedef UINT32 TPM_FAMILY_OPERATION;
+
+//
+// Part 2, section 2.2.4: Vendor specific
+// The following defines allow for the quick specification of a
+// vendor specific item.
+//
+#define TPM_Vendor_Specific32 ((UINT32) 0x00000400)
+#define TPM_Vendor_Specific8 ((UINT8) 0x80)
+
+//
+// Part 2, section 3.1: Structure TAGs
+//
+#define TPM_TAG_CONTEXTBLOB ((TPM_STRUCTURE_TAG) 0x0001)
+#define TPM_TAG_CONTEXT_SENSITIVE ((TPM_STRUCTURE_TAG) 0x0002)
+#define TPM_TAG_CONTEXTPOINTER ((TPM_STRUCTURE_TAG) 0x0003)
+#define TPM_TAG_CONTEXTLIST ((TPM_STRUCTURE_TAG) 0x0004)
+#define TPM_TAG_SIGNINFO ((TPM_STRUCTURE_TAG) 0x0005)
+#define TPM_TAG_PCR_INFO_LONG ((TPM_STRUCTURE_TAG) 0x0006)
+#define TPM_TAG_PERSISTENT_FLAGS ((TPM_STRUCTURE_TAG) 0x0007)
+#define TPM_TAG_VOLATILE_FLAGS ((TPM_STRUCTURE_TAG) 0x0008)
+#define TPM_TAG_PERSISTENT_DATA ((TPM_STRUCTURE_TAG) 0x0009)
+#define TPM_TAG_VOLATILE_DATA ((TPM_STRUCTURE_TAG) 0x000A)
+#define TPM_TAG_SV_DATA ((TPM_STRUCTURE_TAG) 0x000B)
+#define TPM_TAG_EK_BLOB ((TPM_STRUCTURE_TAG) 0x000C)
+#define TPM_TAG_EK_BLOB_AUTH ((TPM_STRUCTURE_TAG) 0x000D)
+#define TPM_TAG_COUNTER_VALUE ((TPM_STRUCTURE_TAG) 0x000E)
+#define TPM_TAG_TRANSPORT_INTERNAL ((TPM_STRUCTURE_TAG) 0x000F)
+#define TPM_TAG_TRANSPORT_LOG_IN ((TPM_STRUCTURE_TAG) 0x0010)
+#define TPM_TAG_TRANSPORT_LOG_OUT ((TPM_STRUCTURE_TAG) 0x0011)
+#define TPM_TAG_AUDIT_EVENT_IN ((TPM_STRUCTURE_TAG) 0x0012)
+#define TPM_TAG_AUDIT_EVENT_OUT ((TPM_STRUCTURE_TAG) 0x0013)
+#define TPM_TAG_CURRENT_TICKS ((TPM_STRUCTURE_TAG) 0x0014)
+#define TPM_TAG_KEY ((TPM_STRUCTURE_TAG) 0x0015)
+#define TPM_TAG_STORED_DATA12 ((TPM_STRUCTURE_TAG) 0x0016)
+#define TPM_TAG_NV_ATTRIBUTES ((TPM_STRUCTURE_TAG) 0x0017)
+#define TPM_TAG_NV_DATA_PUBLIC ((TPM_STRUCTURE_TAG) 0x0018)
+#define TPM_TAG_NV_DATA_SENSITIVE ((TPM_STRUCTURE_TAG) 0x0019)
+#define TPM_TAG_DELEGATIONS ((TPM_STRUCTURE_TAG) 0x001A)
+#define TPM_TAG_DELEGATE_PUBLIC ((TPM_STRUCTURE_TAG) 0x001B)
+#define TPM_TAG_DELEGATE_TABLE_ROW ((TPM_STRUCTURE_TAG) 0x001C)
+#define TPM_TAG_TRANSPORT_AUTH ((TPM_STRUCTURE_TAG) 0x001D)
+#define TPM_TAG_TRANSPORT_PUBLIC ((TPM_STRUCTURE_TAG) 0x001E)
+#define TPM_TAG_PERMANENT_FLAGS ((TPM_STRUCTURE_TAG) 0x001F)
+#define TPM_TAG_STCLEAR_FLAGS ((TPM_STRUCTURE_TAG) 0x0020)
+#define TPM_TAG_STANY_FLAGS ((TPM_STRUCTURE_TAG) 0x0021)
+#define TPM_TAG_PERMANENT_DATA ((TPM_STRUCTURE_TAG) 0x0022)
+#define TPM_TAG_STCLEAR_DATA ((TPM_STRUCTURE_TAG) 0x0023)
+#define TPM_TAG_STANY_DATA ((TPM_STRUCTURE_TAG) 0x0024)
+#define TPM_TAG_FAMILY_TABLE_ENTRY ((TPM_STRUCTURE_TAG) 0x0025)
+#define TPM_TAG_DELEGATE_SENSITIVE ((TPM_STRUCTURE_TAG) 0x0026)
+#define TPM_TAG_DELG_KEY_BLOB ((TPM_STRUCTURE_TAG) 0x0027)
+#define TPM_TAG_KEY12 ((TPM_STRUCTURE_TAG) 0x0028)
+#define TPM_TAG_CERTIFY_INFO2 ((TPM_STRUCTURE_TAG) 0x0029)
+#define TPM_TAG_DELEGATE_OWNER_BLOB ((TPM_STRUCTURE_TAG) 0x002A)
+#define TPM_TAG_EK_BLOB_ACTIVATE ((TPM_STRUCTURE_TAG) 0x002B)
+#define TPM_TAG_DAA_BLOB ((TPM_STRUCTURE_TAG) 0x002C)
+#define TPM_TAG_DAA_CONTEXT ((TPM_STRUCTURE_TAG) 0x002D)
+#define TPM_TAG_DAA_ENFORCE ((TPM_STRUCTURE_TAG) 0x002E)
+#define TPM_TAG_DAA_ISSUER ((TPM_STRUCTURE_TAG) 0x002F)
+#define TPM_TAG_CAP_VERSION_INFO ((TPM_STRUCTURE_TAG) 0x0030)
+#define TPM_TAG_DAA_SENSITIVE ((TPM_STRUCTURE_TAG) 0x0031)
+#define TPM_TAG_DAA_TPM ((TPM_STRUCTURE_TAG) 0x0032)
+#define TPM_TAG_CMK_MIGAUTH ((TPM_STRUCTURE_TAG) 0x0033)
+#define TPM_TAG_CMK_SIGTICKET ((TPM_STRUCTURE_TAG) 0x0034)
+#define TPM_TAG_CMK_MA_APPROVAL ((TPM_STRUCTURE_TAG) 0x0035)
+#define TPM_TAG_QUOTE_INFO2 ((TPM_STRUCTURE_TAG) 0x0036)
+
+//
+// Part 2, section 4: TPM Types
+//
+
+//
+// Part 2, section 4.1: TPM_RESOURCE_TYPE
+//
+#define TPM_RT_KEY ((TPM_RESOURCE_TYPE) 0x00000001) // The handle is a key handle and is the result of a LoadKey type operation
+#define TPM_RT_AUTH ((TPM_RESOURCE_TYPE) 0x00000002) // The handle is an authorization handle. Auth handles come from TPM_OIAP, TPM_OSAP and TPM_DSAP
+#define TPM_RT_HASH ((TPM_RESOURCE_TYPE) 0x00000003) // Reserved for hashes
+#define TPM_RT_TRANS ((TPM_RESOURCE_TYPE) 0x00000004) // The handle is for a transport session. Transport handles come from TPM_EstablishTransport
+#define TPM_RT_CONTEXT ((TPM_RESOURCE_TYPE) 0x00000005) // Resource wrapped and held outside the TPM using the context save/restore commands
+#define TPM_RT_COUNTER ((TPM_RESOURCE_TYPE) 0x00000006) // Reserved for counters
+#define TPM_RT_DELEGATE ((TPM_RESOURCE_TYPE) 0x00000007) // The handle is for a delegate row. These are the internal rows held in NV storage by the TPM
+#define TPM_RT_DAA_TPM ((TPM_RESOURCE_TYPE) 0x00000008) // The value is a DAA TPM specific blob
+#define TPM_RT_DAA_V0 ((TPM_RESOURCE_TYPE) 0x00000009) // The value is a DAA V0 parameter
+#define TPM_RT_DAA_V1 ((TPM_RESOURCE_TYPE) 0x0000000A) // The value is a DAA V1 parameter
+
+//
+// Part 2, section 4.2: TPM_PAYLOAD_TYPE
+//
+#define TPM_PT_ASYM ((TPM_PAYLOAD_TYPE) 0x01) // The entity is an asymmetric key
+#define TPM_PT_BIND ((TPM_PAYLOAD_TYPE) 0x02) // The entity is bound data
+#define TPM_PT_MIGRATE ((TPM_PAYLOAD_TYPE) 0x03) // The entity is a migration blob
+#define TPM_PT_MAINT ((TPM_PAYLOAD_TYPE) 0x04) // The entity is a maintenance blob
+#define TPM_PT_SEAL ((TPM_PAYLOAD_TYPE) 0x05) // The entity is sealed data
+#define TPM_PT_MIGRATE_RESTRICTED ((TPM_PAYLOAD_TYPE) 0x06) // The entity is a restricted-migration asymmetric key
+#define TPM_PT_MIGRATE_EXTERNAL ((TPM_PAYLOAD_TYPE) 0x07) // The entity is a external migratable key
+#define TPM_PT_CMK_MIGRATE ((TPM_PAYLOAD_TYPE) 0x08) // The entity is a CMK migratable blob
+#define TPM_PT_VENDOR_SPECIFIC ((TPM_PAYLOAD_TYPE) 0x80) // 0x80 - 0xFF Vendor specific payloads
+
+//
+// Part 2, section 4.3: TPM_ENTIRY_TYPE
+//
+#define TPM_ET_KEYHANDLE ((UINT16) 0x0001) // The entity is a keyHandle or key
+#define TPM_ET_OWNER ((UINT16) 0x0002) // The entity is the TPM Owner
+#define TPM_ET_DATA ((UINT16) 0x0003) // The entity is some data
+#define TPM_ET_SRK ((UINT16) 0x0004) // The entity is the SRK
+#define TPM_ET_KEY ((UINT16) 0x0005) // The entity is a key or keyHandle
+#define TPM_ET_REVOKE ((UINT16) 0x0006) // The entity is the RevokeTrust value
+#define TPM_ET_DEL_OWNER_BLOB ((UINT16) 0x0007) // The entity is a delegate owner blob
+#define TPM_ET_DEL_ROW ((UINT16) 0x0008) // The entity is a delegate row
+#define TPM_ET_DEL_KEY_BLOB ((UINT16) 0x0009) // The entity is a delegate key blob
+#define TPM_ET_COUNTER ((UINT16) 0x000A) // The entity is a counter
+#define TPM_ET_NV ((UINT16) 0x000B) // The entity is a NV index
+#define TPM_ET_RESERVED_HANDLE ((UINT16) 0x0040) // Reserved. This value avoids collisions with the handle MSB setting.
+//
+// TPM_ENTITY_TYPE MSB Values: The MSB is used to indicate the ADIP encryption sheme when applicable
+//
+#define TPM_ET_XOR ((UINT16) 0x0000) // ADIP encryption scheme: XOR
+#define TPM_ET_AES128 ((UINT16) 0x0006) // ADIP encryption scheme: AES 128 bits
+
+//
+// Part 2, section 4.4.1: Reserved Key Handles
+//
+#define TPM_KH_SRK ((TPM_KEY_HANDLE) 0x40000000) // The handle points to the SRK
+#define TPM_KH_OWNER ((TPM_KEY_HANDLE) 0x40000001) // The handle points to the TPM Owner
+#define TPM_KH_REVOKE ((TPM_KEY_HANDLE) 0x40000002) // The handle points to the RevokeTrust value
+#define TPM_KH_TRANSPORT ((TPM_KEY_HANDLE) 0x40000003) // The handle points to the EstablishTransport static authorization
+#define TPM_KH_OPERATOR ((TPM_KEY_HANDLE) 0x40000004) // The handle points to the Operator auth
+#define TPM_KH_ADMIN ((TPM_KEY_HANDLE) 0x40000005) // The handle points to the delegation administration auth
+#define TPM_KH_EK ((TPM_KEY_HANDLE) 0x40000006) // The handle points to the PUBEK, only usable with TPM_OwnerReadInternalPub
+
+//
+// Part 2, section 4.5: TPM_STARTUP_TYPE
+//
+#define TPM_ST_CLEAR ((TPM_STARTUP_TYPE) 0x0001) // The TPM is starting up from a clean state
+#define TPM_ST_STATE ((TPM_STARTUP_TYPE) 0x0002) // The TPM is starting up from a saved state
+#define TPM_ST_DEACTIVATED ((TPM_STARTUP_TYPE) 0x0003) // The TPM is to startup and set the deactivated flag to TRUE
+
+//
+// Part 2, section 4.6: TPM_STATUP_EFFECTS
+// The table makeup is still an open issue.
+//
+
+//
+// Part 2, section 4.7: TPM_PROTOCOL_ID
+//
+#define TPM_PID_OIAP ((TPM_PROTOCOL_ID) 0x0001) // The OIAP protocol.
+#define TPM_PID_OSAP ((TPM_PROTOCOL_ID) 0x0002) // The OSAP protocol.
+#define TPM_PID_ADIP ((TPM_PROTOCOL_ID) 0x0003) // The ADIP protocol.
+#define TPM_PID_ADCP ((TPM_PROTOCOL_ID) 0x0004) // The ADCP protocol.
+#define TPM_PID_OWNER ((TPM_PROTOCOL_ID) 0x0005) // The protocol for taking ownership of a TPM.
+#define TPM_PID_DSAP ((TPM_PROTOCOL_ID) 0x0006) // The DSAP protocol
+#define TPM_PID_TRANSPORT ((TPM_PROTOCOL_ID) 0x0007) // The transport protocol
+
+//
+// Part 2, section 4.8: TPM_ALGORITHM_ID
+// The TPM MUST support the algorithms TPM_ALG_RSA, TPM_ALG_SHA, TPM_ALG_HMAC,
+// TPM_ALG_MGF1
+//
+#define TPM_ALG_RSA ((TPM_ALGORITHM_ID) 0x00000001) // The RSA algorithm.
+#define TPM_ALG_DES ((TPM_ALGORITHM_ID) 0x00000002) // The DES algorithm
+#define TPM_ALG_3DES ((TPM_ALGORITHM_ID) 0x00000003) // The 3DES algorithm in EDE mode
+#define TPM_ALG_SHA ((TPM_ALGORITHM_ID) 0x00000004) // The SHA1 algorithm
+#define TPM_ALG_HMAC ((TPM_ALGORITHM_ID) 0x00000005) // The RFC 2104 HMAC algorithm
+#define TPM_ALG_AES128 ((TPM_ALGORITHM_ID) 0x00000006) // The AES algorithm, key size 128
+#define TPM_ALG_MGF1 ((TPM_ALGORITHM_ID) 0x00000007) // The XOR algorithm using MGF1 to create a string the size of the encrypted block
+#define TPM_ALG_AES192 ((TPM_ALGORITHM_ID) 0x00000008) // AES, key size 192
+#define TPM_ALG_AES256 ((TPM_ALGORITHM_ID) 0x00000009) // AES, key size 256
+#define TPM_ALG_XOR ((TPM_ALGORITHM_ID) 0x0000000A) // XOR using the rolling nonces
+
+//
+// Part 2, section 4.9: TPM_PHYSICAL_PRESENCE
+//
+#define TPM_PHYSICAL_PRESENCE_HW_DISABLE ((TPM_PHYSICAL_PRESENCE) 0x0200) // Sets the physicalPresenceHWEnable to FALSE
+#define TPM_PHYSICAL_PRESENCE_CMD_DISABLE ((TPM_PHYSICAL_PRESENCE) 0x0100) // Sets the physicalPresenceCMDEnable to FALSE
+#define TPM_PHYSICAL_PRESENCE_LIFETIME_LOCK ((TPM_PHYSICAL_PRESENCE) 0x0080) // Sets the physicalPresenceLifetimeLock to TRUE
+#define TPM_PHYSICAL_PRESENCE_HW_ENABLE ((TPM_PHYSICAL_PRESENCE) 0x0040) // Sets the physicalPresenceHWEnable to TRUE
+#define TPM_PHYSICAL_PRESENCE_CMD_ENABLE ((TPM_PHYSICAL_PRESENCE) 0x0020) // Sets the physicalPresenceCMDEnable to TRUE
+#define TPM_PHYSICAL_PRESENCE_NOTPRESENT ((TPM_PHYSICAL_PRESENCE) 0x0010) // Sets PhysicalPresence = FALSE
+#define TPM_PHYSICAL_PRESENCE_PRESENT ((TPM_PHYSICAL_PRESENCE) 0x0008) // Sets PhysicalPresence = TRUE
+#define TPM_PHYSICAL_PRESENCE_LOCK ((TPM_PHYSICAL_PRESENCE) 0x0004) // Sets PhysicalPresenceLock = TRUE
+
+//
+// Part 2, section 4.10: TPM_MIGRATE_SCHEME
+//
+#define TPM_MS_MIGRATE ((TPM_MIGRATE_SCHEME) 0x0001) // A public key that can be used with all TPM migration commands other than 'ReWrap' mode.
+#define TPM_MS_REWRAP ((TPM_MIGRATE_SCHEME) 0x0002) // A public key that can be used for the ReWrap mode of TPM_CreateMigrationBlob.
+#define TPM_MS_MAINT ((TPM_MIGRATE_SCHEME) 0x0003) // A public key that can be used for the Maintenance commands
+#define TPM_MS_RESTRICT_MIGRATE ((TPM_MIGRATE_SCHEME) 0x0004) // The key is to be migrated to a Migration Authority.
+#define TPM_MS_RESTRICT_APPROVE_DOUBLE ((TPM_MIGRATE_SCHEME) 0x0005) // The key is to be migrated to an entity approved by a Migration Authority using double wrapping
+
+//
+// Part 2, section 4.11: TPM_EK_TYPE
+//
+#define TPM_EK_TYPE_ACTIVATE ((TPM_EK_TYPE) 0x0001) // The blob MUST be TPM_EK_BLOB_ACTIVATE
+#define TPM_EK_TYPE_AUTH ((TPM_EK_TYPE) 0x0002) // The blob MUST be TPM_EK_BLOB_AUTH
+
+//
+// Part 2, section 4.12: TPM_PLATFORM_SPECIFIC
+//
+#define TPM_PS_PC_11 ((TPM_PLATFORM_SPECIFIC) 0x0001) // PC Specific version 1.1
+#define TPM_PS_PC_12 ((TPM_PLATFORM_SPECIFIC) 0x0002) // PC Specific version 1.2
+#define TPM_PS_PDA_12 ((TPM_PLATFORM_SPECIFIC) 0x0003) // PDA Specific version 1.2
+#define TPM_PS_Server_12 ((TPM_PLATFORM_SPECIFIC) 0x0004) // Server Specific version 1.2
+#define TPM_PS_Mobile_12 ((TPM_PLATFORM_SPECIFIC) 0x0005) // Mobil Specific version 1.2
+
+//
+// Part 2, section 5: Basic Structures
+//
+
+//
+// Part 2, section 5.1: TPM_STRUCT_VER
+//
+typedef struct tdTPM_STRUCT_VER {
+ UINT8 major;
+ UINT8 minor;
+ UINT8 revMajor;
+ UINT8 revMinor;
+} TPM_STRUCT_VER;
+
+//
+// Part 2, section 5.3: TPM_VERSION
+//
+typedef struct tdTPM_VERSION {
+ TPM_VERSION_BYTE major;
+ TPM_VERSION_BYTE minor;
+ UINT8 revMajor;
+ UINT8 revMinor;
+} TPM_VERSION;
+
+//
+// Part 2, section 5.4: TPM_DIGEST
+//
+#define TPM_SHA1_160_HASH_LEN 0x14
+#define TPM_SHA1BASED_NONCE_LEN TPM_SHA1_160_HASH_LEN
+
+typedef struct tdTPM_DIGEST{
+ UINT8 digest[TPM_SHA1_160_HASH_LEN];
+} TPM_DIGEST;
+
+typedef TPM_DIGEST TPM_CHOSENID_HASH; // This SHALL be the digest of the chosen identityLabel and privacyCA for a new TPM identity.
+typedef TPM_DIGEST TPM_COMPOSITE_HASH; // This SHALL be the hash of a list of PCR indexes and PCR values that a key or data is bound to.
+typedef TPM_DIGEST TPM_DIRVALUE; // This SHALL be the value of a DIR register
+typedef TPM_DIGEST TPM_HMAC;
+typedef TPM_DIGEST TPM_PCRVALUE; // The value inside of the PCR
+typedef TPM_DIGEST TPM_AUDITDIGEST; // This SHALL be the value of the current internal audit state
+typedef TPM_DIGEST TPM_DAA_TPM_SEED; // This SHALL be a random value generated by a TPM immediately after the EK is installed in that TPM, whenever an EK is installed in that TPM
+typedef TPM_DIGEST TPM_DAA_CONTEXT_SEED; // This SHALL be a random value
+
+//
+// Part 2, section 5.5: TPM_NONCE
+//
+typedef struct tdTPM_NONCE{
+ UINT8 nonce[20];
+} TPM_NONCE;
+
+//
+// Part 2, section 5.6: TPM_AUTHDATA
+//
+typedef UINT8 tdTPM_AUTHDATA[20];
+typedef tdTPM_AUTHDATA TPM_AUTHDATA;
+typedef TPM_AUTHDATA TPM_SECRET;
+typedef TPM_AUTHDATA TPM_ENCAUTH;
+
+//
+// Part 2, section 5.7: TPM_KEY_HANDLE_LIST
+// Size of handle is loaded * sizeof(TPM_KEY_HANDLE)
+//
+typedef struct tdTPM_KEY_HANDLE_LIST {
+ UINT16 loaded;
+ TPM_KEY_HANDLE handle[1];
+} TPM_KEY_HANDLE_LIST;
+
+//
+// Part 2, section 5.8: TPM_KEY_USAGE values
+//
+
+#define TPM_KEY_SIGNING ((UINT16) 0x0010)
+// TPM_KEY_SIGNING SHALL indicate a signing key. The [private] key SHALL be
+// used for signing operations, only. This means that it MUST be a leaf of the
+// Protected Storage key hierarchy.
+
+#define TPM_KEY_STORAGE ((UINT16) 0x0011)
+// TPM_KEY_STORAGE SHALL indicate a storage key. The key SHALL be used to wrap
+// and unwrap other keys in the Protected Storage hierarchy
+
+#define TPM_KEY_IDENTITY ((UINT16) 0x0012)
+// TPM_KEY_IDENTITY SHALL indicate an identity key. The key SHALL be used for
+// operations that require a TPM identity, only.
+
+#define TPM_KEY_AUTHCHANGE ((UINT16) 0x0013)
+// TPM_KEY_AUTHCHANGE SHALL indicate an ephemeral key that is in use during
+// the ChangeAuthAsym process, only.
+
+#define TPM_KEY_BIND ((UINT16) 0x0014)
+// TPM_KEY_BIND SHALL indicate a key that can be used for TPM_Bind and
+// TPM_Unbind operations only.
+
+#define TPM_KEY_LEGACY ((UINT16) 0x0015)
+// TPM_KEY_LEGACY SHALL indicate a key that can perform signing and binding
+// operations. The key MAY be used for both signing and binding operations.
+// The TPM_KEY_LEGACY key type is to allow for use by applications where both
+// signing and encryption operations occur with the same key. The use of this
+// key type is not recommended TPM_KEY_MIGRATE 0x0016 This SHALL indicate a
+// key in use for TPM_MigrateKey
+
+#define TPM_KEY_MIGRATE ((UINT16) 0x0016)
+// TPM_KEY_MIGRAGE SHALL indicate a key in use for TPM_MigrateKey
+
+//
+// Part 2, section 5.8.1: Encryption/Signature schemes
+//
+
+#define TPM_ES_NONE ((TPM_ENC_SCHEME) 0x0001)
+#define TPM_ES_RSAESPKCSv15 ((TPM_ENC_SCHEME) 0x0002)
+#define TPM_ES_RSAESOAEP_SHA1_MGF1 ((TPM_ENC_SCHEME) 0x0003)
+#define TPM_ES_SYM_CNT ((TPM_ENC_SCHEME) 0x0004)
+#define TPM_ES_SYM_OFB ((TPM_ENC_SCHEME) 0x0005)
+
+#define TPM_SS_NONE ((TPM_SIG_SCHEME) 0x0001)
+#define TPM_SS_RSASSAPKCS1v15_SHA1 ((TPM_SIG_SCHEME) 0x0002)
+#define TPM_SS_RSASSAPKCS1v15_DER ((TPM_SIG_SCHEME) 0x0003)
+#define TPM_SS_RSASSAPKCS1v15_INFO ((TPM_SIG_SCHEME) 0x0004)
+
+//
+// Part 2, section 5.9: TPM_AUTH_DATA_USAGE values
+//
+#define TPM_AUTH_NEVER ((TPM_AUTH_DATA_USAGE) 0x00)
+#define TPM_AUTH_ALWAYS ((TPM_AUTH_DATA_USAGE) 0x01)
+#define TPM_AUTH_PRIV_USE_ONLY ((TPM_AUTH_DATA_USAGE) 0x03)
+
+//
+// Part 2, section 5.10: TPM_KEY_FLAGS
+//
+enum tdTPM_KEY_FLAGS {
+ redirection = 0x00000001,
+ migratable = 0x00000002,
+ isVolatile = 0x00000004,
+ pcrIgnoredOnRead = 0x00000008,
+ migrateAuthority = 0x00000010
+};
+
+//
+// Part 2, section 5.11: TPM_CHANGEAUTH_VALIDATE
+//
+typedef struct tdTPM_CHANGEAUTH_VALIDATE {
+ TPM_SECRET newAuthSecret;
+ TPM_NONCE n1;
+} TPM_CHANGEAUTH_VALIDATE;
+
+//
+// Part 2, section 5.12: TPM_MIGRATIONKEYAUTH
+// decalared after section 10 to catch declaration of TPM_PUBKEY
+//
+// Part 2 section 10.1: TPM_KEY_PARMS
+// [size_is(parmSize)] BYTE* parms;
+//
+typedef struct tdTPM_KEY_PARMS {
+ TPM_ALGORITHM_ID algorithmID;
+ TPM_ENC_SCHEME encScheme;
+ TPM_SIG_SCHEME sigScheme;
+ UINT32 parmSize;
+ UINT8 *parms;
+} TPM_KEY_PARMS;
+
+//
+// Part 2, section 10.4: TPM_STORE_PUBKEY
+//
+typedef struct tdTPM_STORE_PUBKEY {
+ UINT32 keyLength;
+ UINT8 key[1];
+} TPM_STORE_PUBKEY;
+
+//
+// Part 2, section 10.5: TPM_PUBKEY
+//
+typedef struct tdTPM_PUBKEY{
+ TPM_KEY_PARMS algorithmParms;
+ TPM_STORE_PUBKEY pubKey;
+} TPM_PUBKEY;
+
+//
+// Part 2, section 5.12: TPM_MIGRATIONKEYAUTH
+//
+typedef struct tdTPM_MIGRATIONKEYAUTH{
+ TPM_PUBKEY migrationKey;
+ TPM_MIGRATE_SCHEME migrationScheme;
+ TPM_DIGEST digest;
+} TPM_MIGRATIONKEYAUTH;
+
+//
+// Part 2, section 5.13: TPM_COUNTER_VALUE
+//
+typedef struct tdTPM_COUNTER_VALUE{
+ TPM_STRUCTURE_TAG tag;
+ UINT8 label[4];
+ TPM_ACTUAL_COUNT counter;
+} TPM_COUNTER_VALUE;
+
+//
+// Part 2, section 5.14: TPM_SIGN_INFO
+// Size of data indicated by dataLen
+//
+typedef struct tdTPM_SIGN_INFO {
+ TPM_STRUCTURE_TAG tag;
+ UINT8 fixed[4];
+ TPM_NONCE replay;
+ UINT32 dataLen;
+ UINT8 *data;
+} TPM_SIGN_INFO;
+
+//
+// Part 2, section 5.15: TPM_MSA_COMPOSITE
+// Number of migAuthDigest indicated by MSAlist
+//
+typedef struct tdTPM_MSA_COMPOSITE {
+ UINT32 MSAlist;
+ TPM_DIGEST migAuthDigest[1];
+} TPM_MSA_COMPOSITE;
+
+//
+// Part 2, section 5.16: TPM_CMK_AUTH
+//
+typedef struct tdTPM_CMK_AUTH{
+ TPM_DIGEST migrationAuthorityDigest;
+ TPM_DIGEST destinationKeyDigest;
+ TPM_DIGEST sourceKeyDigest;
+} TPM_CMK_AUTH;
+
+//
+// Part 2, section 5.17: TPM_CMK_DELEGATE
+//
+#define TPM_CMK_DELEGATE_SIGNING (((TPM_CMK_DELEGATE)1) << 31)
+#define TPM_CMK_DELEGATE_STORAGE (((TPM_CMK_DELEGATE)1) << 30)
+#define TPM_CMK_DELEGATE_BIND (((TPM_CMK_DELEGATE)1) << 29)
+#define TPM_CMK_DELEGATE_LEGACY (((TPM_CMK_DELEGATE)1) << 28)
+#define TPM_CMK_DELEGATE_MIGRATE (((TPM_CMK_DELEGATE)1) << 27)
+
+//
+// Part 2, section 5.18: TPM_SELECT_SIZE
+//
+typedef struct tdTPM_SELECT_SIZE {
+ UINT8 major;
+ UINT8 minor;
+ UINT16 reqSize;
+} TPM_SELECT_SIZE;
+
+//
+// Part 2, section 5,19: TPM_CMK_MIGAUTH
+//
+typedef struct tdTPM_CMK_MIGAUTH{
+ TPM_STRUCTURE_TAG tag;
+ TPM_DIGEST msaDigest;
+ TPM_DIGEST pubKeyDigest;
+} TPM_CMK_MIGAUTH;
+
+//
+// Part 2, section 5.20: TPM_CMK_SIGTICKET
+//
+typedef struct tdTPM_CMK_SIGTICKET{
+ TPM_STRUCTURE_TAG tag;
+ TPM_DIGEST verKeyDigest;
+ TPM_DIGEST signedData;
+} TPM_CMK_SIGTICKET;
+
+//
+// Part 2, section 5.21: TPM_CMK_MA_APPROVAL
+//
+typedef struct tdTPM_CMK_MA_APPROVAL{
+ TPM_STRUCTURE_TAG tag;
+ TPM_DIGEST migrationAuthorityDigest;
+} TPM_CMK_MA_APPROVAL;
+
+//
+// Part 2, section 6: Command Tags
+//
+#define TPM_TAG_RQU_COMMAND ((TPM_STRUCTURE_TAG) 0x00C1)
+#define TPM_TAG_RQU_AUTH1_COMMAND ((TPM_STRUCTURE_TAG) 0x00C2)
+#define TPM_TAG_RQU_AUTH2_COMMAND ((TPM_STRUCTURE_TAG) 0x00C3)
+#define TPM_TAG_RSP_COMMAND ((TPM_STRUCTURE_TAG) 0x00C4)
+#define TPM_TAG_RSP_AUTH1_COMMAND ((TPM_STRUCTURE_TAG) 0x00C5)
+#define TPM_TAG_RSP_AUTH2_COMMAND ((TPM_STRUCTURE_TAG) 0x00C6)
+
+//
+// Part 2, section 7.1: TPM_PERMANENT_FLAGS
+//
+typedef struct tdTPM_PERMANENT_FLAGS{
+ TPM_STRUCTURE_TAG tag;
+ BOOLEAN disable;
+ BOOLEAN ownership;
+ BOOLEAN deactivated;
+ BOOLEAN readPubek;
+ BOOLEAN disableOwnerClear;
+ BOOLEAN allowMaintenance;
+ BOOLEAN physicalPresenceLifetimeLock;
+ BOOLEAN physicalPresenceHWEnable;
+ BOOLEAN physicalPresenceCMDEnable;
+ BOOLEAN CEKPUsed;
+ BOOLEAN TPMpost;
+ BOOLEAN TPMpostLock;
+ BOOLEAN FIPS;
+ BOOLEAN operator;
+ BOOLEAN enableRevokeEK;
+ BOOLEAN nvLocked;
+ BOOLEAN readSRKPub;
+ BOOLEAN tpmEstablished;
+ BOOLEAN maintenanceDone;
+} TPM_PERMANENT_FLAGS;
+
+//
+// Part 2, section 7.1.1: PERMANENT_FLAGS Subcap for SetCapability
+//
+#define TPM_PF_DISABLE ((TPM_CAPABILITY_AREA) 1)
+#define TPM_PF_OWNERSHIP ((TPM_CAPABILITY_AREA) 2)
+#define TPM_PF_DEACTIVATED ((TPM_CAPABILITY_AREA) 3)
+#define TPM_PF_READPUBEK ((TPM_CAPABILITY_AREA) 4)
+#define TPM_PF_DISABLEOWNERCLEAR ((TPM_CAPABILITY_AREA) 5)
+#define TPM_PF_ALLOWMAINTENANCE ((TPM_CAPABILITY_AREA) 6)
+#define TPM_PF_PHYSICALPRESENCELIFETIMELOCK ((TPM_CAPABILITY_AREA) 7)
+#define TPM_PF_PHYSICALPRESENCEHWENABLE ((TPM_CAPABILITY_AREA) 8)
+#define TPM_PF_PHYSICALPRESENCECMDENABLE ((TPM_CAPABILITY_AREA) 9)
+#define TPM_PF_CEKPUSED ((TPM_CAPABILITY_AREA) 10)
+#define TPM_PF_TPMPOST ((TPM_CAPABILITY_AREA) 11)
+#define TPM_PF_TPMPOSTLOCK ((TPM_CAPABILITY_AREA) 12)
+#define TPM_PF_FIPS ((TPM_CAPABILITY_AREA) 13)
+#define TPM_PF_OPERATOR ((TPM_CAPABILITY_AREA) 14)
+#define TPM_PF_ENABLEREVOKEEK ((TPM_CAPABILITY_AREA) 15)
+#define TPM_PF_NV_LOCKED ((TPM_CAPABILITY_AREA) 16)
+#define TPM_PF_READSRKPUB ((TPM_CAPABILITY_AREA) 17)
+#define TPM_PF_TPMESTABLISHED ((TPM_CAPABILITY_AREA) 18)
+#define TPM_PF_MAINTENANCEDONE ((TPM_CAPABILITY_AREA) 19)
+
+//
+// Part 2, section 7.2: TPM_STCLEAR_FLAGS
+//
+typedef struct tdTPM_STCLEAR_FLAGS{
+ TPM_STRUCTURE_TAG tag;
+ BOOLEAN deactivated;
+ BOOLEAN disableForceClear;
+ BOOLEAN physicalPresence;
+ BOOLEAN physicalPresenceLock;
+ BOOLEAN bGlobalLock;
+} TPM_STCLEAR_FLAGS;
+
+//
+// Part 2, section 7.2.1: STCLEAR_FLAGS Subcap for SetCapability
+//
+#define TPM_SF_DEACTIVATED ((TPM_CAPABILITY_AREA) 1)
+#define TPM_SF_DISABLEFORCECLEAR ((TPM_CAPABILITY_AREA) 2)
+#define TPM_SF_PHYSICALPRESENCE ((TPM_CAPABILITY_AREA) 3)
+#define TPM_SF_PHYSICALPRESENCELOCK ((TPM_CAPABILITY_AREA) 4)
+#define TPM_SF_BGLOBALLOCK ((TPM_CAPABILITY_AREA) 5)
+
+//
+// Part 2, section 7.3: TPM_STANY_FLAGS
+//
+typedef struct tdTPM_STANY_FLAGS{
+ TPM_STRUCTURE_TAG tag;
+ BOOLEAN postInitialise;
+ TPM_MODIFIER_INDICATOR localityModifier;
+ BOOLEAN transportExclusive;
+ BOOLEAN TOSPresent;
+} TPM_STANY_FLAGS;
+
+//
+// Part 2, section 7.3.1: STANY_FLAGS Subcap for SetCapability
+//
+#define TPM_AF_POSTINITIALISE ((TPM_CAPABILITY_AREA) 1)
+#define TPM_AF_LOCALITYMODIFIER ((TPM_CAPABILITY_AREA) 2)
+#define TPM_AF_TRANSPORTEXCLUSIVE ((TPM_CAPABILITY_AREA) 3)
+#define TPM_AF_TOSPRESENT ((TPM_CAPABILITY_AREA) 4)
+
+//
+// All those structures (section 7.4, 7.5, 7.6) are not normative and
+// thus no definitions here
+//
+// Part 2, section 7.4: TPM_PERMANENT_DATA
+//
+//#define TPM_MIN_COUNTERS 4 // the minimum number of counters is 4
+//#define TPM_DELEGATE_KEY TPM_KEY
+//#define TPM_NUM_PCR 16
+//#define TPM_MAX_NV_WRITE_NOOWNER 64
+//typedef struct tdTPM_PERMANENT_DATA
+//{
+// TPM_STRUCTURE_TAG tag;
+// UINT8 revMajor;
+// UINT8 revMinor;
+// TPM_NONCE tpmProof;
+// TPM_NONCE ekReset;
+// TPM_SECRET ownerAuth;
+// TPM_SECRET operatorAuth;
+// TPM_DIRVALUE authDIR[1];
+// TPM_PUBKEY manuMaintPub;
+// TPM_KEY endorsementKey;
+// TPM_KEY srk;
+// TPM_KEY contextKey;
+// TPM_KEY delegateKey;
+// TPM_COUNTER_VALUE auditMonotonicCounter;
+// TPM_COUNTER_VALUE monitonicCounter[TPM_MIN_COUNTERS];
+// TPM_PCR_ATTRIBUTES pcrAttrib[TPM_NUM_PCR];
+// UINT8 ordinalAuditStatus[];
+// UINT8 *rngState;
+// TPM_FAMILY_TABLE familyTable;
+// TPM_DELEGATE_TABLE delegateTable;
+// UINT32 maxNVBufSize;
+// UINT32 lastFamilyID;
+// UINT32 noOwnerNVWrite;
+// TPM_CMK_DELEGATE restrictDelegate;
+// TPM_DAA_TPM_SEED tpmDAASeed;
+//} TPM_PERMANENT_DATA;
+
+//
+// Part 2, section 7.5: TPM_STCLEAR_DATA
+// available inside TPM only
+//
+//typedef struct tdTPM_STCLEAR_DATA
+//{
+// TPM_STRUCTURE_TAG tag;
+// TPM_NONCE contextNonceKey;
+// TPM_COUNT_ID countID;
+// UINT32 ownerReference;
+// BOOLEAN disableResetLock;
+//} TPM_STCLEAR_DATA;
+
+//
+// Part 2, section 7.6: TPM_STANY_DATA
+// available inside TPM only
+//
+//typedef struct tdTPM_STANY_DATA
+//{
+// TPM_STRUCTURE_TAG tag;
+// TPM_NONCE contextNonceSession;
+// TPM_DIGEST auditDigest;
+// TPM_CURRENT_TICKS currentTicks;
+// UINT32 contextCount;
+// UINT32 contextList[TPM_MIN_SESSION_LIST];
+// TPM_SESSION_DATA sessions[TPM_MIN_SESSIONS];
+//} TPM_STANY_DATA;
+
+//
+// Part 2, section 8: PCR Structures
+//
+
+//
+// Part 2, section 8.1: TPM_PCR_SELECTION
+// Size of pcrSelect[] indicated by sizeOfSelect
+//
+typedef struct tdTPM_PCR_SELECTION {
+ UINT16 sizeOfSelect;
+ UINT8 pcrSelect[1];
+} TPM_PCR_SELECTION;
+
+//
+// Part 2, section 8.2: TPM_PCR_COMPOSITE
+// Size of pcrValue[] indicated by valueSize
+//
+typedef struct tdTPM_PCR_COMPOSITE {
+ TPM_PCR_SELECTION select;
+ UINT32 valueSize;
+ TPM_PCRVALUE pcrValue[1];
+} TPM_PCR_COMPOSITE;
+
+//
+// Part 2, section 8.3: TPM_PCR_INFO
+//
+typedef struct tdTPM_PCR_INFO {
+ TPM_PCR_SELECTION pcrSelection;
+ TPM_COMPOSITE_HASH digestAtRelease;
+ TPM_COMPOSITE_HASH digestAtCreation;
+} TPM_PCR_INFO;
+
+//
+// Part 2, section 8.6: TPM_LOCALITY_SELECTION
+//
+typedef UINT8 TPM_LOCALITY_SELECTION;
+
+#define TPM_LOC_FOUR ((UINT8) 0x10)
+#define TPM_LOC_THREE ((UINT8) 0x08)
+#define TPM_LOC_TWO ((UINT8) 0x04)
+#define TPM_LOC_ONE ((UINT8) 0x02)
+#define TPM_LOC_ZERO ((UINT8) 0x01)
+
+//
+// Part 2, section 8.4: TPM_PCR_INFO_LONG
+//
+typedef struct tdTPM_PCR_INFO_LONG {
+ TPM_STRUCTURE_TAG tag;
+ TPM_LOCALITY_SELECTION localityAtCreation;
+ TPM_LOCALITY_SELECTION localityAtRelease;
+ TPM_PCR_SELECTION creationPCRSelection;
+ TPM_PCR_SELECTION releasePCRSelection;
+ TPM_COMPOSITE_HASH digestAtCreation;
+ TPM_COMPOSITE_HASH digestAtRelease;
+} TPM_PCR_INFO_LONG;
+
+//
+// Part 2, section 8.5: TPM_PCR_INFO_SHORT
+//
+typedef struct tdTPM_PCR_INFO_SHORT{
+ TPM_PCR_SELECTION pcrSelection;
+ TPM_LOCALITY_SELECTION localityAtRelease;
+ TPM_COMPOSITE_HASH digestAtRelease;
+} TPM_PCR_INFO_SHORT;
+
+//
+// Part 2, section 8.8: TPM_PCR_ATTRIBUTES
+//
+typedef struct tdTPM_PCR_ATTRIBUTES{
+ BOOLEAN pcrReset;
+ TPM_LOCALITY_SELECTION pcrExtendLocal;
+ TPM_LOCALITY_SELECTION pcrResetLocal;
+} TPM_PCR_ATTRIBUTES;
+
+//
+// Part 2, section 9: Storage Structures
+//
+
+//
+// Part 2, section 9.1: TPM_STORED_DATA
+// [size_is(sealInfoSize)] BYTE* sealInfo;
+// [size_is(encDataSize)] BYTE* encData;
+//
+typedef struct tdTPM_STORED_DATA {
+ TPM_STRUCT_VER ver;
+ UINT32 sealInfoSize;
+ UINT8 *sealInfo;
+ UINT32 encDataSize;
+ UINT8 *encData;
+} TPM_STORED_DATA;
+
+//
+// Part 2, section 9.2: TPM_STORED_DATA12
+// [size_is(sealInfoSize)] BYTE* sealInfo;
+// [size_is(encDataSize)] BYTE* encData;
+//
+typedef struct tdTPM_STORED_DATA12 {
+ TPM_STRUCTURE_TAG tag;
+ TPM_ENTITY_TYPE et;
+ UINT32 sealInfoSize;
+ UINT8 *sealInfo;
+ UINT32 encDataSize;
+ UINT8 *encData;
+} TPM_STORED_DATA12;
+
+//
+// Part 2, section 9.3: TPM_SEALED_DATA
+// [size_is(dataSize)] BYTE* data;
+//
+typedef struct tdTPM_SEALED_DATA {
+ TPM_PAYLOAD_TYPE payload;
+ TPM_SECRET authData;
+ TPM_NONCE tpmProof;
+ TPM_DIGEST storedDigest;
+ UINT32 dataSize;
+ UINT8 *data;
+} TPM_SEALED_DATA;
+
+//
+// Part 2, section 9.4: TPM_SYMMETRIC_KEY
+// [size_is(size)] BYTE* data;
+//
+typedef struct tdTPM_SYMMETRIC_KEY {
+ TPM_ALGORITHM_ID algId;
+ TPM_ENC_SCHEME encScheme;
+ UINT16 dataSize;
+ UINT8 *data;
+} TPM_SYMMETRIC_KEY;
+
+//
+// Part 2, section 9.5: TPM_BOUND_DATA
+//
+typedef struct tdTPM_BOUND_DATA {
+ TPM_STRUCT_VER ver;
+ TPM_PAYLOAD_TYPE payload;
+ UINT8 payloadData[1];
+} TPM_BOUND_DATA;
+
+//
+// Part 2 section 10: TPM_KEY complex
+//
+
+//
+// Part 2, section 10.2: TPM_KEY
+// [size_is(encDataSize)] BYTE* encData;
+//
+typedef struct tdTPM_KEY{
+ TPM_STRUCT_VER ver;
+ TPM_KEY_USAGE keyUsage;
+ TPM_KEY_FLAGS keyFlags;
+ TPM_AUTH_DATA_USAGE authDataUsage;
+ TPM_KEY_PARMS algorithmParms;
+ UINT32 PCRInfoSize;
+ UINT8 *PCRInfo;
+ TPM_STORE_PUBKEY pubKey;
+ UINT32 encDataSize;
+ UINT8 *encData;
+} TPM_KEY;
+
+//
+// Part 2, section 10.3: TPM_KEY12
+// [size_is(encDataSize)] BYTE* encData;
+//
+typedef struct tdTPM_KEY12{
+ TPM_STRUCTURE_TAG tag;
+ UINT16 fill;
+ TPM_KEY_USAGE keyUsage;
+ TPM_KEY_FLAGS keyFlags;
+ TPM_AUTH_DATA_USAGE authDataUsage;
+ TPM_KEY_PARMS algorithmParms;
+ UINT32 PCRInfoSize;
+ UINT8 *PCRInfo;
+ TPM_STORE_PUBKEY pubKey;
+ UINT32 encDataSize;
+ UINT8 *encData;
+} TPM_KEY12;
+
+//
+// Part 2, section 10.7: TPM_STORE_PRIVKEY
+// [size_is(keyLength)] BYTE* key;
+//
+typedef struct tdTPM_STORE_PRIVKEY {
+ UINT32 keyLength;
+ UINT8 *key;
+} TPM_STORE_PRIVKEY;
+
+//
+// Part 2, section 10.6: TPM_STORE_ASYMKEY
+//
+typedef struct tdTPM_STORE_ASYMKEY { // pos len total
+ TPM_PAYLOAD_TYPE payload; // 0 1 1
+ TPM_SECRET usageAuth; // 1 20 21
+ TPM_SECRET migrationAuth; // 21 20 41
+ TPM_DIGEST pubDataDigest; // 41 20 61
+ TPM_STORE_PRIVKEY privKey; // 61 132-151 193-214
+} TPM_STORE_ASYMKEY;
+
+//
+// Part 2, section 10.8: TPM_MIGRATE_ASYMKEY
+// [size_is(partPrivKeyLen)] BYTE* partPrivKey;
+//
+typedef struct tdTPM_MIGRATE_ASYMKEY { // pos len total
+ TPM_PAYLOAD_TYPE payload; // 0 1 1
+ TPM_SECRET usageAuth; // 1 20 21
+ TPM_DIGEST pubDataDigest; // 21 20 41
+ UINT32 partPrivKeyLen; // 41 4 45
+ UINT8 *partPrivKey; // 45 112-127 157-172
+} TPM_MIGRATE_ASYMKEY;
+
+//
+// Part 2, section 10.9: TPM_KEY_CONTROL
+//
+#define TPM_KEY_CONTROL_OWNER_EVICT ((UINT32) 0x00000001)
+
+//
+// Part 2, section 11: Signed Structures
+//
+
+typedef struct tdTPM_CERTIFY_INFO
+{
+ TPM_STRUCT_VER version;
+ TPM_KEY_USAGE keyUsage;
+ TPM_KEY_FLAGS keyFlags;
+ TPM_AUTH_DATA_USAGE authDataUsage;
+ TPM_KEY_PARMS algorithmParms;
+ TPM_DIGEST pubkeyDigest;
+ TPM_NONCE data;
+ BOOLEAN parentPCRStatus;
+ UINT32 PCRInfoSize;
+ UINT8 *PCRInfo;
+} TPM_CERTIFY_INFO;
+
+typedef struct tdTPM_CERTIFY_INFO2
+{
+ TPM_STRUCTURE_TAG tag;
+ UINT8 fill;
+ TPM_PAYLOAD_TYPE payloadType;
+ TPM_KEY_USAGE keyUsage;
+ TPM_KEY_FLAGS keyFlags;
+ TPM_AUTH_DATA_USAGE authDataUsage;
+ TPM_KEY_PARMS algorithmParms;
+ TPM_DIGEST pubkeyDigest;
+ TPM_NONCE data;
+ BOOLEAN parentPCRStatus;
+ UINT32 PCRInfoSize;
+ UINT8 *PCRInfo;
+ UINT32 migrationAuthoritySize;
+ UINT8 *migrationAuthority;
+} TPM_CERTIFY_INFO2;
+
+typedef struct tdTPM_QUOTE_INFO
+{
+ TPM_STRUCT_VER version;
+ UINT8 fixed[4];
+ TPM_COMPOSITE_HASH digestValue;
+ TPM_NONCE externalData;
+} TPM_QUOTE_INFO;
+
+typedef struct tdTPM_QUOTE_INFO2
+{
+ TPM_STRUCTURE_TAG tag;
+ UINT8 fixed[4];
+ TPM_NONCE externalData;
+ TPM_PCR_INFO_SHORT infoShort;
+} TPM_QUOTE_INFO2;
+
+//
+// Part 2, section 12: Identity Structures
+//
+
+typedef struct tdTPM_EK_BLOB
+{
+ TPM_STRUCTURE_TAG tag;
+ TPM_EK_TYPE ekType;
+ UINT32 blobSize;
+ UINT8 *blob;
+} TPM_EK_BLOB;
+
+typedef struct tdTPM_EK_BLOB_ACTIVATE
+{
+ TPM_STRUCTURE_TAG tag;
+ TPM_SYMMETRIC_KEY sessionKey;
+ TPM_DIGEST idDigest;
+ TPM_PCR_INFO_SHORT pcrInfo;
+} TPM_EK_BLOB_ACTIVATE;
+
+typedef struct tdTPM_EK_BLOB_AUTH
+{
+ TPM_STRUCTURE_TAG tag;
+ TPM_SECRET authValue;
+} TPM_EK_BLOB_AUTH;
+
+
+// TPM_CHOSENID_HASH = SHA(identityLabel || privacyCA)
+typedef TPM_DIGEST TPM_CHOSENID_HASH;
+
+typedef struct tdTPM_IDENTITY_CONTENTS
+{
+ TPM_STRUCT_VER ver;
+ UINT32 ordinal;
+ TPM_CHOSENID_HASH labelPrivCADigest;
+ TPM_PUBKEY identityPubKey;
+} TPM_IDENTITY_CONTENTS;
+
+typedef struct tdTPM_IDENTITY_REQ
+{
+ UINT32 asymSize;
+ UINT32 symSize;
+ TPM_KEY_PARMS asymAlgorithm;
+ TPM_KEY_PARMS symAlgorithm;
+ UINT8 *asymBlob;
+ UINT8 *symBlob;
+} TPM_IDENTITY_REQ;
+
+typedef struct tdTPM_IDENTITY_PROOF
+{
+ TPM_STRUCT_VER ver;
+ UINT32 labelSize;
+ UINT32 identityBindingSize;
+ UINT32 endorsementSize;
+ UINT32 platformSize;
+ UINT32 conformanceSize;
+ TPM_PUBKEY identityKey;
+ UINT8 *labelArea;
+ UINT8 *identityBinding;
+ UINT8 *endorsementCredential;
+ UINT8 *platformCredential;
+ UINT8 *conformanceCredential;
+} TPM_IDENTITY_PROOF;
+
+typedef struct tdTPM_ASYM_CA_CONTENTS
+{
+ TPM_SYMMETRIC_KEY sessionKey;
+ TPM_DIGEST idDigest;
+} TPM_ASYM_CA_CONTENTS;
+
+typedef struct tdTPM_SYM_CA_ATTESTATION
+{
+ UINT32 credSize;
+ TPM_KEY_PARMS algorithm;
+ UINT8 *credential;
+} TPM_SYM_CA_ATTESTATION;
+
+//
+// Part 2, section 15: TPM_CURRENT_TICKS
+// Placed here out of order because definitions are used in section 13.
+//
+typedef struct tdTPM_CURRENT_TICKS {
+ TPM_STRUCTURE_TAG tag;
+ UINT64 currentTicks;
+ UINT16 tickRate;
+ TPM_NONCE tickNonce;
+} TPM_CURRENT_TICKS;
+
+//
+// Part 2, section 13: Transport structures
+//
+
+#define TPM_TRANSPORT_ENCRYPT ((UINT32)0x00000001)
+#define TPM_TRANSPORT_LOG ((UINT32)0x00000002)
+#define TPM_TRANSPORT_EXCLUSIVE ((UINT32)0x00000004)
+
+typedef struct tdTPM_TRANSPORT_PUBLIC
+{
+ TPM_STRUCTURE_TAG tag;
+ TPM_TRANSPORT_ATTRIBUTES transAttributes;
+ TPM_ALGORITHM_ID algId;
+ TPM_ENC_SCHEME encScheme;
+} TPM_TRANSPORT_PUBLIC;
+
+typedef struct tdTPM_TRANSPORT_INTERNAL
+{
+ TPM_STRUCTURE_TAG tag;
+ TPM_AUTHDATA authData;
+ TPM_TRANSPORT_PUBLIC transPublic;
+ TPM_TRANSHANDLE transHandle;
+ TPM_NONCE transNonceEven;
+ TPM_DIGEST transDigest;
+} TPM_TRANSPORT_INTERNAL;
+
+typedef struct tdTPM_TRANSPORT_LOG_IN
+{
+ TPM_STRUCTURE_TAG tag;
+ TPM_DIGEST parameters;
+ TPM_DIGEST pubKeyHash;
+} TPM_TRANSPORT_LOG_IN;
+
+typedef struct tdTPM_TRANSPORT_LOG_OUT
+{
+ TPM_STRUCTURE_TAG tag;
+ TPM_CURRENT_TICKS currentTicks;
+ TPM_DIGEST parameters;
+ TPM_MODIFIER_INDICATOR locality;
+} TPM_TRANSPORT_LOG_OUT;
+
+typedef struct tdTPM_TRANSPORT_AUTH
+{
+ TPM_STRUCTURE_TAG tag;
+ TPM_AUTHDATA authData;
+} TPM_TRANSPORT_AUTH;
+
+//
+// Part 2, section 14: Audit Structures
+//
+
+typedef struct tdTPM_AUDIT_EVENT_IN
+{
+ TPM_STRUCTURE_TAG tag;
+ TPM_DIGEST inputParms;
+ TPM_COUNTER_VALUE auditCount;
+} TPM_AUDIT_EVENT_IN;
+
+typedef struct tdTPM_AUDIT_EVENT_OUT
+{
+ TPM_STRUCTURE_TAG tag;
+ TPM_COMMAND_CODE ordinal;
+ TPM_DIGEST outputParms;
+ TPM_COUNTER_VALUE auditCount;
+ TPM_RESULT returnCode;
+} TPM_AUDIT_EVENT_OUT;
+
+//
+// Part 2, section 16: Return Codes
+//
+#ifndef TPM_BASE
+#error "TPM Error Codes require definition of TPM_BASE"
+#endif
+
+#define TPM_VENDOR_ERROR TPM_Vendor_Specific32
+#define TPM_NON_FATAL 0x00000800
+
+#define TPM_SUCCESS ((TPM_RESULT) TPM_BASE)
+#define TPM_AUTHFAIL ((TPM_RESULT) (TPM_BASE + 1))
+#define TPM_BADINDEX ((TPM_RESULT) (TPM_BASE + 2))
+#define TPM_BAD_PARAMETER ((TPM_RESULT) (TPM_BASE + 3))
+#define TPM_AUDITFAILURE ((TPM_RESULT) (TPM_BASE + 4))
+#define TPM_CLEAR_DISABLED ((TPM_RESULT) (TPM_BASE + 5))
+#define TPM_DEACTIVATED ((TPM_RESULT) (TPM_BASE + 6))
+#define TPM_DISABLED ((TPM_RESULT) (TPM_BASE + 7))
+#define TPM_DISABLED_CMD ((TPM_RESULT) (TPM_BASE + 8))
+#define TPM_FAIL ((TPM_RESULT) (TPM_BASE + 9))
+#define TPM_BAD_ORDINAL ((TPM_RESULT) (TPM_BASE + 10))
+#define TPM_INSTALL_DISABLED ((TPM_RESULT) (TPM_BASE + 11))
+#define TPM_INVALID_KEYHANDLE ((TPM_RESULT) (TPM_BASE + 12))
+#define TPM_KEYNOTFOUND ((TPM_RESULT) (TPM_BASE + 13))
+#define TPM_INAPPROPRIATE_ENC ((TPM_RESULT) (TPM_BASE + 14))
+#define TPM_MIGRATEFAIL ((TPM_RESULT) (TPM_BASE + 15))
+#define TPM_INVALID_PCR_INFO ((TPM_RESULT) (TPM_BASE + 16))
+#define TPM_NOSPACE ((TPM_RESULT) (TPM_BASE + 17))
+#define TPM_NOSRK ((TPM_RESULT) (TPM_BASE + 18))
+#define TPM_NOTSEALED_BLOB ((TPM_RESULT) (TPM_BASE + 19))
+#define TPM_OWNER_SET ((TPM_RESULT) (TPM_BASE + 20))
+#define TPM_RESOURCES ((TPM_RESULT) (TPM_BASE + 21))
+#define TPM_SHORTRANDOM ((TPM_RESULT) (TPM_BASE + 22))
+#define TPM_SIZE ((TPM_RESULT) (TPM_BASE + 23))
+#define TPM_WRONGPCRVAL ((TPM_RESULT) (TPM_BASE + 24))
+#define TPM_BAD_PARAM_SIZE ((TPM_RESULT) (TPM_BASE + 25))
+#define TPM_SHA_THREAD ((TPM_RESULT) (TPM_BASE + 26))
+#define TPM_SHA_ERROR ((TPM_RESULT) (TPM_BASE + 27))
+#define TPM_FAILEDSELFTEST ((TPM_RESULT) (TPM_BASE + 28))
+#define TPM_AUTH2FAIL ((TPM_RESULT) (TPM_BASE + 29))
+#define TPM_BADTAG ((TPM_RESULT) (TPM_BASE + 30))
+#define TPM_IOERROR ((TPM_RESULT) (TPM_BASE + 31))
+#define TPM_ENCRYPT_ERROR ((TPM_RESULT) (TPM_BASE + 32))
+#define TPM_DECRYPT_ERROR ((TPM_RESULT) (TPM_BASE + 33))
+#define TPM_INVALID_AUTHHANDLE ((TPM_RESULT) (TPM_BASE + 34))
+#define TPM_NO_ENDORSEMENT ((TPM_RESULT) (TPM_BASE + 35))
+#define TPM_INVALID_KEYUSAGE ((TPM_RESULT) (TPM_BASE + 36))
+#define TPM_WRONG_ENTITYTYPE ((TPM_RESULT) (TPM_BASE + 37))
+#define TPM_INVALID_POSTINIT ((TPM_RESULT) (TPM_BASE + 38))
+#define TPM_INAPPROPRIATE_SIG ((TPM_RESULT) (TPM_BASE + 39))
+#define TPM_BAD_KEY_PROPERTY ((TPM_RESULT) (TPM_BASE + 40))
+#define TPM_BAD_MIGRATION ((TPM_RESULT) (TPM_BASE + 41))
+#define TPM_BAD_SCHEME ((TPM_RESULT) (TPM_BASE + 42))
+#define TPM_BAD_DATASIZE ((TPM_RESULT) (TPM_BASE + 43))
+#define TPM_BAD_MODE ((TPM_RESULT) (TPM_BASE + 44))
+#define TPM_BAD_PRESENCE ((TPM_RESULT) (TPM_BASE + 45))
+#define TPM_BAD_VERSION ((TPM_RESULT) (TPM_BASE + 46))
+#define TPM_NO_WRAP_TRANSPORT ((TPM_RESULT) (TPM_BASE + 47))
+#define TPM_AUDITFAIL_UNSUCCESSFUL ((TPM_RESULT) (TPM_BASE + 48))
+#define TPM_AUDITFAIL_SUCCESSFUL ((TPM_RESULT) (TPM_BASE + 49))
+#define TPM_NOTRESETABLE ((TPM_RESULT) (TPM_BASE + 50))
+#define TPM_NOTLOCAL ((TPM_RESULT) (TPM_BASE + 51))
+#define TPM_BAD_TYPE ((TPM_RESULT) (TPM_BASE + 52))
+#define TPM_INVALID_RESOURCE ((TPM_RESULT) (TPM_BASE + 53))
+#define TPM_NOTFIPS ((TPM_RESULT) (TPM_BASE + 54))
+#define TPM_INVALID_FAMILY ((TPM_RESULT) (TPM_BASE + 55))
+#define TPM_NO_NV_PERMISSION ((TPM_RESULT) (TPM_BASE + 56))
+#define TPM_REQUIRES_SIGN ((TPM_RESULT) (TPM_BASE + 57))
+#define TPM_KEY_NOTSUPPORTED ((TPM_RESULT) (TPM_BASE + 58))
+#define TPM_AUTH_CONFLICT ((TPM_RESULT) (TPM_BASE + 59))
+#define TPM_AREA_LOCKED ((TPM_RESULT) (TPM_BASE + 60))
+#define TPM_BAD_LOCALITY ((TPM_RESULT) (TPM_BASE + 61))
+#define TPM_READ_ONLY ((TPM_RESULT) (TPM_BASE + 62))
+#define TPM_PER_NOWRITE ((TPM_RESULT) (TPM_BASE + 63))
+#define TPM_FAMILYCOUNT ((TPM_RESULT) (TPM_BASE + 64))
+#define TPM_WRITE_LOCKED ((TPM_RESULT) (TPM_BASE + 65))
+#define TPM_BAD_ATTRIBUTES ((TPM_RESULT) (TPM_BASE + 66))
+#define TPM_INVALID_STRUCTURE ((TPM_RESULT) (TPM_BASE + 67))
+#define TPM_KEY_OWNER_CONTROL ((TPM_RESULT) (TPM_BASE + 68))
+#define TPM_BAD_COUNTER ((TPM_RESULT) (TPM_BASE + 69))
+#define TPM_NOT_FULLWRITE ((TPM_RESULT) (TPM_BASE + 70))
+#define TPM_CONTEXT_GAP ((TPM_RESULT) (TPM_BASE + 71))
+#define TPM_MAXNVWRITES ((TPM_RESULT) (TPM_BASE + 72))
+#define TPM_NOOPERATOR ((TPM_RESULT) (TPM_BASE + 73))
+#define TPM_RESOURCEMISSING ((TPM_RESULT) (TPM_BASE + 74))
+#define TPM_DELEGATE_LOCK ((TPM_RESULT) (TPM_BASE + 75))
+#define TPM_DELEGATE_FAMILY ((TPM_RESULT) (TPM_BASE + 76))
+#define TPM_DELEGATE_ADMIN ((TPM_RESULT) (TPM_BASE + 77))
+#define TPM_TRANSPORT_NOTEXCLUSIVE ((TPM_RESULT) (TPM_BASE + 78))
+#define TPM_OWNER_CONTROL ((TPM_RESULT) (TPM_BASE + 79))
+#define TPM_DAA_RESOURCES ((TPM_RESULT) (TPM_BASE + 80))
+#define TPM_DAA_INPUT_DATA0 ((TPM_RESULT) (TPM_BASE + 81))
+#define TPM_DAA_INPUT_DATA1 ((TPM_RESULT) (TPM_BASE + 82))
+#define TPM_DAA_ISSUER_SETTINGS ((TPM_RESULT) (TPM_BASE + 83))
+#define TPM_DAA_TPM_SETTINGS ((TPM_RESULT) (TPM_BASE + 84))
+#define TPM_DAA_STAGE ((TPM_RESULT) (TPM_BASE + 85))
+#define TPM_DAA_ISSUER_VALIDITY ((TPM_RESULT) (TPM_BASE + 86))
+#define TPM_DAA_WRONG_W ((TPM_RESULT) (TPM_BASE + 87))
+#define TPM_BAD_HANDLE ((TPM_RESULT) (TPM_BASE + 88))
+#define TPM_BAD_DELEGATE ((TPM_RESULT) (TPM_BASE + 89))
+#define TPM_BADCONTEXT ((TPM_RESULT) (TPM_BASE + 90))
+#define TPM_TOOMANYCONTEXTS ((TPM_RESULT) (TPM_BASE + 91))
+#define TPM_MA_TICKET_SIGNATURE ((TPM_RESULT) (TPM_BASE + 92))
+#define TPM_MA_DESTINATION ((TPM_RESULT) (TPM_BASE + 93))
+#define TPM_MA_SOURCE ((TPM_RESULT) (TPM_BASE + 94))
+#define TPM_MA_AUTHORITY ((TPM_RESULT) (TPM_BASE + 95))
+#define TPM_PERMANENTEK ((TPM_RESULT) (TPM_BASE + 97))
+#define TPM_BAD_SIGNATURE ((TPM_RESULT) (TPM_BASE + 98))
+#define TPM_NOCONTEXTSPACE ((TPM_RESULT) (TPM_BASE + 99))
+
+#define TPM_RETRY ((TPM_RESULT) (TPM_BASE + TPM_NON_FATAL))
+#define TPM_NEEDS_SELFTEST ((TPM_RESULT) (TPM_BASE + TPM_NON_FATAL + 1))
+#define TPM_DOING_SELFTEST ((TPM_RESULT) (TPM_BASE + TPM_NON_FATAL + 2))
+#define TPM_DEFEND_LOCK_RUNNING ((TPM_RESULT) (TPM_BASE + TPM_NON_FATAL + 3))
+
+//
+// Part 2, section 17: Ordinals
+//
+// Ordinals are 32 bit values. The upper byte contains values that serve as
+// flag indicators, the next byte contains values indicating what committee
+// designated the ordinal, and the final two bytes contain the Command
+// Ordinal Index.
+// 3 2 1
+// 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+// +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+// |P|C|V| Reserved| Purview | Command Ordinal Index |
+// +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+//
+// Where:
+//
+// * P is Protected/Unprotected command. When 0 the command is a Protected
+// command, when 1 the command is an Unprotected command.
+//
+// * C is Non-Connection/Connection related command. When 0 this command
+// passes through to either the protected (TPM) or unprotected (TSS)
+// components.
+//
+// * V is TPM/Vendor command. When 0 the command is TPM defined, when 1 the
+// command is vendor defined.
+//
+// * All reserved area bits are set to 0.
+//
+
+#define TPM_ORD_ActivateIdentity ((TPM_COMMAND_CODE) 0x0000007A)
+#define TPM_ORD_AuthorizeMigrationKey ((TPM_COMMAND_CODE) 0x0000002B)
+#define TPM_ORD_CertifyKey ((TPM_COMMAND_CODE) 0x00000032)
+#define TPM_ORD_CertifyKey2 ((TPM_COMMAND_CODE) 0x00000033)
+#define TPM_ORD_CertifySelfTest ((TPM_COMMAND_CODE) 0x00000052)
+#define TPM_ORD_ChangeAuth ((TPM_COMMAND_CODE) 0x0000000C)
+#define TPM_ORD_ChangeAuthAsymFinish ((TPM_COMMAND_CODE) 0x0000000F)
+#define TPM_ORD_ChangeAuthAsymStart ((TPM_COMMAND_CODE) 0x0000000E)
+#define TPM_ORD_ChangeAuthOwner ((TPM_COMMAND_CODE) 0x00000010)
+#define TPM_ORD_CMK_ApproveMA ((TPM_COMMAND_CODE) 0x0000001D)
+#define TPM_ORD_CMK_ConvertMigration ((TPM_COMMAND_CODE) 0x00000024)
+#define TPM_ORD_CMK_CreateBlob ((TPM_COMMAND_CODE) 0x0000001B)
+#define TPM_ORD_CMK_CreateKey ((TPM_COMMAND_CODE) 0x00000013)
+#define TPM_ORD_CMK_CreateTicket ((TPM_COMMAND_CODE) 0x00000012)
+#define TPM_ORD_CMK_SetRestrictions ((TPM_COMMAND_CODE) 0x0000001C)
+#define TPM_ORD_ContinueSelfTest ((TPM_COMMAND_CODE) 0x00000053)
+#define TPM_ORD_ConvertMigrationBlob ((TPM_COMMAND_CODE) 0x0000002A)
+#define TPM_ORD_CreateCounter ((TPM_COMMAND_CODE) 0x000000DC)
+#define TPM_ORD_CreateEndorsementKeyPair ((TPM_COMMAND_CODE) 0x00000078)
+#define TPM_ORD_CreateMaintenanceArchive ((TPM_COMMAND_CODE) 0x0000002C)
+#define TPM_ORD_CreateMigrationBlob ((TPM_COMMAND_CODE) 0x00000028)
+#define TPM_ORD_CreateRevocableEK ((TPM_COMMAND_CODE) 0x0000007F)
+#define TPM_ORD_CreateWrapKey ((TPM_COMMAND_CODE) 0x0000001F)
+#define TPM_ORD_DAA_JOIN ((TPM_COMMAND_CODE) 0x00000029)
+#define TPM_ORD_DAA_SIGN ((TPM_COMMAND_CODE) 0x00000031)
+#define TPM_ORD_Delegate_CreateKeyDelegation ((TPM_COMMAND_CODE) 0x000000D4)
+#define TPM_ORD_Delegate_CreateOwnerDelegation ((TPM_COMMAND_CODE) 0x000000D5)
+#define TPM_ORD_Delegate_LoadOwnerDelegation ((TPM_COMMAND_CODE) 0x000000D8)
+#define TPM_ORD_Delegate_Manage ((TPM_COMMAND_CODE) 0x000000D2)
+#define TPM_ORD_Delegate_ReadTable ((TPM_COMMAND_CODE) 0x000000DB)
+#define TPM_ORD_Delegate_UpdateVerification ((TPM_COMMAND_CODE) 0x000000D1)
+#define TPM_ORD_Delegate_VerifyDelegation ((TPM_COMMAND_CODE) 0x000000D6)
+#define TPM_ORD_DirRead ((TPM_COMMAND_CODE) 0x0000001A)
+#define TPM_ORD_DirWriteAuth ((TPM_COMMAND_CODE) 0x00000019)
+#define TPM_ORD_DisableForceClear ((TPM_COMMAND_CODE) 0x0000005E)
+#define TPM_ORD_DisableOwnerClear ((TPM_COMMAND_CODE) 0x0000005C)
+#define TPM_ORD_DisablePubekRead ((TPM_COMMAND_CODE) 0x0000007E)
+#define TPM_ORD_DSAP ((TPM_COMMAND_CODE) 0x00000011)
+#define TPM_ORD_EstablishTransport ((TPM_COMMAND_CODE) 0x000000E6)
+#define TPM_ORD_EvictKey ((TPM_COMMAND_CODE) 0x00000022)
+#define TPM_ORD_ExecuteTransport ((TPM_COMMAND_CODE) 0x000000E7)
+#define TPM_ORD_Extend ((TPM_COMMAND_CODE) 0x00000014)
+#define TPM_ORD_FieldUpgrade ((TPM_COMMAND_CODE) 0x000000AA)
+#define TPM_ORD_FlushSpecific ((TPM_COMMAND_CODE) 0x000000BA)
+#define TPM_ORD_ForceClear ((TPM_COMMAND_CODE) 0x0000005D)
+#define TPM_ORD_GetAuditDigest ((TPM_COMMAND_CODE) 0x00000085)
+#define TPM_ORD_GetAuditDigestSigned ((TPM_COMMAND_CODE) 0x00000086)
+#define TPM_ORD_GetAuditEvent ((TPM_COMMAND_CODE) 0x00000082)
+#define TPM_ORD_GetAuditEventSigned ((TPM_COMMAND_CODE) 0x00000083)
+#define TPM_ORD_GetCapability ((TPM_COMMAND_CODE) 0x00000065)
+#define TPM_ORD_GetCapabilityOwner ((TPM_COMMAND_CODE) 0x00000066)
+#define TPM_ORD_GetCapabilitySigned ((TPM_COMMAND_CODE) 0x00000064)
+#define TPM_ORD_GetOrdinalAuditStatus ((TPM_COMMAND_CODE) 0x0000008C)
+#define TPM_ORD_GetPubKey ((TPM_COMMAND_CODE) 0x00000021)
+#define TPM_ORD_GetRandom ((TPM_COMMAND_CODE) 0x00000046)
+#define TPM_ORD_GetTestResult ((TPM_COMMAND_CODE) 0x00000054)
+#define TPM_ORD_GetTicks ((TPM_COMMAND_CODE) 0x000000F1)
+#define TPM_ORD_IncrementCounter ((TPM_COMMAND_CODE) 0x000000DD)
+#define TPM_ORD_Init ((TPM_COMMAND_CODE) 0x00000097)
+#define TPM_ORD_KeyControlOwner ((TPM_COMMAND_CODE) 0x00000023)
+#define TPM_ORD_KillMaintenanceFeature ((TPM_COMMAND_CODE) 0x0000002E)
+#define TPM_ORD_LoadAuthContext ((TPM_COMMAND_CODE) 0x000000B7)
+#define TPM_ORD_LoadContext ((TPM_COMMAND_CODE) 0x000000B9)
+#define TPM_ORD_LoadKey ((TPM_COMMAND_CODE) 0x00000020)
+#define TPM_ORD_LoadKey2 ((TPM_COMMAND_CODE) 0x00000041)
+#define TPM_ORD_LoadKeyContext ((TPM_COMMAND_CODE) 0x000000B5)
+#define TPM_ORD_LoadMaintenanceArchive ((TPM_COMMAND_CODE) 0x0000002D)
+#define TPM_ORD_LoadManuMaintPub ((TPM_COMMAND_CODE) 0x0000002F)
+#define TPM_ORD_MakeIdentity ((TPM_COMMAND_CODE) 0x00000079)
+#define TPM_ORD_MigrateKey ((TPM_COMMAND_CODE) 0x00000025)
+#define TPM_ORD_NV_DefineSpace ((TPM_COMMAND_CODE) 0x000000CC)
+#define TPM_ORD_NV_ReadValue ((TPM_COMMAND_CODE) 0x000000CF)
+#define TPM_ORD_NV_ReadValueAuth ((TPM_COMMAND_CODE) 0x000000D0)
+#define TPM_ORD_NV_WriteValue ((TPM_COMMAND_CODE) 0x000000CD)
+#define TPM_ORD_NV_WriteValueAuth ((TPM_COMMAND_CODE) 0x000000CE)
+#define TPM_ORD_OIAP ((TPM_COMMAND_CODE) 0x0000000A)
+#define TPM_ORD_OSAP ((TPM_COMMAND_CODE) 0x0000000B)
+#define TPM_ORD_OwnerClear ((TPM_COMMAND_CODE) 0x0000005B)
+#define TPM_ORD_OwnerReadInternalPub ((TPM_COMMAND_CODE) 0x00000081)
+#define TPM_ORD_OwnerReadPubek ((TPM_COMMAND_CODE) 0x0000007D)
+#define TPM_ORD_OwnerSetDisable ((TPM_COMMAND_CODE) 0x0000006E)
+#define TPM_ORD_PCR_Reset ((TPM_COMMAND_CODE) 0x000000C8)
+#define TPM_ORD_PcrRead ((TPM_COMMAND_CODE) 0x00000015)
+#define TPM_ORD_PhysicalDisable ((TPM_COMMAND_CODE) 0x00000070)
+#define TPM_ORD_PhysicalEnable ((TPM_COMMAND_CODE) 0x0000006F)
+#define TPM_ORD_PhysicalSetDeactivated ((TPM_COMMAND_CODE) 0x00000072)
+#define TPM_ORD_Quote ((TPM_COMMAND_CODE) 0x00000016)
+#define TPM_ORD_Quote2 ((TPM_COMMAND_CODE) 0x0000003E)
+#define TPM_ORD_ReadCounter ((TPM_COMMAND_CODE) 0x000000DE)
+#define TPM_ORD_ReadManuMaintPub ((TPM_COMMAND_CODE) 0x00000030)
+#define TPM_ORD_ReadPubek ((TPM_COMMAND_CODE) 0x0000007C)
+#define TPM_ORD_ReleaseCounter ((TPM_COMMAND_CODE) 0x000000DF)
+#define TPM_ORD_ReleaseCounterOwner ((TPM_COMMAND_CODE) 0x000000E0)
+#define TPM_ORD_ReleaseTransportSigned ((TPM_COMMAND_CODE) 0x000000E8)
+#define TPM_ORD_Reset ((TPM_COMMAND_CODE) 0x0000005A)
+#define TPM_ORD_ResetLockValue ((TPM_COMMAND_CODE) 0x00000040)
+#define TPM_ORD_RevokeTrust ((TPM_COMMAND_CODE) 0x00000080)
+#define TPM_ORD_SaveAuthContext ((TPM_COMMAND_CODE) 0x000000B6)
+#define TPM_ORD_SaveContext ((TPM_COMMAND_CODE) 0x000000B8)
+#define TPM_ORD_SaveKeyContext ((TPM_COMMAND_CODE) 0x000000B4)
+#define TPM_ORD_SaveState ((TPM_COMMAND_CODE) 0x00000098)
+#define TPM_ORD_Seal ((TPM_COMMAND_CODE) 0x00000017)
+#define TPM_ORD_Sealx ((TPM_COMMAND_CODE) 0x0000003D)
+#define TPM_ORD_SelfTestFull ((TPM_COMMAND_CODE) 0x00000050)
+#define TPM_ORD_SetCapability ((TPM_COMMAND_CODE) 0x0000003F)
+#define TPM_ORD_SetOperatorAuth ((TPM_COMMAND_CODE) 0x00000074)
+#define TPM_ORD_SetOrdinalAuditStatus ((TPM_COMMAND_CODE) 0x0000008D)
+#define TPM_ORD_SetOwnerInstall ((TPM_COMMAND_CODE) 0x00000071)
+#define TPM_ORD_SetOwnerPointer ((TPM_COMMAND_CODE) 0x00000075)
+#define TPM_ORD_SetRedirection ((TPM_COMMAND_CODE) 0x0000009A)
+#define TPM_ORD_SetTempDeactivated ((TPM_COMMAND_CODE) 0x00000073)
+#define TPM_ORD_SHA1Complete ((TPM_COMMAND_CODE) 0x000000A2)
+#define TPM_ORD_SHA1CompleteExtend ((TPM_COMMAND_CODE) 0x000000A3)
+#define TPM_ORD_SHA1Start ((TPM_COMMAND_CODE) 0x000000A0)
+#define TPM_ORD_SHA1Update ((TPM_COMMAND_CODE) 0x000000A1)
+#define TPM_ORD_Sign ((TPM_COMMAND_CODE) 0x0000003C)
+#define TPM_ORD_Startup ((TPM_COMMAND_CODE) 0x00000099)
+#define TPM_ORD_StirRandom ((TPM_COMMAND_CODE) 0x00000047)
+#define TPM_ORD_TakeOwnership ((TPM_COMMAND_CODE) 0x0000000D)
+#define TPM_ORD_Terminate_Handle ((TPM_COMMAND_CODE) 0x00000096)
+#define TPM_ORD_TickStampBlob ((TPM_COMMAND_CODE) 0x000000F2)
+#define TPM_ORD_UnBind ((TPM_COMMAND_CODE) 0x0000001E)
+#define TPM_ORD_Unseal ((TPM_COMMAND_CODE) 0x00000018)
+#define TSC_ORD_PhysicalPresence ((TPM_COMMAND_CODE) 0x4000000A)
+#define TSC_ORD_ResetEstablishmentBit ((TPM_COMMAND_CODE) 0x4000000B)
+
+//
+// Part 2, section 18: Context structures
+//
+
+typedef struct tdTPM_CONTEXT_BLOB
+{
+ TPM_STRUCTURE_TAG tag;
+ TPM_RESOURCE_TYPE resourceType;
+ TPM_HANDLE handle;
+ UINT8 label[16];
+ UINT32 contextCount;
+ TPM_DIGEST integrityDigest;
+ UINT32 additionalSize;
+ UINT8 *additionalData;
+ UINT32 sensitiveSize;
+ UINT8 *sensitiveData;
+} TPM_CONTEXT_BLOB;
+
+typedef struct tdTPM_CONTEXT_SENSITIVE
+{
+ TPM_STRUCTURE_TAG tag;
+ TPM_NONCE contextNonce;
+ UINT32 internalSize;
+ UINT8 *internalData;
+} TPM_CONTEXT_SENSITIVE;
+
+//
+// Part 2, section 19: NV Structures
+//
+
+#define TPM_NV_INDEX_LOCK ((UINT32)0xffffffff)
+#define TPM_NV_INDEX0 ((UINT32)0x00000000)
+#define TPM_NV_INDEX_DIR ((UINT32)0x10000001)
+#define TPM_NV_INDEX_EKCert ((UINT32)0x0000f000)
+#define TPM_NV_INDEX_TPM_CC ((UINT32)0x0000f001)
+#define TPM_NV_INDEX_PlatformCert ((UINT32)0x0000f002)
+#define TPM_NV_INDEX_Platform_CC ((UINT32)0x0000f003)
+// The following define ranges of reserved indices.
+#define TPM_NV_INDEX_TSS_BASE ((UINT32)0x00011100)
+#define TPM_NV_INDEX_PC_BASE ((UINT32)0x00011200)
+#define TPM_NV_INDEX_SERVER_BASE ((UINT32)0x00011300)
+#define TPM_NV_INDEX_MOBILE_BASE ((UINT32)0x00011400)
+#define TPM_NV_INDEX_PERIPHERAL_BASE ((UINT32)0x00011500)
+#define TPM_NV_INDEX_GROUP_RESV_BASE ((UINT32)0x00010000)
+
+typedef UINT32 TPM_NV_PER_ATTRIBUTES;
+// The typedefs TPM_NV_PER_ATTRIBUTES (not present in TPM 1.2 Spec. have been added
+// and structure fields that were to hold the following values
+#define TPM_NV_PER_READ_STCLEAR (((UINT32)1)<<31)
+#define TPM_NV_PER_AUTHREAD (((UINT32)1)<<18)
+#define TPM_NV_PER_OWNERREAD (((UINT32)1)<<17)
+#define TPM_NV_PER_PPREAD (((UINT32)1)<<16)
+#define TPM_NV_PER_GLOBALLOCK (((UINT32)1)<<15)
+#define TPM_NV_PER_WRITE_STCLEAR (((UINT32)1)<<14)
+#define TPM_NV_PER_WRITEDEFINE (((UINT32)1)<<13)
+#define TPM_NV_PER_WRITEALL (((UINT32)1)<<12)
+#define TPM_NV_PER_AUTHWRITE (((UINT32)1)<<2)
+#define TPM_NV_PER_OWNERWRITE (((UINT32)1)<<1)
+#define TPM_NV_PER_PPWRITE (((UINT32)1)<<0)
+
+typedef struct tdTPM_NV_ATTRIBUTES
+{
+ TPM_STRUCTURE_TAG tag;
+ TPM_NV_PER_ATTRIBUTES attributes;
+} TPM_NV_ATTRIBUTES;
+
+
+typedef struct tdTPM_NV_DATA_PUBLIC
+{
+ TPM_STRUCTURE_TAG tag;
+ TPM_NV_INDEX nvIndex;
+ TPM_PCR_INFO_SHORT pcrInfoRead;
+ TPM_PCR_INFO_SHORT pcrInfoWrite;
+ TPM_NV_ATTRIBUTES permission;
+ BOOLEAN bReadSTClear;
+ BOOLEAN bWriteSTClear;
+ BOOLEAN bWriteDefine;
+ UINT32 dataSize;
+} TPM_NV_DATA_PUBLIC;
+
+
+
+// Internal to TPM:
+//typedef struct tdTPM_NV_DATA_SENSITIVE
+//{
+// TPM_STRUCTURE_TAG tag;
+// TPM_NV_DATA_PUBLIC pubInfo;
+// TPM_AUTHDATA authValue;
+// UINT8 *data;
+//} TPM_NV_DATA_SENSITIVE;
+
+
+//
+// Part 2, section 20: Delegation
+//
+
+//
+// Part 2, section 20.3: Owner Permissions Settings for per1 bits
+//
+#define TPM_DELEGATE_SetOrdinalAuditStatus (((UINT32)1)<<30)
+#define TPM_DELEGATE_DirWriteAuth (((UINT32)1)<<29)
+#define TPM_DELEGATE_CMK_ApproveMA (((UINT32)1)<<28)
+#define TPM_DELEGATE_CMK_CreateTicket (((UINT32)1)<<26)
+#define TPM_DELEGATE_Delegate_LoadOwnerDelegation (((UINT32)1)<<24)
+#define TPM_DELEGATE_DAA_Join (((UINT32)1)<<23)
+#define TPM_DELEGATE_AuthorizeMigrationKey (((UINT32)1)<<22)
+#define TPM_DELEGATE_CreateMaintenanceArchive (((UINT32)1)<<21)
+#define TPM_DELEGATE_LoadMaintenanceArchive (((UINT32)1)<<20)
+#define TPM_DELEGATE_KillMaintenanceFeature (((UINT32)1)<<19)
+#define TPM_DELEGATE_OwnerReadInteralPub (((UINT32)1)<<18)
+#define TPM_DELEGATE_ResetLockValue (((UINT32)1)<<17)
+#define TPM_DELEGATE_OwnerClear (((UINT32)1)<<16)
+#define TPM_DELEGATE_DisableOwnerClear (((UINT32)1)<<15)
+#define TPM_DELEGATE_OwnerSetDisable (((UINT32)1)<<13)
+#define TPM_DELEGATE_SetCapability (((UINT32)1)<<12)
+#define TPM_DELEGATE_MakeIdentity (((UINT32)1)<<11)
+#define TPM_DELEGATE_ActivateIdentity (((UINT32)1)<<10)
+#define TPM_DELEGATE_OwnerReadPubek (((UINT32)1)<<9)
+#define TPM_DELEGATE_DisablePubekRead (((UINT32)1)<<8)
+#define TPM_DELEGATE_SetRedirection (((UINT32)1)<<7)
+#define TPM_DELEGATE_FieldUpgrade (((UINT32)1)<<6)
+#define TPM_DELEGATE_Delegate_UpdateVerification (((UINT32)1)<<5)
+#define TPM_DELEGATE_CreateCounter (((UINT32)1)<<4)
+#define TPM_DELEGATE_ReleaseCounterOwner (((UINT32)1)<<3)
+#define TPM_DELEGATE_DelegateManage (((UINT32)1)<<2)
+#define TPM_DELEGATE_Delegate_CreateOwnerDelegation (((UINT32)1)<<1)
+#define TPM_DELEGATE_DAA_Sign (((UINT32)1)<<0)
+
+//
+// Part 2, section 20.3: Key Permissions Settings for per1 bits
+//
+#define TPM_KEY_DELEGATE_CMK_ConvertMigration (((UINT32)1)<<28)
+#define TPM_KEY_DELEGATE_TickStampBlob (((UINT32)1)<<27)
+#define TPM_KEY_DELEGATE_ChangeAuthAsymStart (((UINT32)1)<<26)
+#define TPM_KEY_DELEGATE_ChangeAuthAsymFinish (((UINT32)1)<<25)
+#define TPM_KEY_DELEGATE_CMK_CreateKey (((UINT32)1)<<24)
+#define TPM_KEY_DELEGATE_MigrateKey (((UINT32)1)<<23)
+#define TPM_KEY_DELEGATE_LoadKey2 (((UINT32)1)<<22)
+#define TPM_KEY_DELEGATE_EstablishTransport (((UINT32)1)<<21)
+#define TPM_KEY_DELEGATE_ReleaseTransportSigned (((UINT32)1)<<20)
+#define TPM_KEY_DELEGATE_Quote2 (((UINT32)1)<<19)
+#define TPM_KEY_DELEGATE_Sealx (((UINT32)1)<<18)
+#define TPM_KEY_DELEGATE_MakeIdentity (((UINT32)1)<<17)
+#define TPM_KEY_DELEGATE_ActivateIdentity (((UINT32)1)<<16)
+#define TPM_KEY_DELEGATE_GetAuditDigestSigned (((UINT32)1)<<15)
+#define TPM_KEY_DELEGATE_Sign (((UINT32)1)<<14)
+#define TPM_KEY_DELEGATE_CertifyKey2 (((UINT32)1)<<13)
+#define TPM_KEY_DELEGATE_CertifyKey (((UINT32)1)<<12)
+#define TPM_KEY_DELEGATE_CreateWrapKey (((UINT32)1)<<11)
+#define TPM_KEY_DELEGATE_CMK_CreateBlob (((UINT32)1)<<10)
+#define TPM_KEY_DELEGATE_CreateMigrationBlob (((UINT32)1)<<9)
+#define TPM_KEY_DELEGATE_ConvertMigrationBlob (((UINT32)1)<<8)
+#define TPM_KEY_DELEGATE_CreateKeyDelegation (((UINT32)1)<<7)
+#define TPM_KEY_DELEGATE_ChangeAuth (((UINT32)1)<<6)
+#define TPM_KEY_DELEGATE_GetPubKey (((UINT32)1)<<5)
+#define TPM_KEY_DELEGATE_UnBind (((UINT32)1)<<4)
+#define TPM_KEY_DELEGATE_Quote (((UINT32)1)<<3)
+#define TPM_KEY_DELEGATE_Unseal (((UINT32)1)<<2)
+#define TPM_KEY_DELEGATE_Seal (((UINT32)1)<<1)
+#define TPM_KEY_DELEGATE_LoadKey (((UINT32)1)<<0)
+
+#define TPM_FAMILY_CREATE ((UINT32)0x00000001)
+#define TPM_FAMILY_ENABLE ((UINT32)0x00000002)
+#define TPM_FAMILY_ADMIN ((UINT32)0x00000003)
+#define TPM_FAMILY_INVALIDATE ((UINT32)0x00000004)
+
+#define TPM_FAMFLAG_DELEGATE_ADMIN_LOCK (((UINT32)1)<<1)
+#define TPM_FAMFLAG_ENABLE (((UINT32)1)<<0)
+
+typedef struct tdTPM_FAMILY_LABEL
+{
+ UINT8 label;
+} TPM_FAMILY_LABEL;
+
+typedef struct tdTPM_FAMILY_TABLE_ENTRY
+{
+ TPM_STRUCTURE_TAG tag;
+ TPM_FAMILY_LABEL label;
+ TPM_FAMILY_ID familyID;
+ TPM_FAMILY_VERIFICATION verificationCount;
+ TPM_FAMILY_FLAGS flags;
+} TPM_FAMILY_TABLE_ENTRY;
+
+#define TPM_FAMILY_TABLE_ENTRY_MIN 8
+//typedef struct tdTPM_FAMILY_TABLE
+//{
+// TPM_FAMILY_TABLE_ENTRY FamTableRow[TPM_NUM_FAMILY_TABLE_ENTRY_MIN];
+//} TPM_FAMILY_TABLE;
+
+
+typedef struct tdTPM_DELEGATE_LABEL
+{
+ UINT8 label;
+} TPM_DELEGATE_LABEL;
+
+
+typedef UINT32 TPM_DELEGATE_TYPE;
+#define TPM_DEL_OWNER_BITS ((UINT32)0x00000001)
+#define TPM_DEL_KEY_BITS ((UINT32)0x00000002)
+
+typedef struct tdTPM_DELEGATIONS
+{
+ TPM_STRUCTURE_TAG tag;
+ TPM_DELEGATE_TYPE delegateType;
+ UINT32 per1;
+ UINT32 per2;
+} TPM_DELEGATIONS;
+
+typedef struct tdTPM_DELEGATE_PUBLIC
+{
+ TPM_STRUCTURE_TAG tag;
+ TPM_DELEGATE_LABEL label;
+ TPM_PCR_INFO_SHORT pcrInfo;
+ TPM_DELEGATIONS permissions;
+ TPM_FAMILY_ID familyID;
+ TPM_FAMILY_VERIFICATION verificationCount;
+} TPM_DELEGATE_PUBLIC;
+
+typedef struct tdTPM_DELEGATE_TABLE_ROW
+{
+ TPM_STRUCTURE_TAG tag;
+ TPM_DELEGATE_PUBLIC pub;
+ TPM_SECRET authValue;
+} TPM_DELEGATE_TABLE_ROW;
+
+
+#define TPM_NUM_DELEGATE_TABLE_ENTRY_MIN 2
+//typedef struct tdTPM_DELEGATE_TABLE
+//{
+// TPM_DELEGATE_TABLE_ROW delRow[TPM_NUM_DELEGATE_TABLE_ENTRY_MIN];
+//} TPM_DELEGATE_TABLE;
+
+typedef struct tdTPM_DELEGATE_SENSITIVE
+{
+ TPM_STRUCTURE_TAG tag;
+ TPM_SECRET authValue;
+} TPM_DELEGATE_SENSITIVE;
+
+typedef struct tdTPM_DELEGATE_OWNER_BLOB
+{
+ TPM_STRUCTURE_TAG tag;
+ TPM_DELEGATE_PUBLIC pub;
+ TPM_DIGEST integrityDigest;
+ UINT32 additionalSize;
+ UINT8 *additionalArea;
+ UINT32 sensitiveSize;
+ UINT8 *sensitiveArea;
+} TPM_DELEGATE_OWNER_BLOB;
+
+typedef struct tdTPM_DELEGATE_KEY_BLOB
+{
+ TPM_STRUCTURE_TAG tag;
+ TPM_DELEGATE_PUBLIC pub;
+ TPM_DIGEST integrityDigest;
+ TPM_DIGEST pubKeyDigest;
+ UINT32 additionalSize;
+ UINT8 *additionalArea;
+ UINT32 sensitiveSize;
+ UINT8 *sensitiveArea;
+} TPM_DELEGATE_KEY_BLOB;
+
+//
+// Part 2, section 21.1: TPM_CAPABILITY_AREA for GetCapability
+//
+#define TPM_CAP_ORD ((TPM_CAPABILITY_AREA) 0x00000001)
+#define TPM_CAP_ALG ((TPM_CAPABILITY_AREA) 0x00000002)
+#define TPM_CAP_PID ((TPM_CAPABILITY_AREA) 0x00000003)
+#define TPM_CAP_FLAG ((TPM_CAPABILITY_AREA) 0x00000004)
+#define TPM_CAP_PROPERTY ((TPM_CAPABILITY_AREA) 0x00000005)
+#define TPM_CAP_VERSION ((TPM_CAPABILITY_AREA) 0x00000006)
+#define TPM_CAP_KEY_HANDLE ((TPM_CAPABILITY_AREA) 0x00000007)
+#define TPM_CAP_CHECK_LOADED ((TPM_CAPABILITY_AREA) 0x00000008)
+#define TPM_CAP_SYM_MODE ((TPM_CAPABILITY_AREA) 0x00000009)
+#define TPM_CAP_KEY_STATUS ((TPM_CAPABILITY_AREA) 0x0000000C)
+#define TPM_CAP_NV_LIST ((TPM_CAPABILITY_AREA) 0x0000000D)
+#define TPM_CAP_MFR ((TPM_CAPABILITY_AREA) 0x00000010)
+#define TPM_CAP_NV_INDEX ((TPM_CAPABILITY_AREA) 0x00000011)
+#define TPM_CAP_TRANS_ALG ((TPM_CAPABILITY_AREA) 0x00000012)
+#define TPM_CAP_HANDLE ((TPM_CAPABILITY_AREA) 0x00000014)
+#define TPM_CAP_TRANS_ES ((TPM_CAPABILITY_AREA) 0x00000015)
+#define TPM_CAP_AUTH_ENCRYPT ((TPM_CAPABILITY_AREA) 0x00000017)
+#define TPM_CAP_SELECT_SIZE ((TPM_CAPABILITY_AREA) 0x00000018)
+#define TPM_CAP_VERSION_VAL ((TPM_CAPABILITY_AREA) 0x0000001A)
+
+#define TPM_CAP_FLAG_PERMANENT ((TPM_CAPABILITY_AREA) 0x00000108)
+#define TPM_CAP_FLAG_VOLATILE ((TPM_CAPABILITY_AREA) 0x00000109)
+
+//
+// Part 2, section 21.2: CAP_PROPERTY Subcap values for GetCapability
+//
+#define TPM_CAP_PROP_PCR ((TPM_CAPABILITY_AREA) 0x00000101)
+#define TPM_CAP_PROP_DIR ((TPM_CAPABILITY_AREA) 0x00000102)
+#define TPM_CAP_PROP_MANUFACTURER ((TPM_CAPABILITY_AREA) 0x00000103)
+#define TPM_CAP_PROP_KEYS ((TPM_CAPABILITY_AREA) 0x00000104)
+#define TPM_CAP_PROP_MIN_COUNTER ((TPM_CAPABILITY_AREA) 0x00000107)
+#define TPM_CAP_PROP_AUTHSESS ((TPM_CAPABILITY_AREA) 0x0000010A)
+#define TPM_CAP_PROP_TRANSESS ((TPM_CAPABILITY_AREA) 0x0000010B)
+#define TPM_CAP_PROP_COUNTERS ((TPM_CAPABILITY_AREA) 0x0000010C)
+#define TPM_CAP_PROP_MAX_AUTHSESS ((TPM_CAPABILITY_AREA) 0x0000010D)
+#define TPM_CAP_PROP_MAX_TRANSESS ((TPM_CAPABILITY_AREA) 0x0000010E)
+#define TPM_CAP_PROP_MAX_COUNTERS ((TPM_CAPABILITY_AREA) 0x0000010F)
+#define TPM_CAP_PROP_MAX_KEYS ((TPM_CAPABILITY_AREA) 0x00000110)
+#define TPM_CAP_PROP_OWNER ((TPM_CAPABILITY_AREA) 0x00000111)
+#define TPM_CAP_PROP_CONTEXT ((TPM_CAPABILITY_AREA) 0x00000112)
+#define TPM_CAP_PROP_MAX_CONTEXT ((TPM_CAPABILITY_AREA) 0x00000113)
+#define TPM_CAP_PROP_FAMILYROWS ((TPM_CAPABILITY_AREA) 0x00000114)
+#define TPM_CAP_PROP_TIS_TIMEOUT ((TPM_CAPABILITY_AREA) 0x00000115)
+#define TPM_CAP_PROP_STARTUP_EFFECT ((TPM_CAPABILITY_AREA) 0x00000116)
+#define TPM_CAP_PROP_DELEGATE_ROW ((TPM_CAPABILITY_AREA) 0x00000117)
+#define TPM_CAP_PROP_DAA_MAX ((TPM_CAPABILITY_AREA) 0x00000119)
+#define CAP_PROP_SESSION_DAA ((TPM_CAPABILITY_AREA) 0x0000011A)
+#define TPM_CAP_PROP_CONTEXT_DIST ((TPM_CAPABILITY_AREA) 0x0000011B)
+#define TPM_CAP_PROP_DAA_INTERRUPT ((TPM_CAPABILITY_AREA) 0x0000011C)
+#define TPM_CAP_PROP_SESSIONS ((TPM_CAPABILITY_AREA) 0x0000011D)
+#define TPM_CAP_PROP_MAX_SESSIONS ((TPM_CAPABILITY_AREA) 0x0000011E)
+#define TPM_CAP_PROP_CMK_RESTRICTION ((TPM_CAPABILITY_AREA) 0x0000011F)
+#define TPM_CAP_PROP_DURATION ((TPM_CAPABILITY_AREA) 0x00000120)
+#define TPM_CAP_PROP_ACTIVE_COUNTER ((TPM_CAPABILITY_AREA) 0x00000122)
+#define TPM_CAP_PROP_MAX_NV_AVAILABLE ((TPM_CAPABILITY_AREA) 0x00000123)
+#define TPM_CAP_PROP_INPUT_BUFFER ((TPM_CAPABILITY_AREA) 0x00000124)
+
+//
+// Part 2, section 21.6: TPM_CAP_VERSION_INFO
+// [size_is(vendorSpecificSize)] BYTE* vendorSpecific;
+//
+typedef struct tdTPM_CAP_VERSION_INFO {
+ TPM_STRUCTURE_TAG tag;
+ TPM_VERSION version;
+ UINT16 specLevel;
+ UINT8 errataRev;
+ UINT8 tpmVendorID[4];
+ UINT16 vendorSpecificSize;
+ UINT8 *vendorSpecific;
+} TPM_CAP_VERSION_INFO;
+
+//
+// Part 2, section 22: DAA Structures
+//
+
+#define TPM_DAA_SIZE_r0 (43)
+#define TPM_DAA_SIZE_r1 (43)
+#define TPM_DAA_SIZE_r2 (128)
+#define TPM_DAA_SIZE_r3 (168)
+#define TPM_DAA_SIZE_r4 (219)
+#define TPM_DAA_SIZE_NT (20)
+#define TPM_DAA_SIZE_v0 (128)
+#define TPM_DAA_SIZE_v1 (192)
+#define TPM_DAA_SIZE_NE (256)
+#define TPM_DAA_SIZE_w (256)
+#define TPM_DAA_SIZE_issuerModulus (256)
+#define TPM_DAA_power0 (104)
+#define TPM_DAA_power1 (1024)
+
+typedef struct tdTPM_DAA_ISSUER
+{
+ TPM_STRUCTURE_TAG tag;
+ TPM_DIGEST DAA_digest_R0;
+ TPM_DIGEST DAA_digest_R1;
+ TPM_DIGEST DAA_digest_S0;
+ TPM_DIGEST DAA_digest_S1;
+ TPM_DIGEST DAA_digest_n;
+ TPM_DIGEST DAA_digest_gamma;
+ UINT8 DAA_generic_q[26];
+} TPM_DAA_ISSUER;
+
+
+typedef struct tdTPM_DAA_TPM
+{
+ TPM_STRUCTURE_TAG tag;
+ TPM_DIGEST DAA_digestIssuer;
+ TPM_DIGEST DAA_digest_v0;
+ TPM_DIGEST DAA_digest_v1;
+ TPM_DIGEST DAA_rekey;
+ UINT32 DAA_count;
+} TPM_DAA_TPM;
+
+typedef struct tdTPM_DAA_CONTEXT
+{
+ TPM_STRUCTURE_TAG tag;
+ TPM_DIGEST DAA_digestContext;
+ TPM_DIGEST DAA_digest;
+ TPM_DAA_CONTEXT_SEED DAA_contextSeed;
+ UINT8 DAA_scratch[256];
+ UINT8 DAA_stage;
+} TPM_DAA_CONTEXT;
+
+typedef struct tdTPM_DAA_JOINDATA
+{
+ UINT8 DAA_join_u0[128];
+ UINT8 DAA_join_u1[138];
+ TPM_DIGEST DAA_digest_n0;
+} TPM_DAA_JOINDATA;
+
+typedef struct tdTPM_DAA_BLOB
+{
+ TPM_STRUCTURE_TAG tag;
+ TPM_RESOURCE_TYPE resourceType;
+ UINT8 label[16];
+ TPM_DIGEST blobIntegrity;
+ UINT32 additionalSize;
+ UINT8 *additionalData;
+ UINT32 sensitiveSize;
+ UINT8 *sensitiveData;
+} TPM_DAA_BLOB;
+
+typedef struct tdTPM_DAA_SENSITIVE
+{
+ TPM_STRUCTURE_TAG tag;
+ UINT32 internalSize;
+ UINT8 *internalData;
+} TPM_DAA_SENSITIVE;
+
+
+//
+// Part 2, section 23: Redirection
+//
+
+// This section of the TPM spec defines exactly one value but does not
+// give it a name. The definition of TPM_SetRedirection in Part3
+// refers to exactly one name but does not give its value. We join
+// them here.
+#define TPM_REDIR_GPIO (0x00000001)
+
+//
+// TPM Command & Response Headers
+//
+typedef struct tdTPM_RQU_COMMAND_HDR {
+ TPM_STRUCTURE_TAG tag;
+ UINT32 paramSize;
+ TPM_COMMAND_CODE ordinal;
+} TPM_RQU_COMMAND_HDR;
+
+typedef struct tdTPM_RSP_COMMAND_HDR {
+ TPM_STRUCTURE_TAG tag;
+ UINT32 paramSize;
+ TPM_RESULT returnCode;
+} TPM_RSP_COMMAND_HDR;
+
+#pragma pack (pop)
+
+#endif // _TPM12_H_
diff --git a/EdkCompatibilityPkg/Foundation/Include/IndustryStandard/WatchdogDescriptionTable.h b/EdkCompatibilityPkg/Foundation/Include/IndustryStandard/WatchdogDescriptionTable.h new file mode 100644 index 0000000000..8a23e7e07e --- /dev/null +++ b/EdkCompatibilityPkg/Foundation/Include/IndustryStandard/WatchdogDescriptionTable.h @@ -0,0 +1,94 @@ +/*++
+
+Copyright (c) 2007, Intel Corporation
+All rights reserved. This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution. The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+Module Name:
+
+ WatchdogDescriptionTable.h
+
+Abstract:
+
+ ACPI Watchdog Description Table as defined in Intel
+ ICH Family Watchdog Timer (WDT) Application Note (AP-725)
+
+--*/
+
+#ifndef _WATCH_DOG_DESCRIPTION_TABLE_H_
+#define _WATCH_DOG_DESCRIPTION_TABLE_H_
+
+//
+// Include files
+//
+#include "Acpi2_0.h"
+
+//
+// Ensure proper structure formats
+//
+#pragma pack(1)
+//
+// WDDT structure
+//
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT16 SpecVersion;
+ UINT16 TableVersion;
+ UINT16 Vid;
+ EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE BaseAddress;
+ UINT16 TimerMaxCount;
+ UINT16 TimerMinCount;
+ UINT16 TimerCountPeriod;
+ UINT16 Status;
+ UINT16 Capability;
+} EFI_ACPI_1_0_WATCH_DOG_DESCRIPTION_TABLE;
+
+//
+// "WDDT" Watchdog Description Table signatures
+//
+#define EFI_ACPI_1_0_WDDT_SIGNATURE 0x54444457
+
+#pragma pack()
+
+//
+// WDDT Revision
+//
+#define EFI_ACPI_WATCHDOG_DESCRIPTION_1_0_TABLE_REVISION 0x01
+
+//
+// WDDT Spec Version
+//
+#define EFI_ACPI_WDDT_SPEC_1_0_VERSION 0x01
+
+//
+// WDDT Description Table Version
+//
+#define EFI_ACPI_WDDT_TABLE_1_0_VERSION 0x01
+
+//
+// WDT Status
+//
+#define EFI_ACPI_WDDT_STATUS_AVAILABLE 0x0001
+#define EFI_ACPI_WDDT_STATUS_ACTIVE 0x0002
+#define EFI_ACPI_WDDT_STATUS_OWNED_BY_BIOS 0x0000
+#define EFI_ACPI_WDDT_STATUS_OWNED_BY_OS 0x0004
+#define EFI_ACPI_WDDT_STATUS_USER_RESET_EVENT 0x0800
+#define EFI_ACPI_WDDT_STATUS_WDT_EVENT 0x1000
+#define EFI_ACPI_WDDT_STATUS_POWER_FAIL_EVENT 0x2000
+#define EFI_ACPI_WDDT_STATUS_UNKNOWN_RESET_EVENT 0x4000
+
+//
+// WDT Capability
+//
+#define EFI_ACPI_WDDT_CAPABILITY_AUTO_RESET 0x0001
+#define EFI_ACPI_WDDT_CAPABILITY_ALERT_SUPPORT 0x0002
+#define EFI_ACPI_WDDT_CAPABILITY_PLATFORM_SHUTDOWN 0x0004
+#define EFI_ACPI_WDDT_CAPABILITY_IMMEDIATE_SHUTDOWN 0x0008
+#define EFI_ACPI_WDDT_CAPABILITY_BIOS_HANDOFF_SUPPORT 0x0010
+
+#endif
diff --git a/EdkCompatibilityPkg/Foundation/Include/IndustryStandard/atapi.h b/EdkCompatibilityPkg/Foundation/Include/IndustryStandard/atapi.h new file mode 100644 index 0000000000..3fcc287a5a --- /dev/null +++ b/EdkCompatibilityPkg/Foundation/Include/IndustryStandard/atapi.h @@ -0,0 +1,331 @@ +/*++
+
+Copyright (c) 2007, Intel Corporation
+All rights reserved. This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution. The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+Module Name:
+
+ Atapi.h
+
+Abstract:
+
+
+Revision History
+--*/
+
+#ifndef _ATAPI_H
+#define _ATAPI_H
+
+#include "Tiano.h"
+
+#pragma pack(1)
+
+typedef struct {
+ UINT16 config; /* General Configuration */
+ UINT16 cylinders; /* Number of Cylinders */
+ UINT16 reserved_2;
+ UINT16 heads; /* Number of logical heads */
+ UINT16 vendor_data1;
+ UINT16 vendoe_data2;
+ UINT16 sectors_per_track;
+ UINT16 vendor_specific_7_9[3];
+ CHAR8 SerialNo[20]; /* ASCII */
+ UINT16 vendor_specific_20_21[2];
+ UINT16 ecc_bytes_available;
+ CHAR8 FirmwareVer[8]; /* ASCII */
+ CHAR8 ModelName[40]; /* ASCII */
+ UINT16 multi_sector_cmd_max_sct_cnt;
+ UINT16 reserved_48;
+ UINT16 capabilities;
+ UINT16 reserved_50;
+ UINT16 pio_cycle_timing;
+ UINT16 reserved_52;
+ UINT16 field_validity;
+ UINT16 current_cylinders;
+ UINT16 current_heads;
+ UINT16 current_sectors;
+ UINT16 CurrentCapacityLsb;
+ UINT16 CurrentCapacityMsb;
+ UINT16 reserved_59;
+ UINT16 user_addressable_sectors_lo;
+ UINT16 user_addressable_sectors_hi;
+ UINT16 reserved_62;
+ UINT16 multi_word_dma_mode;
+ UINT16 advanced_pio_modes;
+ UINT16 min_multi_word_dma_cycle_time;
+ UINT16 rec_multi_word_dma_cycle_time;
+ UINT16 min_pio_cycle_time_without_flow_control;
+ UINT16 min_pio_cycle_time_with_flow_control;
+ UINT16 reserved_69_79[11];
+ UINT16 major_version_no;
+ UINT16 minor_version_no;
+ UINT16 reserved_82_127[46];
+ UINT16 security_status;
+ UINT16 vendor_data_129_159[31];
+ UINT16 reserved_160_255[96];
+} IDENTIFY;
+
+typedef struct {
+ UINT8 peripheral_type;
+ UINT8 RMB;
+ UINT8 version;
+ UINT8 response_data_format;
+ UINT8 addnl_length;
+ UINT8 reserved_5;
+ UINT8 reserved_6;
+ UINT8 reserved_7;
+ UINT8 vendor_info[8];
+ UINT8 product_id[12];
+ UINT8 eeprom_product_code[4];
+ UINT8 firmware_rev_level[4];
+ UINT8 firmware_sub_rev_level[1];
+ UINT8 reserved_37;
+ UINT8 reserved_38;
+ UINT8 reserved_39;
+ UINT8 max_capacity_hi;
+ UINT8 max_capacity_mid;
+ UINT8 max_capacity_lo;
+ UINT8 reserved_43_95[95 - 43 + 1];
+ UINT8 vendor_id[20];
+ UINT8 eeprom_drive_sno[12];
+} INQUIRY_DATA;
+
+typedef struct {
+ UINT8 error_code : 7;
+ UINT8 valid : 1;
+ UINT8 reserved_1;
+ UINT8 sense_key : 4;
+ UINT8 reserved_21 : 1;
+ UINT8 ILI : 1;
+ UINT8 reserved_22 : 2;
+ UINT8 vendor_specific_3;
+ UINT8 vendor_specific_4;
+ UINT8 vendor_specific_5;
+ UINT8 vendor_specific_6;
+ UINT8 addnl_sense_length; // n - 7
+ UINT8 vendor_specific_8;
+ UINT8 vendor_specific_9;
+ UINT8 vendor_specific_10;
+ UINT8 vendor_specific_11;
+ UINT8 addnl_sense_code; // mandatory
+ UINT8 addnl_sense_code_qualifier; // mandatory
+ UINT8 field_replaceable_unit_code; // optional
+ UINT8 reserved_15;
+ UINT8 reserved_16;
+ UINT8 reserved_17;
+ //
+ // Followed by additional sense bytes : FIXME
+ //
+} REQUEST_SENSE_DATA;
+
+typedef struct {
+ UINT8 LastLba3;
+ UINT8 LastLba2;
+ UINT8 LastLba1;
+ UINT8 LastLba0;
+ UINT8 BlockSize3;
+ UINT8 BlockSize2;
+ UINT8 BlockSize1;
+ UINT8 BlockSize0;
+} READ_CAPACITY_DATA;
+
+typedef struct {
+ UINT8 reserved_0;
+ UINT8 reserved_1;
+ UINT8 reserved_2;
+ UINT8 Capacity_Length;
+ UINT8 LastLba3;
+ UINT8 LastLba2;
+ UINT8 LastLba1;
+ UINT8 LastLba0;
+ UINT8 DesCode : 2;
+ UINT8 reserved_9 : 6;
+ UINT8 BlockSize2;
+ UINT8 BlockSize1;
+ UINT8 BlockSize0;
+} READ_FORMAT_CAPACITY_DATA;
+
+#pragma pack()
+//
+// ATAPI Command
+//
+#define ATAPI_SOFT_RESET_CMD 0x08
+#define PACKET_CMD 0xA0
+#define ATAPI_IDENTIFY_DEVICE_CMD 0xA1
+#define ATAPI_SERVICE_CMD 0xA2
+
+//
+// ATAPI Packet Command
+//
+#pragma pack(1)
+
+typedef struct {
+ UINT8 opcode;
+ UINT8 reserved_1;
+ UINT8 reserved_2;
+ UINT8 reserved_3;
+ UINT8 reserved_4;
+ UINT8 reserved_5;
+ UINT8 reserved_6;
+ UINT8 reserved_7;
+ UINT8 reserved_8;
+ UINT8 reserved_9;
+ UINT8 reserved_10;
+ UINT8 reserved_11;
+} TEST_UNIT_READY_CMD;
+
+typedef struct {
+ UINT8 opcode;
+ UINT8 reserved_1 : 4;
+ UINT8 lun : 4;
+ UINT8 page_code;
+ UINT8 reserved_3;
+ UINT8 allocation_length;
+ UINT8 reserved_5;
+ UINT8 reserved_6;
+ UINT8 reserved_7;
+ UINT8 reserved_8;
+ UINT8 reserved_9;
+ UINT8 reserved_10;
+ UINT8 reserved_11;
+} INQUIRY_CMD;
+
+typedef struct {
+ UINT8 opcode;
+ UINT8 reserved_1 : 4;
+ UINT8 lun : 4;
+ UINT8 reserved_2;
+ UINT8 reserved_3;
+ UINT8 allocation_length;
+ UINT8 reserved_5;
+ UINT8 reserved_6;
+ UINT8 reserved_7;
+ UINT8 reserved_8;
+ UINT8 reserved_9;
+ UINT8 reserved_10;
+ UINT8 reserved_11;
+} REQUEST_SENSE_CMD;
+
+typedef struct {
+ UINT8 opcode;
+ UINT8 reserved_1 : 5;
+ UINT8 lun : 3;
+ UINT8 Lba0;
+ UINT8 Lba1;
+ UINT8 Lba2;
+ UINT8 Lba3;
+ UINT8 reserved_6;
+ UINT8 TranLen0;
+ UINT8 TranLen1;
+ UINT8 reserved_9;
+ UINT8 reserved_10;
+ UINT8 reserved_11;
+} READ10_CMD;
+
+typedef struct {
+ UINT8 opcode;
+ UINT8 reserved_1;
+ UINT8 reserved_2;
+ UINT8 reserved_3;
+ UINT8 reserved_4;
+ UINT8 reserved_5;
+ UINT8 reserved_6;
+ UINT8 allocation_length_hi;
+ UINT8 allocation_length_lo;
+ UINT8 reserved_9;
+ UINT8 reserved_10;
+ UINT8 reserved_11;
+} READ_FORMAT_CAP_CMD;
+
+typedef struct {
+ UINT8 peripheral_type;
+ UINT8 RMB;
+ UINT8 version;
+ UINT8 response_data_format;
+ UINT8 addnl_length;
+ UINT8 reserved_5;
+ UINT8 reserved_6;
+ UINT8 reserved_7;
+ UINT8 vendor_info[8];
+ UINT8 product_id[12];
+ UINT8 eeprom_product_code[4];
+ UINT8 firmware_rev_level[4];
+} USB_INQUIRY_DATA;
+
+typedef union {
+ UINT16 Data16[6];
+ TEST_UNIT_READY_CMD TestUnitReady;
+ READ10_CMD Read10;
+ REQUEST_SENSE_CMD RequestSence;
+ INQUIRY_CMD Inquiry;
+ READ_FORMAT_CAP_CMD ReadFormatCapacity;
+} ATAPI_PACKET_COMMAND;
+
+#pragma pack()
+//
+// Packet Command Code
+//
+#define TEST_UNIT_READY 0x00
+#define REQUEST_SENSE 0x03
+#define INQUIRY 0x12
+#define READ_FORMAT_CAPACITY 0x23
+#define READ_CAPACITY 0x25
+#define READ_10 0x28
+
+#define DEFAULT_CTL (0x0a) // default content of device control register, disable INT
+#define DEFAULT_CMD (0xa0)
+
+#define MAX_ATAPI_BYTE_COUNT (0xfffe)
+
+//
+// Sense Key
+//
+#define REQUEST_SENSE_ERROR (0x70)
+#define SK_NO_SENSE (0x0)
+#define SK_RECOVERY_ERROR (0x1)
+#define SK_NOT_READY (0x2)
+#define SK_MEDIUM_ERROR (0x3)
+#define SK_HARDWARE_ERROR (0x4)
+#define SK_ILLEGAL_REQUEST (0x5)
+#define SK_UNIT_ATTENTION (0x6)
+#define SK_DATA_PROTECT (0x7)
+#define SK_BLANK_CHECK (0x8)
+#define SK_VENDOR_SPECIFIC (0x9)
+#define SK_RESERVED_A (0xA)
+#define SK_ABORT (0xB)
+#define SK_RESERVED_C (0xC)
+#define SK_OVERFLOW (0xD)
+#define SK_MISCOMPARE (0xE)
+#define SK_RESERVED_F (0xF)
+
+//
+// Additional Sense Codes
+//
+#define ASC_NOT_READY (0x04)
+#define ASC_MEDIA_ERR1 (0x10)
+#define ASC_MEDIA_ERR2 (0x11)
+#define ASC_MEDIA_ERR3 (0x14)
+#define ASC_MEDIA_ERR4 (0x30)
+#define ASC_MEDIA_UPSIDE_DOWN (0x06)
+#define ASC_INVALID_CMD (0x20)
+#define ASC_LBA_OUT_OF_RANGE (0x21)
+#define ASC_INVALID_FIELD (0x24)
+#define ASC_WRITE_PROTECTED (0x27)
+#define ASC_MEDIA_CHANGE (0x28)
+#define ASC_RESET (0x29) /* Power On Reset or Bus Reset occurred */
+#define ASC_ILLEGAL_FIELD (0x26)
+#define ASC_NO_MEDIA (0x3A)
+#define ASC_ILLEGAL_MODE_FOR_THIS_TRACK (0x64)
+
+//
+// Additional Sense Code Qualifier
+//
+#define ASCQ_IN_PROGRESS (0x01)
+
+#endif
diff --git a/EdkCompatibilityPkg/Foundation/Include/IndustryStandard/pci.h b/EdkCompatibilityPkg/Foundation/Include/IndustryStandard/pci.h new file mode 100644 index 0000000000..aa0668b9dc --- /dev/null +++ b/EdkCompatibilityPkg/Foundation/Include/IndustryStandard/pci.h @@ -0,0 +1,31 @@ +/*++
+
+Copyright (c) 2007, Intel Corporation
+All rights reserved. This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution. The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+Module Name:
+
+ pci.h
+
+Abstract:
+ Support for PCI standard.
+
+Revision History
+
+--*/
+
+#ifndef _PCI_H
+#define _PCI_H
+
+#include "pci22.h"
+#include "pci23.h"
+#include "pci30.h"
+#include "EfiPci.h"
+
+#endif
diff --git a/EdkCompatibilityPkg/Foundation/Include/IndustryStandard/pci22.h b/EdkCompatibilityPkg/Foundation/Include/IndustryStandard/pci22.h new file mode 100644 index 0000000000..77aebb69e6 --- /dev/null +++ b/EdkCompatibilityPkg/Foundation/Include/IndustryStandard/pci22.h @@ -0,0 +1,555 @@ +/*++
+
+Copyright (c) 2004 - 2007, Intel Corporation
+All rights reserved. This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution. The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+Module Name:
+
+ pci22.h
+
+Abstract:
+ Support for PCI 2.2 standard.
+
+Revision History
+
+--*/
+
+#ifndef _PCI22_H
+#define _PCI22_H
+
+#define PCI_MAX_SEGMENT 0
+
+#define PCI_MAX_BUS 255
+
+#define PCI_MAX_DEVICE 31
+#define PCI_MAX_FUNC 7
+
+//
+// Command
+//
+#define PCI_VGA_PALETTE_SNOOP_DISABLED 0x20
+
+#pragma pack(push, 1)
+typedef struct {
+ UINT16 VendorId;
+ UINT16 DeviceId;
+ UINT16 Command;
+ UINT16 Status;
+ UINT8 RevisionID;
+ UINT8 ClassCode[3];
+ UINT8 CacheLineSize;
+ UINT8 LatencyTimer;
+ UINT8 HeaderType;
+ UINT8 BIST;
+} PCI_DEVICE_INDEPENDENT_REGION;
+
+typedef struct {
+ UINT32 Bar[6];
+ UINT32 CISPtr;
+ UINT16 SubsystemVendorID;
+ UINT16 SubsystemID;
+ UINT32 ExpansionRomBar;
+ UINT8 CapabilityPtr;
+ UINT8 Reserved1[3];
+ UINT32 Reserved2;
+ UINT8 InterruptLine;
+ UINT8 InterruptPin;
+ UINT8 MinGnt;
+ UINT8 MaxLat;
+} PCI_DEVICE_HEADER_TYPE_REGION;
+
+typedef struct {
+ PCI_DEVICE_INDEPENDENT_REGION Hdr;
+ PCI_DEVICE_HEADER_TYPE_REGION Device;
+} PCI_TYPE00;
+
+typedef struct {
+ UINT32 Bar[2];
+ UINT8 PrimaryBus;
+ UINT8 SecondaryBus;
+ UINT8 SubordinateBus;
+ UINT8 SecondaryLatencyTimer;
+ UINT8 IoBase;
+ UINT8 IoLimit;
+ UINT16 SecondaryStatus;
+ UINT16 MemoryBase;
+ UINT16 MemoryLimit;
+ UINT16 PrefetchableMemoryBase;
+ UINT16 PrefetchableMemoryLimit;
+ UINT32 PrefetchableBaseUpper32;
+ UINT32 PrefetchableLimitUpper32;
+ UINT16 IoBaseUpper16;
+ UINT16 IoLimitUpper16;
+ UINT8 CapabilityPtr;
+ UINT8 Reserved[3];
+ UINT32 ExpansionRomBAR;
+ UINT8 InterruptLine;
+ UINT8 InterruptPin;
+ UINT16 BridgeControl;
+} PCI_BRIDGE_CONTROL_REGISTER;
+
+typedef struct {
+ PCI_DEVICE_INDEPENDENT_REGION Hdr;
+ PCI_BRIDGE_CONTROL_REGISTER Bridge;
+} PCI_TYPE01;
+
+typedef union {
+ PCI_TYPE00 Device;
+ PCI_TYPE01 Bridge;
+} PCI_TYPE_GENERIC;
+
+typedef struct {
+ UINT32 CardBusSocketReg; // Cardus Socket/ExCA Base
+ // Address Register
+ //
+ UINT16 Reserved;
+ UINT16 SecondaryStatus; // Secondary Status
+ UINT8 PciBusNumber; // PCI Bus Number
+ UINT8 CardBusBusNumber; // CardBus Bus Number
+ UINT8 SubordinateBusNumber; // Subordinate Bus Number
+ UINT8 CardBusLatencyTimer; // CardBus Latency Timer
+ UINT32 MemoryBase0; // Memory Base Register 0
+ UINT32 MemoryLimit0; // Memory Limit Register 0
+ UINT32 MemoryBase1;
+ UINT32 MemoryLimit1;
+ UINT32 IoBase0;
+ UINT32 IoLimit0; // I/O Base Register 0
+ UINT32 IoBase1; // I/O Limit Register 0
+ UINT32 IoLimit1;
+ UINT8 InterruptLine; // Interrupt Line
+ UINT8 InterruptPin; // Interrupt Pin
+ UINT16 BridgeControl; // Bridge Control
+} PCI_CARDBUS_CONTROL_REGISTER;
+
+//
+// Definitions of PCI class bytes and manipulation macros.
+//
+#define PCI_CLASS_OLD 0x00
+#define PCI_CLASS_OLD_OTHER 0x00
+#define PCI_CLASS_OLD_VGA 0x01
+
+#define PCI_CLASS_MASS_STORAGE 0x01
+#define PCI_CLASS_MASS_STORAGE_SCSI 0x00
+#define PCI_CLASS_MASS_STORAGE_IDE 0x01 // obsolete
+#define PCI_CLASS_IDE 0x01
+#define PCI_CLASS_MASS_STORAGE_FLOPPY 0x02
+#define PCI_CLASS_MASS_STORAGE_IPI 0x03
+#define PCI_CLASS_MASS_STORAGE_RAID 0x04
+#define PCI_CLASS_MASS_STORAGE_OTHER 0x80
+
+#define PCI_CLASS_NETWORK 0x02
+#define PCI_CLASS_NETWORK_ETHERNET 0x00
+#define PCI_CLASS_ETHERNET 0x00 // obsolete
+#define PCI_CLASS_NETWORK_TOKENRING 0x01
+#define PCI_CLASS_NETWORK_FDDI 0x02
+#define PCI_CLASS_NETWORK_ATM 0x03
+#define PCI_CLASS_NETWORK_ISDN 0x04
+#define PCI_CLASS_NETWORK_OTHER 0x80
+
+#define PCI_CLASS_DISPLAY 0x03
+#define PCI_CLASS_DISPLAY_CTRL 0x03 // obsolete
+#define PCI_CLASS_DISPLAY_VGA 0x00
+#define PCI_CLASS_VGA 0x00 // obsolete
+#define PCI_CLASS_DISPLAY_XGA 0x01
+#define PCI_CLASS_DISPLAY_3D 0x02
+#define PCI_CLASS_DISPLAY_OTHER 0x80
+#define PCI_CLASS_DISPLAY_GFX 0x80
+#define PCI_CLASS_GFX 0x80 // obsolete
+
+#define PCI_CLASS_BRIDGE 0x06
+#define PCI_CLASS_BRIDGE_HOST 0x00
+#define PCI_CLASS_BRIDGE_ISA 0x01
+#define PCI_CLASS_ISA 0x01 // obsolete
+#define PCI_CLASS_BRIDGE_EISA 0x02
+#define PCI_CLASS_BRIDGE_MCA 0x03
+#define PCI_CLASS_BRIDGE_P2P 0x04
+#define PCI_CLASS_BRIDGE_PCMCIA 0x05
+#define PCI_CLASS_BRIDGE_NUBUS 0x06
+#define PCI_CLASS_BRIDGE_CARDBUS 0x07
+#define PCI_CLASS_BRIDGE_RACEWAY 0x08
+#define PCI_CLASS_BRIDGE_ISA_PDECODE 0x80
+#define PCI_CLASS_ISA_POSITIVE_DECODE 0x80 // obsolete
+
+#define PCI_CLASS_SCC 0x07 // Simple communications controllers
+#define PCI_SUBCLASS_SERIAL 0x00
+#define PCI_IF_GENERIC_XT 0x00
+#define PCI_IF_16450 0x01
+#define PCI_IF_16550 0x02
+#define PCI_IF_16650 0x03
+#define PCI_IF_16750 0x04
+#define PCI_IF_16850 0x05
+#define PCI_IF_16950 0x06
+#define PCI_SUBCLASS_PARALLEL 0x01
+#define PCI_IF_PARALLEL_PORT 0x00
+#define PCI_IF_BI_DIR_PARALLEL_PORT 0x01
+#define PCI_IF_ECP_PARALLEL_PORT 0x02
+#define PCI_IF_1284_CONTROLLER 0x03
+#define PCI_IF_1284_DEVICE 0xFE
+#define PCI_SUBCLASS_MULTIPORT_SERIAL 0x02
+#define PCI_SUBCLASS_MODEM 0x03
+#define PCI_IF_GENERIC_MODEM 0x00
+#define PCI_IF_16450_MODEM 0x01
+#define PCI_IF_16550_MODEM 0x02
+#define PCI_IF_16650_MODEM 0x03
+#define PCI_IF_16750_MODEM 0x04
+#define PCI_SUBCLASS_OTHER 0x80
+
+#define PCI_CLASS_SYSTEM_PERIPHERAL 0x08
+#define PCI_SUBCLASS_PIC 0x00
+#define PCI_IF_8259_PIC 0x00
+#define PCI_IF_ISA_PIC 0x01
+#define PCI_IF_EISA_PIC 0x02
+#define PCI_IF_APIC_CONTROLLER 0x10 // I/O APIC interrupt controller , 32 bye none-prefectable memory.
+#define PCI_IF_APIC_CONTROLLER2 0x20
+#define PCI_SUBCLASS_TIMER 0x02
+#define PCI_IF_8254_TIMER 0x00
+#define PCI_IF_ISA_TIMER 0x01
+#define PCI_EISA_TIMER 0x02
+#define PCI_SUBCLASS_RTC 0x03
+#define PCI_IF_GENERIC_RTC 0x00
+#define PCI_IF_ISA_RTC 0x00
+#define PCI_SUBCLASS_PNP_CONTROLLER 0x04 // HotPlug Controller
+
+#define PCI_CLASS_INPUT_DEVICE 0x09
+#define PCI_SUBCLASS_KEYBOARD 0x00
+#define PCI_SUBCLASS_PEN 0x01
+#define PCI_SUBCLASS_MOUSE_CONTROLLER 0x02
+#define PCI_SUBCLASS_SCAN_CONTROLLER 0x03
+#define PCI_SUBCLASS_GAMEPORT 0x04
+
+#define PCI_CLASS_DOCKING_STATION 0x0A
+
+#define PCI_CLASS_PROCESSOR 0x0B
+#define PCI_SUBCLASS_PROC_386 0x00
+#define PCI_SUBCLASS_PROC_486 0x01
+#define PCI_SUBCLASS_PROC_PENTIUM 0x02
+#define PCI_SUBCLASS_PROC_ALPHA 0x10
+#define PCI_SUBCLASS_PROC_POWERPC 0x20
+#define PCI_SUBCLASS_PROC_MIPS 0x30
+#define PCI_SUBCLASS_PROC_CO_PORC 0x40 // Co-Processor
+
+#define PCI_CLASS_SERIAL 0x0C
+#define PCI_CLASS_SERIAL_FIREWIRE 0x00
+#define PCI_CLASS_SERIAL_ACCESS_BUS 0x01
+#define PCI_CLASS_SERIAL_SSA 0x02
+#define PCI_CLASS_SERIAL_USB 0x03
+#define PCI_IF_EHCI 0x20
+#define PCI_CLASS_SERIAL_FIBRECHANNEL 0x04
+#define PCI_CLASS_SERIAL_SMB 0x05
+
+#define PCI_CLASS_WIRELESS 0x0D
+#define PCI_SUBCLASS_IRDA 0x00
+#define PCI_SUBCLASS_IR 0x01
+#define PCI_SUBCLASS_RF 0x02
+
+#define PCI_CLASS_INTELLIGENT_IO 0x0E
+
+#define PCI_CLASS_SATELLITE 0x0F
+#define PCI_SUBCLASS_TV 0x01
+#define PCI_SUBCLASS_AUDIO 0x02
+#define PCI_SUBCLASS_VOICE 0x03
+#define PCI_SUBCLASS_DATA 0x04
+
+#define PCI_SECURITY_CONTROLLER 0x10 // Encryption and decryption controller
+#define PCI_SUBCLASS_NET_COMPUT 0x00
+#define PCI_SUBCLASS_ENTERTAINMENT 0x10
+
+#define PCI_CLASS_DPIO 0x11
+
+#define IS_CLASS1(_p, c) ((_p)->Hdr.ClassCode[2] == (c))
+#define IS_CLASS2(_p, c, s) (IS_CLASS1 (_p, c) && ((_p)->Hdr.ClassCode[1] == (s)))
+#define IS_CLASS3(_p, c, s, p) (IS_CLASS2 (_p, c, s) && ((_p)->Hdr.ClassCode[0] == (p)))
+
+#define IS_PCI_DISPLAY(_p) IS_CLASS1 (_p, PCI_CLASS_DISPLAY)
+#define IS_PCI_VGA(_p) IS_CLASS3 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_VGA, 0)
+#define IS_PCI_8514(_p) IS_CLASS3 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_VGA, 1)
+#define IS_PCI_GFX(_p) IS_CLASS3 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_GFX, 0)
+#define IS_PCI_OLD(_p) IS_CLASS1 (_p, PCI_CLASS_OLD)
+#define IS_PCI_OLD_VGA(_p) IS_CLASS2 (_p, PCI_CLASS_OLD, PCI_CLASS_OLD_VGA)
+#define IS_PCI_IDE(_p) IS_CLASS2 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_IDE)
+#define IS_PCI_SCSI(_p) IS_CLASS3 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_SCSI, 0)
+#define IS_PCI_RAID(_p) IS_CLASS3 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_RAID, 0)
+#define IS_PCI_LPC(_p) IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_ISA, 0)
+#define IS_PCI_ISA_PDECODE(_p) IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_ISA_PDECODE, 0)
+#define IS_PCI_P2P(_p) IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_P2P, 0)
+#define IS_PCI_P2P_SUB(_p) IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_P2P, 1)
+#define IS_PCI_16550_SERIAL(_p) IS_CLASS3 (_p, PCI_CLASS_SCC, PCI_SUBCLASS_SERIAL, PCI_IF_16550)
+#define IS_PCI_USB(_p) IS_CLASS2 (_p, PCI_CLASS_SERIAL, PCI_CLASS_SERIAL_USB)
+
+#define HEADER_TYPE_DEVICE 0x00
+#define HEADER_TYPE_PCI_TO_PCI_BRIDGE 0x01
+#define HEADER_TYPE_CARDBUS_BRIDGE 0x02
+
+#define HEADER_TYPE_MULTI_FUNCTION 0x80
+#define HEADER_LAYOUT_CODE 0x7f
+
+#define IS_PCI_BRIDGE(_p) (((_p)->Hdr.HeaderType & HEADER_LAYOUT_CODE) == (HEADER_TYPE_PCI_TO_PCI_BRIDGE))
+#define IS_CARDBUS_BRIDGE(_p) (((_p)->Hdr.HeaderType & HEADER_LAYOUT_CODE) == (HEADER_TYPE_CARDBUS_BRIDGE))
+#define IS_PCI_MULTI_FUNC(_p) ((_p)->Hdr.HeaderType & HEADER_TYPE_MULTI_FUNCTION)
+
+#define PCI_DEVICE_ROMBAR 0x30
+#define PCI_BRIDGE_ROMBAR 0x38
+
+#define PCI_MAX_BAR 0x0006
+#define PCI_MAX_CONFIG_OFFSET 0x0100
+
+#define PCI_VENDOR_ID_OFFSET 0x00
+#define PCI_DEVICE_ID_OFFSET 0x02
+#define PCI_COMMAND_OFFSET 0x04
+#define PCI_PRIMARY_STATUS_OFFSET 0x06
+#define PCI_REVISION_ID_OFFSET 0x08
+#define PCI_CLASSCODE_OFFSET 0x09
+#define PCI_SUBCLASSCODE_OFFSET 0x0A
+#define PCI_CACHELINE_SIZE_OFFSET 0x0C
+#define PCI_LATENCY_TIMER_OFFSET 0x0D
+#define PCI_HEADER_TYPE_OFFSET 0x0E
+#define PCI_BIST_OFFSET 0x0F
+#define PCI_BASE_ADDRESSREG_OFFSET 0x10
+#define PCI_CARDBUS_CIS_OFFSET 0x28
+#define PCI_SVID_OFFSET 0x2C // SubSystem Vendor id
+#define PCI_SUBSYSTEM_VENDOR_ID_OFFSET 0x2C
+#define PCI_SID_OFFSET 0x2E // SubSystem ID
+#define PCI_SUBSYSTEM_ID_OFFSET 0x2E
+#define PCI_EXPANSION_ROM_BASE 0x30
+#define PCI_CAPBILITY_POINTER_OFFSET 0x34
+#define PCI_INT_LINE_OFFSET 0x3C // Interrupt Line Register
+#define PCI_INT_PIN_OFFSET 0x3D // Interrupt Pin Register
+#define PCI_MAXGNT_OFFSET 0x3E // Max Grant Register
+#define PCI_MAXLAT_OFFSET 0x3F // Max Latency Register
+
+#define PCI_BRIDGE_CONTROL_REGISTER_OFFSET 0x3E
+#define PCI_BRIDGE_STATUS_REGISTER_OFFSET 0x1E
+
+#define PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET 0x18
+#define PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET 0x19
+#define PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET 0x1a
+
+//
+// Interrupt Line "Unknown" or "No connection" value defined for x86 based system
+//
+#define PCI_INT_LINE_UNKNOWN 0xFF
+
+
+typedef struct {
+ UINT32 Reg : 8;
+ UINT32 Func : 3;
+ UINT32 Dev : 5;
+ UINT32 Bus : 8;
+ UINT32 Reserved : 7;
+ UINT32 Enable : 1;
+} PCI_CONFIG_ACCESS_CF8;
+
+#pragma pack()
+
+#define PCI_EXPANSION_ROM_HEADER_SIGNATURE 0xaa55
+#define PCI_DATA_STRUCTURE_SIGNATURE EFI_SIGNATURE_32 ('P', 'C', 'I', 'R')
+#define PCI_CODE_TYPE_PCAT_IMAGE 0x00
+#define PCI_CODE_TYPE_EFI_IMAGE 0x03
+#define EFI_PCI_EXPANSION_ROM_HEADER_COMPRESSED 0x0001
+
+#define EFI_PCI_COMMAND_IO_SPACE 0x0001
+#define EFI_PCI_COMMAND_MEMORY_SPACE 0x0002
+#define EFI_PCI_COMMAND_BUS_MASTER 0x0004
+#define EFI_PCI_COMMAND_SPECIAL_CYCLE 0x0008
+#define EFI_PCI_COMMAND_MEMORY_WRITE_AND_INVALIDATE 0x0010
+#define EFI_PCI_COMMAND_VGA_PALETTE_SNOOP 0x0020
+#define EFI_PCI_COMMAND_PARITY_ERROR_RESPOND 0x0040
+#define EFI_PCI_COMMAND_STEPPING_CONTROL 0x0080
+#define EFI_PCI_COMMAND_SERR 0x0100
+#define EFI_PCI_COMMAND_FAST_BACK_TO_BACK 0x0200
+
+#define EFI_PCI_BRIDGE_CONTROL_PARITY_ERROR_RESPONSE 0x0001
+#define EFI_PCI_BRIDGE_CONTROL_SERR 0x0002
+#define EFI_PCI_BRIDGE_CONTROL_ISA 0x0004
+#define EFI_PCI_BRIDGE_CONTROL_VGA 0x0008
+#define EFI_PCI_BRIDGE_CONTROL_VGA_16 0x0010
+#define EFI_PCI_BRIDGE_CONTROL_MASTER_ABORT 0x0020
+#define EFI_PCI_BRIDGE_CONTROL_RESET_SECONDARY_BUS 0x0040
+#define EFI_PCI_BRIDGE_CONTROL_FAST_BACK_TO_BACK 0x0080
+#define EFI_PCI_BRIDGE_CONTROL_PRIMARY_DISCARD_TIMER 0x0100
+#define EFI_PCI_BRIDGE_CONTROL_SECONDARY_DISCARD_TIMER 0x0200
+#define EFI_PCI_BRIDGE_CONTROL_TIMER_STATUS 0x0400
+#define EFI_PCI_BRIDGE_CONTROL_DISCARD_TIMER_SERR 0x0800
+
+//
+// Following are the PCI-CARDBUS bridge control bit
+//
+#define EFI_PCI_BRIDGE_CONTROL_IREQINT_ENABLE 0x0080
+#define EFI_PCI_BRIDGE_CONTROL_RANGE0_MEMORY_TYPE 0x0100
+#define EFI_PCI_BRIDGE_CONTROL_RANGE1_MEMORY_TYPE 0x0200
+#define EFI_PCI_BRIDGE_CONTROL_WRITE_POSTING_ENABLE 0x0400
+
+//
+// Following are the PCI status control bit
+//
+#define EFI_PCI_STATUS_CAPABILITY 0x0010
+#define EFI_PCI_STATUS_66MZ_CAPABLE 0x0020
+#define EFI_PCI_FAST_BACK_TO_BACK_CAPABLE 0x0080
+#define EFI_PCI_MASTER_DATA_PARITY_ERROR 0x0100
+
+#define EFI_PCI_CAPABILITY_PTR 0x34
+#define EFI_PCI_CARDBUS_BRIDGE_CAPABILITY_PTR 0x14
+
+#pragma pack(1)
+typedef struct {
+ UINT16 Signature; // 0xaa55
+ UINT8 Reserved[0x16];
+ UINT16 PcirOffset;
+} PCI_EXPANSION_ROM_HEADER;
+
+typedef struct {
+ UINT16 Signature; // 0xaa55
+ UINT8 Size512;
+ UINT8 InitEntryPoint[3];
+ UINT8 Reserved[0x12];
+ UINT16 PcirOffset;
+} EFI_LEGACY_EXPANSION_ROM_HEADER;
+
+typedef struct {
+ UINT32 Signature; // "PCIR"
+ UINT16 VendorId;
+ UINT16 DeviceId;
+ UINT16 Reserved0;
+ UINT16 Length;
+ UINT8 Revision;
+ UINT8 ClassCode[3];
+ UINT16 ImageLength;
+ UINT16 CodeRevision;
+ UINT8 CodeType;
+ UINT8 Indicator;
+ UINT16 Reserved1;
+} PCI_DATA_STRUCTURE;
+
+//
+// PCI Capability List IDs and records
+//
+#define EFI_PCI_CAPABILITY_ID_PMI 0x01
+#define EFI_PCI_CAPABILITY_ID_AGP 0x02
+#define EFI_PCI_CAPABILITY_ID_VPD 0x03
+#define EFI_PCI_CAPABILITY_ID_SLOTID 0x04
+#define EFI_PCI_CAPABILITY_ID_MSI 0x05
+#define EFI_PCI_CAPABILITY_ID_HOTPLUG 0x06
+#define EFI_PCI_CAPABILITY_ID_PCIX 0x07
+
+typedef struct {
+ UINT8 CapabilityID;
+ UINT8 NextItemPtr;
+} EFI_PCI_CAPABILITY_HDR;
+
+//
+// Capability EFI_PCI_CAPABILITY_ID_PMI
+//
+typedef struct {
+ EFI_PCI_CAPABILITY_HDR Hdr;
+ UINT16 PMC;
+ UINT16 PMCSR;
+ UINT8 BridgeExtention;
+ UINT8 Data;
+} EFI_PCI_CAPABILITY_PMI;
+
+//
+// Capability EFI_PCI_CAPABILITY_ID_AGP
+//
+typedef struct {
+ EFI_PCI_CAPABILITY_HDR Hdr;
+ UINT8 Rev;
+ UINT8 Reserved;
+ UINT32 Status;
+ UINT32 Command;
+} EFI_PCI_CAPABILITY_AGP;
+
+//
+// Capability EFI_PCI_CAPABILITY_ID_VPD
+//
+typedef struct {
+ EFI_PCI_CAPABILITY_HDR Hdr;
+ UINT16 AddrReg;
+ UINT32 DataReg;
+} EFI_PCI_CAPABILITY_VPD;
+
+//
+// Capability EFI_PCI_CAPABILITY_ID_SLOTID
+//
+typedef struct {
+ EFI_PCI_CAPABILITY_HDR Hdr;
+ UINT8 ExpnsSlotReg;
+ UINT8 ChassisNo;
+} EFI_PCI_CAPABILITY_SLOTID;
+
+//
+// Capability EFI_PCI_CAPABILITY_ID_MSI
+//
+typedef struct {
+ EFI_PCI_CAPABILITY_HDR Hdr;
+ UINT16 MsgCtrlReg;
+ UINT32 MsgAddrReg;
+ UINT16 MsgDataReg;
+} EFI_PCI_CAPABILITY_MSI32;
+
+typedef struct {
+ EFI_PCI_CAPABILITY_HDR Hdr;
+ UINT16 MsgCtrlReg;
+ UINT32 MsgAddrRegLsdw;
+ UINT32 MsgAddrRegMsdw;
+ UINT16 MsgDataReg;
+} EFI_PCI_CAPABILITY_MSI64;
+
+//
+// Capability EFI_PCI_CAPABILITY_ID_HOTPLUG
+//
+typedef struct {
+ EFI_PCI_CAPABILITY_HDR Hdr;
+ //
+ // not finished - fields need to go here
+ //
+} EFI_PCI_CAPABILITY_HOTPLUG;
+
+//
+// Capability EFI_PCI_CAPABILITY_ID_PCIX
+//
+typedef struct {
+ EFI_PCI_CAPABILITY_HDR Hdr;
+ UINT16 CommandReg;
+ UINT32 StatusReg;
+} EFI_PCI_CAPABILITY_PCIX;
+
+typedef struct {
+ EFI_PCI_CAPABILITY_HDR Hdr;
+ UINT16 SecStatusReg;
+ UINT32 StatusReg;
+ UINT32 SplitTransCtrlRegUp;
+ UINT32 SplitTransCtrlRegDn;
+} EFI_PCI_CAPABILITY_PCIX_BRDG;
+
+#define DEVICE_ID_NOCARE 0xFFFF
+
+#define PCI_ACPI_UNUSED 0
+#define PCI_BAR_NOCHANGE 0
+#define PCI_BAR_OLD_ALIGN 0xFFFFFFFFFFFFFFFF
+#define PCI_BAR_EVEN_ALIGN 0xFFFFFFFFFFFFFFFE
+#define PCI_BAR_SQUAD_ALIGN 0xFFFFFFFFFFFFFFFD
+#define PCI_BAR_DQUAD_ALIGN 0xFFFFFFFFFFFFFFFC
+
+#define PCI_BAR_IDX0 0x00
+#define PCI_BAR_IDX1 0x01
+#define PCI_BAR_IDX2 0x02
+#define PCI_BAR_IDX3 0x03
+#define PCI_BAR_IDX4 0x04
+#define PCI_BAR_IDX5 0x05
+#define PCI_BAR_ALL 0xFF
+
+#pragma pack(pop)
+
+//
+// NOTE: The following header files are included here for
+// compatibility consideration.
+//
+#include "EfiPci.h"
+
+#endif
diff --git a/EdkCompatibilityPkg/Foundation/Include/IndustryStandard/pci23.h b/EdkCompatibilityPkg/Foundation/Include/IndustryStandard/pci23.h new file mode 100644 index 0000000000..c42991f38c --- /dev/null +++ b/EdkCompatibilityPkg/Foundation/Include/IndustryStandard/pci23.h @@ -0,0 +1,31 @@ +/*++
+
+Copyright (c) 2006 - 2007, Intel Corporation
+All rights reserved. This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution. The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+Module Name:
+
+ pci23.h
+
+Abstract:
+ Support for PCI 2.3 standard.
+
+Revision History
+
+--*/
+
+#ifndef _PCI23_H
+#define _PCI23_H
+
+#include "pci22.h"
+
+#define PCI_EXP_MAX_CONFIG_OFFSET 0x1000
+#define EFI_PCI_CAPABILITY_ID_PCIEXP 0x10
+
+#endif
diff --git a/EdkCompatibilityPkg/Foundation/Include/IndustryStandard/pci30.h b/EdkCompatibilityPkg/Foundation/Include/IndustryStandard/pci30.h new file mode 100644 index 0000000000..1a9219b377 --- /dev/null +++ b/EdkCompatibilityPkg/Foundation/Include/IndustryStandard/pci30.h @@ -0,0 +1,52 @@ +/*++
+
+Copyright (c) 2006 - 2007, Intel Corporation
+All rights reserved. This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution. The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+Module Name:
+
+ pci30.h
+
+Abstract:
+ Support for PCI 3.0 standard.
+
+Revision History
+
+--*/
+
+#ifndef _PCI30_H
+#define _PCI30_H
+
+#include "pci23.h"
+
+#define PCI_CLASS_MASS_STORAGE_SATADPA 0x06
+#define PCI_CLASS_MASS_STORAGE_AHCI PCI_CLASS_MASS_STORAGE_SATADPA
+
+#pragma pack(push, 1)
+
+typedef struct {
+ UINT32 Signature; // "PCIR"
+ UINT16 VendorId;
+ UINT16 DeviceId;
+ UINT16 DeviceListOffset;
+ UINT16 Length;
+ UINT8 Revision;
+ UINT8 ClassCode[3];
+ UINT16 ImageLength;
+ UINT16 CodeRevision;
+ UINT8 CodeType;
+ UINT8 Indicator;
+ UINT16 MaxRuntimeImageLength;
+ UINT16 ConfigUtilityCodeHeaderOffset;
+ UINT16 DMTFCLPEntryPointOffset;
+} PCI_3_0_DATA_STRUCTURE;
+
+#pragma pack(pop)
+
+#endif
diff --git a/EdkCompatibilityPkg/Foundation/Include/IndustryStandard/scsi.h b/EdkCompatibilityPkg/Foundation/Include/IndustryStandard/scsi.h new file mode 100644 index 0000000000..70a6b23833 --- /dev/null +++ b/EdkCompatibilityPkg/Foundation/Include/IndustryStandard/scsi.h @@ -0,0 +1,292 @@ +/*++
+
+Copyright (c) 2004 - 2006, Intel Corporation
+All rights reserved. This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution. The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+Module Name:
+
+ scsi.h
+
+Abstract:
+ support for SCSI standard
+
+Revision History
+--*/
+
+#ifndef _SCSI_H
+#define _SCSI_H
+
+//
+// SCSI command OP Code
+//
+//
+// Commands for all device types
+//
+#define EFI_SCSI_OP_CHANGE_DEFINITION 0x40
+#define EFI_SCSI_OP_COMPARE 0x39
+#define EFI_SCSI_OP_COPY 0x18
+#define EFI_SCSI_OP_COPY_VERIFY 0x3a
+#define EFI_SCSI_OP_INQUIRY 0x12
+#define EFI_SCSI_OP_LOG_SELECT 0x4c
+#define EFI_SCSI_OP_LOG_SENSE 0x4d
+#define EFI_SCSI_OP_MODE_SEL6 0x15
+#define EFI_SCSI_OP_MODE_SEL10 0x55
+#define EFI_SCSI_OP_MODE_SEN6 0x1a
+#define EFI_SCSI_OP_MODE_SEN10 0x5a
+#define EFI_SCSI_OP_READ_BUFFER 0x3c
+#define EFI_SCSI_OP_REQUEST_SENSE 0x03
+#define EFI_SCSI_OP_SEND_DIAG 0x1d
+#define EFI_SCSI_OP_TEST_UNIT_READY 0x00
+#define EFI_SCSI_OP_WRITE_BUFF 0x3b
+
+//
+// Commands unique to Direct Access Devices
+//
+#define EFI_SCSI_OP_COMPARE 0x39
+#define EFI_SCSI_OP_FORMAT 0x04
+#define EFI_SCSI_OP_LOCK_UN_CACHE 0x36
+#define EFI_SCSI_OP_PREFETCH 0x34
+#define EFI_SCSI_OP_MEDIA_REMOVAL 0x1e
+#define EFI_SCSI_OP_READ6 0x08
+#define EFI_SCSI_OP_READ10 0x28
+#define EFI_SCSI_OP_READ_CAPACITY 0x25
+#define EFI_SCSI_OP_READ_DEFECT 0x37
+#define EFI_SCSI_OP_READ_LONG 0x3e
+#define EFI_SCSI_OP_REASSIGN_BLK 0x07
+#define EFI_SCSI_OP_RECEIVE_DIAG 0x1c
+#define EFI_SCSI_OP_RELEASE 0x17
+#define EFI_SCSI_OP_REZERO 0x01
+#define EFI_SCSI_OP_SEARCH_DATA_E 0x31
+#define EFI_SCSI_OP_SEARCH_DATA_H 0x30
+#define EFI_SCSI_OP_SEARCH_DATA_L 0x32
+#define EFI_SCSI_OP_SEEK6 0x0b
+#define EFI_SCSI_OP_SEEK10 0x2b
+#define EFI_SCSI_OP_SEND_DIAG 0x1d
+#define EFI_SCSI_OP_SET_LIMIT 0x33
+#define EFI_SCSI_OP_START_STOP_UNIT 0x1b
+#define EFI_SCSI_OP_SYNC_CACHE 0x35
+#define EFI_SCSI_OP_VERIFY 0x2f
+#define EFI_SCSI_OP_WRITE6 0x0a
+#define EFI_SCSI_OP_WRITE10 0x2a
+#define EFI_SCSI_OP_WRITE_VERIFY 0x2e
+#define EFI_SCSI_OP_WRITE_LONG 0x3f
+#define EFI_SCSI_OP_WRITE_SAME 0x41
+
+//
+// Commands unique to Sequential Access Devices
+//
+#define EFI_SCSI_OP_ERASE 0x19
+#define EFI_SCSI_OP_LOAD_UNLOAD 0x1b
+#define EFI_SCSI_OP_LOCATE 0x2b
+#define EFI_SCSI_OP_READ_BLOCK_LIMIT 0x05
+#define EFI_SCSI_OP_READ_POS 0x34
+#define EFI_SCSI_OP_READ_REVERSE 0x0f
+#define EFI_SCSI_OP_RECOVER_BUF_DATA 0x14
+#define EFI_SCSI_OP_RESERVE_UNIT 0x16
+#define EFI_SCSI_OP_REWIND 0x01
+#define EFI_SCSI_OP_SPACE 0x11
+#define EFI_SCSI_OP_VERIFY_TAPE 0x13
+#define EFI_SCSI_OP_WRITE_FILEMARK 0x10
+
+//
+// Commands unique to Printer Devices
+//
+#define EFI_SCSI_OP_PRINT 0x0a
+#define EFI_SCSI_OP_SLEW_PRINT 0x0b
+#define EFI_SCSI_OP_STOP_PRINT 0x1b
+#define EFI_SCSI_OP_SYNC_BUFF 0x10
+
+//
+// Commands unique to Processor Devices
+//
+#define EFI_SCSI_OP_RECEIVE 0x08
+#define EFI_SCSI_OP_SEND 0x0a
+
+//
+// Commands unique to Write-Once Devices
+//
+#define EFI_SCSI_OP_MEDIUM_SCAN 0x38
+#define EFI_SCSI_OP_SEARCH_DAT_E10 0x31
+#define EFI_SCSI_OP_SEARCH_DAT_E12 0xb1
+#define EFI_SCSI_OP_SEARCH_DAT_H10 0x30
+#define EFI_SCSI_OP_SEARCH_DAT_H12 0xb0
+#define EFI_SCSI_OP_SEARCH_DAT_L10 0x32
+#define EFI_SCSI_OP_SEARCH_DAT_L12 0xb2
+#define EFI_SCSI_OP_SET_LIMIT10 0x33
+#define EFI_SCSI_OP_SET_LIMIT12 0xb3
+#define EFI_SCSI_OP_VERIFY10 0x2f
+#define EFI_SCSI_OP_VERIFY12 0xaf
+#define EFI_SCSI_OP_WRITE12 0xaa
+#define EFI_SCSI_OP_WRITE_VERIFY10 0x2e
+#define EFI_SCSI_OP_WRITE_VERIFY12 0xae
+
+//
+// Commands unique to CD-ROM Devices
+//
+#define EFI_SCSI_OP_PLAY_AUD_10 0x45
+#define EFI_SCSI_OP_PLAY_AUD_12 0xa5
+#define EFI_SCSI_OP_PLAY_AUD_MSF 0x47
+#define EFI_SCSI_OP_PLAY_AUD_TKIN 0x48
+#define EFI_SCSI_OP_PLAY_TK_REL10 0x49
+#define EFI_SCSI_OP_PLAY_TK_REL12 0xa9
+#define EFI_SCSI_OP_READ_CD_CAPACITY 0x25
+#define EFI_SCSI_OP_READ_HEADER 0x44
+#define EFI_SCSI_OP_READ_SUB_CHANNEL 0x42
+#define EFI_SCSI_OP_READ_TOC 0x43
+
+//
+// Commands unique to Scanner Devices
+//
+#define EFI_SCSI_OP_GET_DATABUFF_STAT 0x34
+#define EFI_SCSI_OP_GET_WINDOW 0x25
+#define EFI_SCSI_OP_OBJECT_POS 0x31
+#define EFI_SCSI_OP_SCAN 0x1b
+#define EFI_SCSI_OP_SET_WINDOW 0x24
+
+//
+// Commands unique to Optical Memory Devices
+//
+#define EFI_SCSI_OP_UPDATE_BLOCK 0x3d
+
+//
+// Commands unique to Medium Changer Devices
+//
+#define EFI_SCSI_OP_EXCHANGE_MEDIUM 0xa6
+#define EFI_SCSI_OP_INIT_ELEMENT_STAT 0x07
+#define EFI_SCSI_OP_POS_TO_ELEMENT 0x2b
+#define EFI_SCSI_OP_REQUEST_VE_ADDR 0xb5
+#define EFI_SCSI_OP_SEND_VOL_TAG 0xb6
+
+//
+// Commands unique to Communition Devices
+//
+#define EFI_SCSI_OP_GET_MESSAGE6 0x08
+#define EFI_SCSI_OP_GET_MESSAGE10 0x28
+#define EFI_SCSI_OP_GET_MESSAGE12 0xa8
+#define EFI_SCSI_OP_SEND_MESSAGE6 0x0a
+#define EFI_SCSI_OP_SEND_MESSAGE10 0x2a
+#define EFI_SCSI_OP_SEND_MESSAGE12 0xaa
+
+//
+// SCSI Data Transfer Direction
+//
+#define EFI_SCSI_DATA_IN 0
+#define EFI_SCSI_DATA_OUT 1
+
+//
+// Peripheral Device Type Definitions
+//
+#define EFI_SCSI_TYPE_DISK 0x00 // Disk device
+#define EFI_SCSI_TYPE_TAPE 0x01 // Tape device
+#define EFI_SCSI_TYPE_PRINTER 0x02 // Printer
+#define EFI_SCSI_TYPE_PROCESSOR 0x03 // Processor
+#define EFI_SCSI_TYPE_WORM 0x04 // Write-once read-multiple
+#define EFI_SCSI_TYPE_CDROM 0x05 // CD-ROM device
+#define EFI_SCSI_TYPE_SCANNER 0x06 // Scanner device
+#define EFI_SCSI_TYPE_OPTICAL 0x07 // Optical memory device
+#define EFI_SCSI_TYPE_MEDIUMCHANGER 0x08 // Medium Changer device
+#define EFI_SCSI_TYPE_COMMUNICATION 0x09 // Communications device
+#define EFI_SCSI_TYPE_RESERVED_LOW 0x0A // Reserved (low)
+#define EFI_SCSI_TYPE_RESERVED_HIGH 0x1E // Reserved (high)
+#define EFI_SCSI_TYPE_UNKNOWN 0x1F // Unknown or no device type
+#pragma pack(1)
+//
+// Data structures for scsi command use
+//
+typedef struct {
+ UINT8 Peripheral_Type : 5;
+ UINT8 Peripheral_Qualifier : 3;
+ UINT8 DeviceType_Modifier : 7;
+ UINT8 RMB : 1;
+ UINT8 Version;
+ UINT8 Response_Data_Format;
+ UINT8 Addnl_Length;
+ UINT8 Reserved_5_95[95 - 5 + 1];
+} EFI_SCSI_INQUIRY_DATA;
+
+typedef struct {
+ UINT8 Error_Code : 7;
+ UINT8 Valid : 1;
+ UINT8 Segment_Number;
+ UINT8 Sense_Key : 4;
+ UINT8 Reserved_21 : 1;
+ UINT8 ILI : 1;
+ UINT8 Reserved_22 : 2;
+ UINT8 Information_3_6[4];
+ UINT8 Addnl_Sense_Length; // n - 7
+ UINT8 Vendor_Specific_8_11[4];
+ UINT8 Addnl_Sense_Code; // mandatory
+ UINT8 Addnl_Sense_Code_Qualifier; // mandatory
+ UINT8 Field_Replaceable_Unit_Code; // optional
+ UINT8 Reserved_15_17[3];
+} EFI_SCSI_SENSE_DATA;
+
+typedef struct {
+ UINT8 LastLba3;
+ UINT8 LastLba2;
+ UINT8 LastLba1;
+ UINT8 LastLba0;
+ UINT8 BlockSize3;
+ UINT8 BlockSize2;
+ UINT8 BlockSize1;
+ UINT8 BlockSize0;
+} EFI_SCSI_DISK_CAPACITY_DATA;
+
+#pragma pack()
+//
+// Sense Key
+//
+#define EFI_SCSI_REQUEST_SENSE_ERROR (0x70)
+#define EFI_SCSI_SK_NO_SENSE (0x0)
+#define EFI_SCSI_SK_RECOVERY_ERROR (0x1)
+#define EFI_SCSI_SK_NOT_READY (0x2)
+#define EFI_SCSI_SK_MEDIUM_ERROR (0x3)
+#define EFI_SCSI_SK_HARDWARE_ERROR (0x4)
+#define EFI_SCSI_SK_ILLEGAL_REQUEST (0x5)
+#define EFI_SCSI_SK_UNIT_ATTENTION (0x6)
+#define EFI_SCSI_SK_DATA_PROTECT (0x7)
+#define EFI_SCSI_SK_BLANK_CHECK (0x8)
+#define EFI_SCSI_SK_VENDOR_SPECIFIC (0x9)
+#define EFI_SCSI_SK_RESERVED_A (0xA)
+#define EFI_SCSI_SK_ABORT (0xB)
+#define EFI_SCSI_SK_RESERVED_C (0xC)
+#define EFI_SCSI_SK_OVERFLOW (0xD)
+#define EFI_SCSI_SK_MISCOMPARE (0xE)
+#define EFI_SCSI_SK_RESERVED_F (0xF)
+
+//
+// Additional Sense Codes
+//
+#define EFI_SCSI_ASC_NOT_READY (0x04)
+#define EFI_SCSI_ASC_MEDIA_ERR1 (0x10)
+#define EFI_SCSI_ASC_MEDIA_ERR2 (0x11)
+#define EFI_SCSI_ASC_MEDIA_ERR3 (0x14)
+#define EFI_SCSI_ASC_MEDIA_ERR4 (0x30)
+#define EFI_SCSI_ASC_MEDIA_UPSIDE_DOWN (0x06)
+#define EFI_SCSI_ASC_INVALID_CMD (0x20)
+#define EFI_SCSI_ASC_LBA_OUT_OF_RANGE (0x21)
+#define EFI_SCSI_ASC_INVALID_FIELD (0x24)
+#define EFI_SCSI_ASC_WRITE_PROTECTED (0x27)
+#define EFI_SCSI_ASC_MEDIA_CHANGE (0x28)
+#define EFI_SCSI_ASC_RESET (0x29) /* Power On Reset or Bus Reset occurred */
+#define EFI_SCSI_ASC_ILLEGAL_FIELD (0x26)
+#define EFI_SCSI_ASC_NO_MEDIA (0x3A)
+#define EFI_SCSI_ASC_ILLEGAL_MODE_FOR_THIS_TRACK (0x64)
+
+//
+// Additional Sense Code Qualifier
+//
+#define EFI_SCSI_ASCQ_IN_PROGRESS (0x01)
+
+//
+// Max bytes needed to represent ID of a SCSI device
+//
+#define EFI_SCSI_TARGET_MAX_BYTES (0x10)
+
+#endif
diff --git a/EdkCompatibilityPkg/Foundation/Include/IndustryStandard/usb.h b/EdkCompatibilityPkg/Foundation/Include/IndustryStandard/usb.h new file mode 100644 index 0000000000..8ccfd11ea8 --- /dev/null +++ b/EdkCompatibilityPkg/Foundation/Include/IndustryStandard/usb.h @@ -0,0 +1,293 @@ +/*++
+
+Copyright (c) 2004 - 2006, Intel Corporation
+All rights reserved. This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution. The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+Module Name:
+
+ usb.h
+
+Abstract:
+ Support for USB 1.1 standard.
+
+
+
+
+Revision History
+
+--*/
+
+#ifndef _USB_H
+#define _USB_H
+//
+// USB Descriptor types
+//
+#define USB_DT_DEVICE 0x01
+#define USB_DT_CONFIG 0x02
+#define USB_DT_STRING 0x03
+#define USB_DT_INTERFACE 0x04
+#define USB_DT_ENDPOINT 0x05
+#define USB_DT_HUB 0x29
+#define USB_DT_HID 0x21
+
+//
+// USB request type
+//
+#define USB_TYPE_STANDARD (0x00 << 5)
+#define USB_TYPE_CLASS (0x01 << 5)
+#define USB_TYPE_VENDOR (0x02 << 5)
+#define USB_TYPE_RESERVED (0x03 << 5)
+
+//
+// USB request targer device
+//
+#define USB_RECIP_DEVICE 0x00
+#define USB_RECIP_INTERFACE 0x01
+#define USB_RECIP_ENDPOINT 0x02
+#define USB_RECIP_OTHER 0x03
+
+//
+// Request target types.
+//
+#define USB_RT_DEVICE 0x00
+#define USB_RT_INTERFACE 0x01
+#define USB_RT_ENDPOINT 0x02
+#define USB_RT_HUB (USB_TYPE_CLASS | USB_RECIP_DEVICE)
+#define USB_RT_PORT (USB_TYPE_CLASS | USB_RECIP_OTHER)
+
+//
+// USB Transfer Results
+//
+#define EFI_USB_NOERROR 0x00
+#define EFI_USB_ERR_NOTEXECUTE 0x01
+#define EFI_USB_ERR_STALL 0x02
+#define EFI_USB_ERR_BUFFER 0x04
+#define EFI_USB_ERR_BABBLE 0x08
+#define EFI_USB_ERR_NAK 0x10
+#define EFI_USB_ERR_CRC 0x20
+#define EFI_USB_ERR_TIMEOUT 0x40
+#define EFI_USB_ERR_BITSTUFF 0x80
+#define EFI_USB_ERR_SYSTEM 0x100
+
+//
+//Use 200 ms to increase the error handling response time
+//
+#define EFI_USB_INTERRUPT_DELAY 2000000
+
+//
+// USB transation direction
+//
+typedef enum {
+ EfiUsbDataIn,
+ EfiUsbDataOut,
+ EfiUsbNoData
+} EFI_USB_DATA_DIRECTION;
+
+//
+// Usb Data recipient type
+//
+typedef enum {
+ EfiUsbDevice,
+ EfiUsbInterface,
+ EfiUsbEndpoint
+} EFI_USB_RECIPIENT;
+
+typedef enum {
+ EfiUsbEndpointHalt,
+ EfiUsbDeviceRemoteWakeup
+} EFI_USB_STANDARD_FEATURE_SELECTOR;
+
+#pragma pack(1)
+//
+// Usb device request structure
+//
+typedef struct {
+ UINT8 RequestType;
+ UINT8 Request;
+ UINT16 Value;
+ UINT16 Index;
+ UINT16 Length;
+} EFI_USB_DEVICE_REQUEST;
+
+//
+// Standard USB request
+//
+#define USB_DEV_GET_STATUS 0x00
+
+#define USB_DEV_CLEAR_FEATURE 0x01
+
+#define USB_DEV_SET_FEATURE 0x03
+
+#define USB_DEV_SET_ADDRESS 0x05
+#define USB_DEV_SET_ADDRESS_REQ_TYPE 0x00
+
+#define USB_DEV_GET_DESCRIPTOR 0x06
+#define USB_DEV_GET_DESCRIPTOR_REQ_TYPE 0x80
+
+#define USB_DEV_SET_DESCRIPTOR 0x07
+#define USB_DEV_SET_DESCRIPTOR_REQ_TYPE 0x00
+
+#define USB_DEV_GET_CONFIGURATION 0x08
+#define USB_DEV_GET_CONFIGURATION_REQ_TYPE 0x80
+
+#define USB_DEV_SET_CONFIGURATION 0x09
+#define USB_DEV_SET_CONFIGURATION_REQ_TYPE 0x00
+
+#define USB_DEV_GET_INTERFACE 0x0A
+#define USB_DEV_GET_INTERFACE_REQ_TYPE 0x81
+
+#define USB_DEV_SET_INTERFACE 0x0B
+#define USB_DEV_SET_INTERFACE_REQ_TYPE 0x01
+
+#define USB_DEV_SYNCH_FRAME 0x0C
+#define USB_DEV_SYNCH_FRAME_REQ_TYPE 0x82
+
+//
+// Device descriptor. refer USB1.1
+//
+typedef struct usb_device_descriptor {
+ UINT8 Length;
+ UINT8 DescriptorType;
+ UINT16 BcdUSB;
+ UINT8 DeviceClass;
+ UINT8 DeviceSubClass;
+ UINT8 DeviceProtocol;
+ UINT8 MaxPacketSize0;
+ UINT16 IdVendor;
+ UINT16 IdProduct;
+ UINT16 BcdDevice;
+ UINT8 StrManufacturer;
+ UINT8 StrProduct;
+ UINT8 StrSerialNumber;
+ UINT8 NumConfigurations;
+} EFI_USB_DEVICE_DESCRIPTOR;
+
+//
+// Endpoint descriptor
+//
+typedef struct {
+ UINT8 Length;
+ UINT8 DescriptorType;
+ UINT8 EndpointAddress;
+ UINT8 Attributes;
+ UINT16 MaxPacketSize;
+ UINT8 Interval;
+} EFI_USB_ENDPOINT_DESCRIPTOR;
+
+//
+// Interface descriptor
+//
+typedef struct {
+ UINT8 Length;
+ UINT8 DescriptorType;
+ UINT8 InterfaceNumber;
+ UINT8 AlternateSetting;
+ UINT8 NumEndpoints;
+ UINT8 InterfaceClass;
+ UINT8 InterfaceSubClass;
+ UINT8 InterfaceProtocol;
+ UINT8 Interface;
+} EFI_USB_INTERFACE_DESCRIPTOR;
+
+//
+// USB alternate setting
+//
+typedef struct {
+ EFI_USB_INTERFACE_DESCRIPTOR *Interface;
+} USB_ALT_SETTING;
+
+//
+// Configuration descriptor
+//
+typedef struct {
+ UINT8 Length;
+ UINT8 DescriptorType;
+ UINT16 TotalLength;
+ UINT8 NumInterfaces;
+ UINT8 ConfigurationValue;
+ UINT8 Configuration;
+ UINT8 Attributes;
+ UINT8 MaxPower;
+} EFI_USB_CONFIG_DESCRIPTOR;
+
+//
+// Supported String Languages
+//
+typedef struct {
+ UINT8 Length;
+ UINT8 DescriptorType;
+ UINT16 SupportedLanID[1];
+} EFI_USB_SUPPORTED_LANGUAGES;
+
+//
+// String descriptor
+//
+typedef struct {
+ UINT8 Length;
+ UINT8 DescriptorType;
+ CHAR16 String[1];
+} EFI_USB_STRING_DESCRIPTOR;
+
+//
+// Hub descriptor
+//
+#define MAXBYTES 8
+typedef struct {
+ UINT8 Length;
+ UINT8 DescriptorType;
+ UINT8 NbrPorts;
+ UINT8 HubCharacteristics[2];
+ UINT8 PwrOn2PwrGood;
+ UINT8 HubContrCurrent;
+ UINT8 Filler[MAXBYTES];
+} EFI_USB_HUB_DESCRIPTOR;
+
+typedef struct {
+ UINT16 PortStatus;
+ UINT16 PortChangeStatus;
+} EFI_USB_PORT_STATUS;
+
+//
+// Constant value for Port Status & Port Change Status
+//
+#define USB_PORT_STAT_CONNECTION 0x0001
+#define USB_PORT_STAT_ENABLE 0x0002
+#define USB_PORT_STAT_SUSPEND 0x0004
+#define USB_PORT_STAT_OVERCURRENT 0x0008
+#define USB_PORT_STAT_RESET 0x0010
+#define USB_PORT_STAT_POWER 0x0100
+#define USB_PORT_STAT_LOW_SPEED 0x0200
+#define USB_PORT_STAT_HIGH_SPEED 0x0400
+#define USB_PORT_STAT_OWNER 0x0800
+
+#define USB_PORT_STAT_C_CONNECTION 0x0001
+#define USB_PORT_STAT_C_ENABLE 0x0002
+#define USB_PORT_STAT_C_SUSPEND 0x0004
+#define USB_PORT_STAT_C_OVERCURRENT 0x0008
+#define USB_PORT_STAT_C_RESET 0x0010
+
+//
+// Used for set/clear port feature request
+//
+typedef enum {
+ EfiUsbPortEnable = 1,
+ EfiUsbPortSuspend = 2,
+ EfiUsbPortReset = 4,
+ EfiUsbPortPower = 8,
+ EfiUsbPortOwner = 13,
+ EfiUsbPortConnectChange = 16,
+ EfiUsbPortEnableChange = 17,
+ EfiUsbPortSuspendChange = 18,
+ EfiUsbPortOverCurrentChange = 19,
+ EfiUsbPortResetChange = 20
+} EFI_USB_PORT_FEATURE;
+
+#pragma pack()
+
+#endif
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