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authorJeff Fan <jeff.fan@intel.com>2016-03-21 13:36:50 +0800
committerJeff Fan <jeff.fan@intel.com>2016-04-05 14:07:15 +0800
commit5f0a17d83a6443931068d428600824276ca2bd37 (patch)
tree2b35c0e698e2e58a55e8e0158b4e5074db0e1a2a /EmulatorPkg
parent0f18e1eda2a807283484adfbf5eaae6a92b1ffa7 (diff)
downloadedk2-platforms-5f0a17d83a6443931068d428600824276ca2bd37.tar.xz
MdePkg/BaseSynchronizationLib: Add spin lock alignment for IA32/x64
From Intel(R) 64 and IA-32 Architectures Software Developer's Manual, one lock or semaphore is suggested to be present within a cache line. If the processors are based on Intel NetBurst microarchitecture, two cache lines are suggested. This could minimize the bus traffic required to service locks. Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
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