MdeModulePkg/NvmExpressDxe: Check if CSTS.RDY is 0 to wait NVMe Host controller disable

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Tian, Feng <feng.tian@intel.com>
Reviewed-by: Zeng, Star <star.zeng@intel.com>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15557 6f19259b-4bc3-4df7-8a09-765794883524

2 files changed, 37 insertions, 18 deletions

diff --git a/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressHci.c b/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressHci.c
index 62eb39a7d6..8848d1a2a9 100644
--- a/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressHci.c
+++ b/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressHci.c
@@ -2,7 +2,7 @@
   NvmExpressDxe driver is used to manage non-volatile memory subsystem which follows

   NVM Express specification.

 

-  Copyright (c) 2013, Intel Corporation. All rights reserved.<BR>

+  Copyright (c) 2013 - 2014, Intel Corporation. All rights reserved.<BR>

   This program and the accompanying materials

   are licensed and made available under the terms and conditions of the BSD License

   which accompanies this distribution.  The full text of the license may be found at

@@ -430,6 +430,8 @@ NvmeDisableController (
   NVME_CC                Cc;

   NVME_CSTS              Csts;

   EFI_STATUS             Status;

+  UINT32                 Index;

+  UINT8                  Timeout;

 

   //

   // Read Controller Configuration Register.

@@ -450,19 +452,35 @@ NvmeDisableController (
     return Status;

   }

 

-  gBS->Stall(10000);

-

   //

-  // Check if the controller is reset

+  // Cap.To specifies max delay time in 500ms increments for Csts.Rdy to transition from 1 to 0 after

+  // Cc.Enable transition from 1 to 0. Loop produces a 1 millisecond delay per itteration, up to 500 * Cap.To.

   //

-  Status = ReadNvmeControllerStatus (Private, &Csts);

+  if (Private->Cap.To == 0) {

+    Timeout = 1;

+  } else {

+    Timeout = Private->Cap.To;

+  }

 

-  if (EFI_ERROR(Status)) {

-    return Status;

+  for(Index = (Timeout * 500); Index != 0; --Index) {

+    gBS->Stall(1000);

+

+    //

+    // Check if the controller is initialized

+    //

+    Status = ReadNvmeControllerStatus (Private, &Csts);

+

+    if (EFI_ERROR(Status)) {

+      return Status;

+    }

+

+    if (Csts.Rdy == 0) {

+      break;

+    }

   }

 

-  if (Csts.Rdy != 0) {

-    return EFI_DEVICE_ERROR;

+  if (Index == 0) {

+    Status = EFI_DEVICE_ERROR;

   }

 

   DEBUG ((EFI_D_INFO, "NVMe controller is disabled with status [%r].\n", Status));

@@ -959,7 +977,7 @@ NvmeControllerInit (
   DEBUG ((EFI_D_INFO, "    MN        : %a\n",   (CHAR8 *)(Private->ControllerData->Mn)));

   DEBUG ((EFI_D_INFO, "    FR        : 0x%x\n", *((UINT64*)Private->ControllerData->Fr)));

   DEBUG ((EFI_D_INFO, "    RAB       : 0x%x\n", Private->ControllerData->Rab));

-  DEBUG ((EFI_D_INFO, "    IEEE      : 0x%x\n", *(UINT32*)Private->ControllerData->Ieee_oiu));

+  DEBUG ((EFI_D_INFO, "    IEEE      : 0x%x\n", *(UINT32*)Private->ControllerData->Ieee_oui));

   DEBUG ((EFI_D_INFO, "    AERL      : 0x%x\n", Private->ControllerData->Aerl));

   DEBUG ((EFI_D_INFO, "    SQES      : 0x%x\n", Private->ControllerData->Sqes));

   DEBUG ((EFI_D_INFO, "    CQES      : 0x%x\n", Private->ControllerData->Cqes));

diff --git a/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressHci.h b/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressHci.h
index 406cef4f8e..aa0ac35c30 100644
--- a/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressHci.h
+++ b/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressHci.h
@@ -2,7 +2,7 @@
   NvmExpressDxe driver is used to manage non-volatile memory subsystem which follows

   NVM Express specification.

 

-  Copyright (c) 2013, Intel Corporation. All rights reserved.<BR>

+  Copyright (c) 2013 - 2014, Intel Corporation. All rights reserved.<BR>

   This program and the accompanying materials

   are licensed and made available under the terms and conditions of the BSD License

   which accompanies this distribution.  The full text of the license may be found at

@@ -27,6 +27,7 @@
 #define NVME_INTMC_OFFSET        0x0010  // Interrupt Mask Clear

 #define NVME_CC_OFFSET           0x0014  // Controller Configuration

 #define NVME_CSTS_OFFSET         0x001c  // Controller Status

+#define NVME_NSSR_OFFSET         0x0020  // NVM Subsystem Reset

 #define NVME_AQA_OFFSET          0x0024  // Admin Queue Attributes

 #define NVME_ASQ_OFFSET          0x0028  // Admin Submission Queue Base Address

 #define NVME_ACQ_OFFSET          0x0030  // Admin Completion Queue Base Address

@@ -53,8 +54,8 @@ typedef struct {
   UINT8  Rsvd1:5;

   UINT8  To;        // Timeout

   UINT16 Dstrd:4;

-  UINT16 Rsvd2:1;

-  UINT16 Css:4;     // Command Sets Supported

+  UINT16 Nssrs:1;   // NVM Subsystem Reset Supported NSSRS

+  UINT16 Css:4;     // Command Sets Supported - Bit 37

   UINT16 Rsvd3:7;

   UINT8  Mpsmin:4;

   UINT8  Mpsmax:4;

@@ -75,7 +76,7 @@ typedef struct {
 typedef struct {

   UINT16 En:1;       // Enable

   UINT16 Rsvd1:3;

-  UINT16 Css:3;      // Command Set Selected

+  UINT16 Css:3;      // I/O Command Set Selected

   UINT16 Mps:4;      // Memory Page Size

   UINT16 Ams:3;      // Arbitration Mechanism Selected

   UINT16 Shn:2;      // Shutdown Notification

@@ -333,12 +334,12 @@ typedef struct {
   //

   UINT16 Vid;                 /* PCI Vendor ID */

   UINT16 Ssvid;               /* PCI sub-system vendor ID */

-  UINT8  Sn[20];              /* Produce serial number */

+  UINT8  Sn[20];              /* Product serial number */

 

   UINT8  Mn[40];              /* Proeduct model number */

   UINT8  Fr[8];               /* Firmware Revision */

   UINT8  Rab;                 /* Recommended Arbitration Burst */

-  UINT8  Ieee_oiu[3];         /* Organization Unique Identifier */

+  UINT8  Ieee_oui[3];         /* Organization Unique Identifier */

   UINT8  Cmic;                /* Multi-interface Capabilities */

   UINT8  Mdts;                /* Maximum Data Transfer Size */

   UINT8  Cntlid[2];           /* Controller ID */

@@ -454,7 +455,7 @@ typedef struct {
   UINT32 Pc:1;                /* Physically Contiguous */

   UINT32 Ien:1;               /* Interrupts Enabled */

   UINT32 Rsvd1:14;            /* reserved as of Nvm Express 1.1 Spec */

-  UINT32 Iv:16;               /* Interrupt Vector */

+  UINT32 Iv:16;               /* Interrupt Vector for MSI-X or MSI*/

 } NVME_ADMIN_CRIOCQ;

 

 //

@@ -717,7 +718,7 @@ typedef struct {
   UINT16 Sct:3;             // Status Code Type

   UINT16 Rsvd2:2;

   UINT16 Mo:1;              // More

-  UINT16 Dnr:1;             // Retry

+  UINT16 Dnr:1;             // Do Not Retry

 } NVME_CQ;

 

 //