1. Updated PalCallStatic.s in BaseCacheMaintenanceLib

2. Updated PalCallStatic.s in BaseTimerLibLocalApic

git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@467 6f19259b-4bc3-4df7-8a09-765794883524

4 files changed, 54 insertions, 83 deletions

diff --git a/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.msa b/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.msa
index 30c4f1f007..a405b44d6f 100644
--- a/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.msa
+++ b/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.msa
@@ -49,7 +49,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
     <Arch ArchType="IPF">

       <Filename>IpfCache.c</Filename>

       <Filename>Ipf/Cpu.s</Filename>

-      <Filename>Ipf/CallPalProc.s</Filename>

+      <Filename>Ipf/PalCallStatic.s</Filename>

     </Arch>

   </SourceFiles>

   <Includes>

diff --git a/MdePkg/Library/BaseCacheMaintenanceLib/Ipf/CallPalProc.s b/MdePkg/Library/BaseCacheMaintenanceLib/Ipf/CallPalProc.s
deleted file mode 100644
index 18b0f5815a..0000000000
--- a/MdePkg/Library/BaseCacheMaintenanceLib/Ipf/CallPalProc.s
+++ /dev/null
@@ -1,38 +0,0 @@
-/// @file

-///   Contains an implementation of CallPalProcStatic on Itanium-based

-///   architecture.

-///

-/// Copyright (c) 2006, Intel Corporation

-/// All rights reserved. This program and the accompanying materials

-/// are licensed and made available under the terms and conditions of the BSD License

-/// which accompanies this distribution.  The full text of the license may be found at

-/// http://opensource.org/licenses/bsd-license.php

-///

-/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,

-/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

-///

-/// Module Name:  CallPalProc.s

-///

-///

-

-.auto

-.text

-

-.proc   CallPalProcStatic

-.type   CallPalProcStatic, @function

-CallPalProcStatic::

-        mov                 r9  = ar.k5

-        mov                 r8  = ip

-        add                 r8  = (PalProcReturn - CallPalProcStatic), r8

-        mov                 r28 = r32

-        mov                 b7  = r9

-        mov                 r29 = r33

-        mov                 r30 = r34

-        mov                 r31 = r35

-        mov                 r32 = b0

-        mov                 b0  = r8

-        br.sptk             b7

-PalProcReturn:

-        mov                 b0 = r32

-        br.ret.sptk.many    b0

-.endp   CallPalProcStatic

diff --git a/MdePkg/Library/BaseCacheMaintenanceLib/Ipf/PalCallStatic.s b/MdePkg/Library/BaseCacheMaintenanceLib/Ipf/PalCallStatic.s
new file mode 100644
index 0000000000..686383793d
--- /dev/null
+++ b/MdePkg/Library/BaseCacheMaintenanceLib/Ipf/PalCallStatic.s
@@ -0,0 +1,48 @@
+/// @file

+///   Contains an implementation of CallPalProcStatic on Itanium-based

+///   architecture.

+///

+/// Copyright (c) 2006, Intel Corporation

+/// All rights reserved. This program and the accompanying materials

+/// are licensed and made available under the terms and conditions of the BSD License

+/// which accompanies this distribution.  The full text of the license may be found at

+/// http://opensource.org/licenses/bsd-license.php

+///

+/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,

+/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

+///

+/// Module Name:  PalCallStatic.s

+///

+///

+

+.auto

+.text

+

+.proc   PalCallStatic

+.type   PalCallStatic, @function

+.regstk 5, 0, 0, 0

+PalCallStatic::

+        cmp.eq              p6 = r0, in0

+        mov                 r31 = in4

+        mov                 r8  = ip

+(p6)    mov                 in0 = ar.k5

+        add                 r8  = (PalProcReturn - PalCallStatic), r8

+        mov                 in4 = b0

+        mov                 r30 = in3

+        mov                 r29 = in2

+        mov                 b7  = in0

+        mov                 in3 = psr

+        rsm                 1 << 14                 // Disable interrupts

+        mov                 r28 = in1

+        mov                 in0 = 256

+        mov                 b0  = r8

+        br.cond.sptk        b7

+PalProcReturn:

+        mov                 psr.l = in3

+        cmp.eq              p6 = in0, in1           // in1 == PAL_COPY_PAL?

+(p6)    cmp.eq              p6 = r0, r8             // Status == Success?

+(p6)    add                 in2 = r9, in2

+(p6)    mov                 ar.k5 = in2

+        mov                 b0  = in4

+        br.ret.sptk.many    b0

+.endp   PalCallStatic

diff --git a/MdePkg/Library/BaseCacheMaintenanceLib/IpfCache.c b/MdePkg/Library/BaseCacheMaintenanceLib/IpfCache.c
index b37ac9ee1f..7e96d9b76a 100644
--- a/MdePkg/Library/BaseCacheMaintenanceLib/IpfCache.c
+++ b/MdePkg/Library/BaseCacheMaintenanceLib/IpfCache.c
@@ -20,7 +20,8 @@ typedef struct {
 } PAL_PROC_RETURN;

 

 PAL_PROC_RETURN

-CallPalProcStatic (

+PalCallStatic (

+  IN      CONST VOID                *PalEntryPoint,

   IN      UINT64                    Arg1,

   IN      UINT64                    Arg2,

   IN      UINT64                    Arg3,

@@ -41,47 +42,7 @@ InvalidateInstructionCache (
   VOID

   )

 {

-  CallPalProcStatic (1, 1, 1, 0);

-}

-

-/**

-  Invalidates a range of instruction cache lines in the cache coherency domain

-  of the calling CPU.

-

-  Invalidates the instruction cache lines specified by Address and Length. If

-  Address is not aligned on a cache line boundary, then entire instruction

-  cache line containing Address is invalidated. If Address + Length is not

-  aligned on a cache line boundary, then the entire instruction cache line

-  containing Address + Length -1 is invalidated. This function may choose to

-  invalidate the entire instruction cache if that is more efficient than

-  invalidating the specified range. If Length is 0, the no instruction cache

-  lines are invalidated. Address is returned.

-

-  If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().

-

-  @param  Address The base address of the instruction cache lines to

-                  invalidate. If the CPU is in a physical addressing mode, then

-                  Address is a physical address. If the CPU is in a virtual

-                  addressing mode, then Address is a virtual address.

-

-  @param  Length  The number of bytes to invalidate from the instruction cache.

-

-  @return Address

-

-**/

-VOID*

-EFIAPI

-InvalidateInstructionCacheRange (

-  IN      VOID                      *Address,

-  IN      UINTN                     Length

-  )

-{

-  ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);

-

-  if (Length > 0) {

-    InvalidateInstructionCache ();

-  }

-  return Address;

+  PalCallStatic (NULL, 1, 1, 1, 0);

 }

 

 /**

@@ -100,7 +61,7 @@ WriteBackInvalidateDataCache (
   VOID

   )

 {

-  CallPalProcStatic (1, 2, 1, 0);

+  PalCallStatic (NULL, 1, 2, 1, 0);

 }

 

 /**

@@ -160,7 +121,7 @@ WriteBackDataCache (
   VOID

   )

 {

-  CallPalProcStatic (1, 2, 0, 0);

+  PalCallStatic (NULL, 1, 2, 0, 0);

 }

 

 /**