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authormdkinney <mdkinney@6f19259b-4bc3-4df7-8a09-765794883524>2009-08-18 21:04:14 +0000
committermdkinney <mdkinney@6f19259b-4bc3-4df7-8a09-765794883524>2009-08-18 21:04:14 +0000
commit64698eb8415e6829b956a12c3883655acc02f5a7 (patch)
treec0546059354c12eac27dfcf0195f462cbc98e9d6 /MdePkg/Library/BaseLib/Arm/EnableInterrupts.asm
parent3c99107841da7f4f646c5bba94f55d73a936e82a (diff)
downloadedk2-platforms-64698eb8415e6829b956a12c3883655acc02f5a7.tar.xz
Add ARM support
Add C inline assembly files for IA32 and X64 GCC builds. git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@9113 6f19259b-4bc3-4df7-8a09-765794883524
Diffstat (limited to 'MdePkg/Library/BaseLib/Arm/EnableInterrupts.asm')
-rw-r--r--MdePkg/Library/BaseLib/Arm/EnableInterrupts.asm37
1 files changed, 37 insertions, 0 deletions
diff --git a/MdePkg/Library/BaseLib/Arm/EnableInterrupts.asm b/MdePkg/Library/BaseLib/Arm/EnableInterrupts.asm
new file mode 100644
index 0000000000..1a98fb57b4
--- /dev/null
+++ b/MdePkg/Library/BaseLib/Arm/EnableInterrupts.asm
@@ -0,0 +1,37 @@
+;------------------------------------------------------------------------------
+;
+; EnableInterrupts() for ARM
+;
+; Copyright (c) 2006 - 2009, Intel Corporation<BR>
+; Portions copyright (c) 2008-2009 Apple Inc.<BR>
+; All rights reserved. This program and the accompanying materials
+; are licensed and made available under the terms and conditions of the BSD License
+; which accompanies this distribution. The full text of the license may be found at
+; http://opensource.org/licenses/bsd-license.php
+;
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+;
+;------------------------------------------------------------------------------
+
+ EXPORT EnableInterrupts
+
+ AREA Interrupt_enable, CODE, READONLY
+
+;/**
+; Enables CPU interrupts.
+;
+;**/
+;VOID
+;EFIAPI
+;EnableInterrupts (
+; VOID
+; );
+;
+EnableInterrupts
+ MRS R0,CPSR
+ BIC R0,R0,#0x80 ;Enable IRQ interrupts
+ MSR CPSR_c,R0
+ BX LR
+
+ END