diff options
| author | bbahnsen <bbahnsen@6f19259b-4bc3-4df7-8a09-765794883524> | 2006-06-20 21:50:44 +0000 |
|---|---|---|
| committer | bbahnsen <bbahnsen@6f19259b-4bc3-4df7-8a09-765794883524> | 2006-06-20 21:50:44 +0000 |
| commit | 975201130c7223ef29be7a28500ed107623fc4be (patch) | |
| tree | 1ee2dacc73b6285d5371cf34e8100e831d971695 /MdePkg/Library/BaseLib/Ia32/DivU64x32Remainder.S | |
| parent | 11e7b0f6dd28d03942494d3e18842d31421a9842 (diff) | |
| download | edk2-platforms-975201130c7223ef29be7a28500ed107623fc4be.tar.xz | |
Use capital S for GCC assembly. This enables pre-processing for PCD support.
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@576 6f19259b-4bc3-4df7-8a09-765794883524
Diffstat (limited to 'MdePkg/Library/BaseLib/Ia32/DivU64x32Remainder.S')
| -rw-r--r-- | MdePkg/Library/BaseLib/Ia32/DivU64x32Remainder.S | 43 |
1 files changed, 43 insertions, 0 deletions
diff --git a/MdePkg/Library/BaseLib/Ia32/DivU64x32Remainder.S b/MdePkg/Library/BaseLib/Ia32/DivU64x32Remainder.S new file mode 100644 index 0000000000..1f34f18255 --- /dev/null +++ b/MdePkg/Library/BaseLib/Ia32/DivU64x32Remainder.S @@ -0,0 +1,43 @@ +#------------------------------------------------------------------------------
+#
+# Copyright (c) 2006, Intel Corporation
+# All rights reserved. This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+# Module Name:
+#
+# DivError.asm
+#
+# Abstract:
+#
+# Set error flag for all division functions
+#
+#------------------------------------------------------------------------------
+
+
+
+
+
+.global _InternalMathDivRemU64x32
+_InternalMathDivRemU64x32:
+ movl 12(%esp),%ecx
+ movl 8(%esp),%eax
+ xorl %edx,%edx
+ divl %ecx
+ pushl %eax
+ movl 8(%esp),%eax
+ divl %ecx
+ movl 20(%esp),%ecx
+ jecxz L1
+ movl %edx,(%ecx)
+L1:
+ popl %edx
+ ret
+
+
+
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