Add EnableCache() and DisableCache() implementations for IA32 and X64 to the BaseLib

git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@6705 6f19259b-4bc3-4df7-8a09-765794883524

4 files changed, 164 insertions, 0 deletions

diff --git a/MdePkg/Library/BaseLib/X64/DisableCache.S b/MdePkg/Library/BaseLib/X64/DisableCache.S
new file mode 100644
index 0000000000..44f82bbe52
--- /dev/null
+++ b/MdePkg/Library/BaseLib/X64/DisableCache.S
@@ -0,0 +1,39 @@
+#------------------------------------------------------------------------------

+#

+# Copyright (c) 2006 - 2008, Intel Corporation

+# All rights reserved. This program and the accompanying materials

+# are licensed and made available under the terms and conditions of the BSD License

+# which accompanies this distribution.  The full text of the license may be found at

+# http://opensource.org/licenses/bsd-license.php

+#

+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,

+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

+#

+# Module Name:

+#

+#   DisableCache.S

+#

+# Abstract:

+#

+#   Set the CD bit of CR0 to 1, clear the NW bit of CR0 to 0, and flush all caches with a

+#   WBINVD instruction.

+#

+# Notes:

+#

+#------------------------------------------------------------------------------

+

+#------------------------------------------------------------------------------

+# VOID

+# EFIAPI

+# AsmDisableCache (

+#   VOID

+#   );

+#------------------------------------------------------------------------------

+.globl ASM_PFX(AsmDisableCache)

+ASM_PFX(AsmDisableCache):

+    movl    %cr0, %rax

+    btsl    $30, %rax

+    btrl    $29, %rax

+    movl    %rax, %cr0

+    wbinvd

+    ret

diff --git a/MdePkg/Library/BaseLib/X64/DisableCache.asm b/MdePkg/Library/BaseLib/X64/DisableCache.asm
new file mode 100644
index 0000000000..5ad85c7697
--- /dev/null
+++ b/MdePkg/Library/BaseLib/X64/DisableCache.asm
@@ -0,0 +1,43 @@
+;------------------------------------------------------------------------------

+;

+; Copyright (c) 2006, Intel Corporation

+; All rights reserved. This program and the accompanying materials

+; are licensed and made available under the terms and conditions of the BSD License

+; which accompanies this distribution.  The full text of the license may be found at

+; http://opensource.org/licenses/bsd-license.php

+;

+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,

+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

+;

+; Module Name:

+;

+;   DisableCache.Asm

+;

+; Abstract:

+;

+;   Set the CD bit of CR0 to 1, clear the NW bit of CR0 to 0, and flush all caches with a

+;   WBINVD instruction.

+;

+; Notes:

+;

+;------------------------------------------------------------------------------

+

+    .code

+

+;------------------------------------------------------------------------------

+; VOID

+; EFIAPI

+; AsmDisableCache (

+;   VOID

+;   );

+;------------------------------------------------------------------------------

+AsmDisableCache PROC

+    mov     rax, cr0

+    bts     rax, 30

+    btr     rax, 29

+    mov     cr0, rax

+    wbinvd

+    ret

+AsmDisableCache ENDP

+

+    END

diff --git a/MdePkg/Library/BaseLib/X64/EnableCache.S b/MdePkg/Library/BaseLib/X64/EnableCache.S
new file mode 100644
index 0000000000..99257d6527
--- /dev/null
+++ b/MdePkg/Library/BaseLib/X64/EnableCache.S
@@ -0,0 +1,39 @@
+#------------------------------------------------------------------------------

+#

+# Copyright (c) 2006 - 2008, Intel Corporation

+# All rights reserved. This program and the accompanying materials

+# are licensed and made available under the terms and conditions of the BSD License

+# which accompanies this distribution.  The full text of the license may be found at

+# http://opensource.org/licenses/bsd-license.php

+#

+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,

+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

+#

+# Module Name:

+#

+#   EnableCache.S

+#

+# Abstract:

+#

+#   Flush all caches with a WBINVD instruction, clear the CD bit of CR0 to 0, and clear 

+#   the NW bit of CR0 to 0

+#

+# Notes:

+#

+#------------------------------------------------------------------------------

+

+#------------------------------------------------------------------------------

+# VOID

+# EFIAPI

+# AsmEnableCache (

+#   VOID

+#   );

+#------------------------------------------------------------------------------

+.globl ASM_PFX(AsmEnableCache)

+ASM_PFX(AsmEnableCache):

+    wbinvd

+    movl    %cr0, %rax

+    btrl    $30, %rax

+    btrl    $29, %rax

+    movl    %rax, %cr0

+    ret

diff --git a/MdePkg/Library/BaseLib/X64/EnableCache.asm b/MdePkg/Library/BaseLib/X64/EnableCache.asm
new file mode 100644
index 0000000000..5846cf0a5f
--- /dev/null
+++ b/MdePkg/Library/BaseLib/X64/EnableCache.asm
@@ -0,0 +1,43 @@
+;------------------------------------------------------------------------------

+;

+; Copyright (c) 2006, Intel Corporation

+; All rights reserved. This program and the accompanying materials

+; are licensed and made available under the terms and conditions of the BSD License

+; which accompanies this distribution.  The full text of the license may be found at

+; http://opensource.org/licenses/bsd-license.php

+;

+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,

+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

+;

+; Module Name:

+;

+;   EnableCache.Asm

+;

+; Abstract:

+;

+;  Flush all caches with a WBINVD instruction, clear the CD bit of CR0 to 0, and clear 

+;  the NW bit of CR0 to 0

+;

+; Notes:

+;

+;------------------------------------------------------------------------------

+

+    .code

+

+;------------------------------------------------------------------------------

+; VOID

+; EFIAPI

+; AsmEnableCache (

+;   VOID

+;   );

+;------------------------------------------------------------------------------

+AsmEnableCache PROC

+    wbinvd

+    mov     rax, cr0

+    btr     rax, 29

+    btr     rax, 30

+    mov     cr0, rax

+    ret

+AsmEnableCache ENDP

+

+    END