diff options
| author | Ard Biesheuvel <ard.biesheuvel@linaro.org> | 2017-11-15 12:17:42 +0000 |
|---|---|---|
| committer | Ard Biesheuvel <ard.biesheuvel@linaro.org> | 2017-12-08 16:16:53 +0000 |
| commit | 8ad58788b5c39c3b4cc46aa20c9c557a6b90d42e (patch) | |
| tree | ba9b99246523c3eedc71583204af9a2ac3ee3e1d /Platform/ARM/VExpressPkg/Include | |
| parent | ec842a8c5f666c278a5f759294c4a0ea9b126e1f (diff) | |
| download | edk2-platforms-8ad58788b5c39c3b4cc46aa20c9c557a6b90d42e.tar.xz | |
Platform/ARM/VExpress: import VExpressPkg from EDK2
Import the pieces that are closely tied to the ARM Versatile Express
development platforms into edk2-platforms, so they can be removed from
upstream EDK2.
Note that this includes the ArmPlatformSysConfigLib library class, which
is not used anywhere else.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Diffstat (limited to 'Platform/ARM/VExpressPkg/Include')
5 files changed, 657 insertions, 0 deletions
diff --git a/Platform/ARM/VExpressPkg/Include/Library/ArmPlatformSysConfigLib.h b/Platform/ARM/VExpressPkg/Include/Library/ArmPlatformSysConfigLib.h new file mode 100644 index 0000000000..39a0cc7f73 --- /dev/null +++ b/Platform/ARM/VExpressPkg/Include/Library/ArmPlatformSysConfigLib.h @@ -0,0 +1,63 @@ +/** @file ArmPlatformSysConfigLib.h
+
+ Copyright (c) 2011-2012, ARM Ltd. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __ARM_PLATFORM_SYS_CONFIG_H__
+#define __ARM_PLATFORM_SYS_CONFIG_H__
+
+#include <Base.h>
+
+/* This header file makes it easier to access the System Configuration Registers
+ * in the ARM Versatile Express motherboard.
+ */
+
+//
+// Typedef
+//
+typedef UINT32 SYS_CONFIG_FUNCTION;
+
+//
+// Functions
+//
+RETURN_STATUS
+ArmPlatformSysConfigInitialize (
+ VOID
+ );
+
+RETURN_STATUS
+ArmPlatformSysConfigGet (
+ IN SYS_CONFIG_FUNCTION Function,
+ OUT UINT32* Value
+ );
+
+RETURN_STATUS
+ArmPlatformSysConfigGetValues (
+ IN SYS_CONFIG_FUNCTION Function,
+ IN UINTN Size,
+ OUT UINT32* Values
+ );
+
+RETURN_STATUS
+ArmPlatformSysConfigSet (
+ IN SYS_CONFIG_FUNCTION Function,
+ IN UINT32 Value
+ );
+
+RETURN_STATUS
+ArmPlatformSysConfigSetDevice (
+ IN SYS_CONFIG_FUNCTION Function,
+ IN UINT32 Device,
+ IN UINT32 Value
+ );
+
+#endif /* __SYS_CFG_REGISTERS_H__ */
diff --git a/Platform/ARM/VExpressPkg/Include/Library/LcdPlatformLib.h b/Platform/ARM/VExpressPkg/Include/Library/LcdPlatformLib.h new file mode 100644 index 0000000000..b9bdf471e2 --- /dev/null +++ b/Platform/ARM/VExpressPkg/Include/Library/LcdPlatformLib.h @@ -0,0 +1,221 @@ +/** @file
+
+ Copyright (c) 2011, ARM Ltd. All rights reserved.<BR>
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+ **/
+
+#ifndef __LCDPLATFORMLIB_H
+#define __LCDPLATFORMLIB_H
+
+#include <Protocol/GraphicsOutput.h>
+
+#define LCD_VRAM_SIZE SIZE_8MB
+
+//
+// Modes definitions
+//
+#define VGA 0
+#define SVGA 1
+#define XGA 2
+#define SXGA 3
+#define WSXGA 4
+#define UXGA 5
+#define HD 6
+
+//
+// VGA Mode: 640 x 480
+//
+#define VGA_H_RES_PIXELS 640
+#define VGA_V_RES_PIXELS 480
+#define VGA_OSC_FREQUENCY 23750000 /* 0x016A6570 */
+
+#define VGA_H_SYNC ( 80 - 1)
+#define VGA_H_FRONT_PORCH ( 16 - 1)
+#define VGA_H_BACK_PORCH ( 64 - 1)
+
+#define VGA_V_SYNC ( 4 - 1)
+#define VGA_V_FRONT_PORCH ( 3 - 1)
+#define VGA_V_BACK_PORCH ( 13 - 1)
+
+//
+// SVGA Mode: 800 x 600
+//
+#define SVGA_H_RES_PIXELS 800
+#define SVGA_V_RES_PIXELS 600
+#define SVGA_OSC_FREQUENCY 38250000 /* 0x0247A610 */
+
+#define SVGA_H_SYNC ( 80 - 1)
+#define SVGA_H_FRONT_PORCH ( 32 - 1)
+#define SVGA_H_BACK_PORCH (112 - 1)
+
+#define SVGA_V_SYNC ( 4 - 1)
+#define SVGA_V_FRONT_PORCH ( 3 - 1)
+#define SVGA_V_BACK_PORCH ( 17 - 1)
+
+//
+// XGA Mode: 1024 x 768
+//
+#define XGA_H_RES_PIXELS 1024
+#define XGA_V_RES_PIXELS 768
+#define XGA_OSC_FREQUENCY 63500000 /* 0x03C8EEE0 */
+
+#define XGA_H_SYNC (104 - 1)
+#define XGA_H_FRONT_PORCH ( 48 - 1)
+#define XGA_H_BACK_PORCH (152 - 1)
+
+#define XGA_V_SYNC ( 4 - 1)
+#define XGA_V_FRONT_PORCH ( 3 - 1)
+#define XGA_V_BACK_PORCH ( 23 - 1)
+
+//
+// SXGA Mode: 1280 x 1024
+//
+#define SXGA_H_RES_PIXELS 1280
+#define SXGA_V_RES_PIXELS 1024
+#define SXGA_OSC_FREQUENCY 109000000 /* 0x067F3540 */
+
+#define SXGA_H_SYNC (136 - 1)
+#define SXGA_H_FRONT_PORCH ( 80 - 1)
+#define SXGA_H_BACK_PORCH (216 - 1)
+
+#define SXGA_V_SYNC ( 7 - 1)
+#define SXGA_V_FRONT_PORCH ( 3 - 1)
+#define SXGA_V_BACK_PORCH ( 29 - 1)
+
+//
+// WSXGA+ Mode: 1680 x 1050
+//
+#define WSXGA_H_RES_PIXELS 1680
+#define WSXGA_V_RES_PIXELS 1050
+#define WSXGA_OSC_FREQUENCY 147000000 /* 0x08C30AC0 */
+
+#define WSXGA_H_SYNC (170 - 1)
+#define WSXGA_H_FRONT_PORCH (104 - 1)
+#define WSXGA_H_BACK_PORCH (274 - 1)
+
+#define WSXGA_V_SYNC ( 5 - 1)
+#define WSXGA_V_FRONT_PORCH ( 4 - 1)
+#define WSXGA_V_BACK_PORCH ( 41 - 1)
+
+//
+// UXGA Mode: 1600 x 1200
+//
+#define UXGA_H_RES_PIXELS 1600
+#define UXGA_V_RES_PIXELS 1200
+#define UXGA_OSC_FREQUENCY 161000000 /* 0x0998AA40 */
+
+#define UXGA_H_SYNC (168 - 1)
+#define UXGA_H_FRONT_PORCH (112 - 1)
+#define UXGA_H_BACK_PORCH (280 - 1)
+
+#define UXGA_V_SYNC ( 4 - 1)
+#define UXGA_V_FRONT_PORCH ( 3 - 1)
+#define UXGA_V_BACK_PORCH ( 38 - 1)
+
+//
+// HD Mode: 1920 x 1080
+//
+#define HD_H_RES_PIXELS 1920
+#define HD_V_RES_PIXELS 1080
+#define HD_OSC_FREQUENCY 165000000 /* 0x09D5B340 */
+
+#define HD_H_SYNC ( 79 - 1)
+#define HD_H_FRONT_PORCH (128 - 1)
+#define HD_H_BACK_PORCH (328 - 1)
+
+#define HD_V_SYNC ( 5 - 1)
+#define HD_V_FRONT_PORCH ( 3 - 1)
+#define HD_V_BACK_PORCH ( 32 - 1)
+
+//
+// Colour Masks
+//
+
+#define LCD_24BPP_RED_MASK 0x00FF0000
+#define LCD_24BPP_GREEN_MASK 0x0000FF00
+#define LCD_24BPP_BLUE_MASK 0x000000FF
+#define LCD_24BPP_RESERVED_MASK 0xFF000000
+
+#define LCD_16BPP_555_RED_MASK 0x00007C00
+#define LCD_16BPP_555_GREEN_MASK 0x000003E0
+#define LCD_16BPP_555_BLUE_MASK 0x0000001F
+#define LCD_16BPP_555_RESERVED_MASK 0x00000000
+
+#define LCD_16BPP_565_RED_MASK 0x0000F800
+#define LCD_16BPP_565_GREEN_MASK 0x000007E0
+#define LCD_16BPP_565_BLUE_MASK 0x0000001F
+#define LCD_16BPP_565_RESERVED_MASK 0x00008000
+
+#define LCD_12BPP_444_RED_MASK 0x00000F00
+#define LCD_12BPP_444_GREEN_MASK 0x000000F0
+#define LCD_12BPP_444_BLUE_MASK 0x0000000F
+#define LCD_12BPP_444_RESERVED_MASK 0x0000F000
+
+
+// The enumeration indexes maps the PL111 LcdBpp values used in the LCD Control Register
+typedef enum {
+ LCD_BITS_PER_PIXEL_1 = 0,
+ LCD_BITS_PER_PIXEL_2,
+ LCD_BITS_PER_PIXEL_4,
+ LCD_BITS_PER_PIXEL_8,
+ LCD_BITS_PER_PIXEL_16_555,
+ LCD_BITS_PER_PIXEL_24,
+ LCD_BITS_PER_PIXEL_16_565,
+ LCD_BITS_PER_PIXEL_12_444
+} LCD_BPP;
+
+
+EFI_STATUS
+LcdPlatformInitializeDisplay (
+ IN EFI_HANDLE Handle
+ );
+
+EFI_STATUS
+LcdPlatformGetVram (
+ OUT EFI_PHYSICAL_ADDRESS* VramBaseAddress,
+ OUT UINTN* VramSize
+ );
+
+UINT32
+LcdPlatformGetMaxMode (
+ VOID
+ );
+
+EFI_STATUS
+LcdPlatformSetMode (
+ IN UINT32 ModeNumber
+ );
+
+EFI_STATUS
+LcdPlatformQueryMode (
+ IN UINT32 ModeNumber,
+ OUT EFI_GRAPHICS_OUTPUT_MODE_INFORMATION *Info
+ );
+
+EFI_STATUS
+LcdPlatformGetTimings (
+ IN UINT32 ModeNumber,
+ OUT UINT32* HRes,
+ OUT UINT32* HSync,
+ OUT UINT32* HBackPorch,
+ OUT UINT32* HFrontPorch,
+ OUT UINT32* VRes,
+ OUT UINT32* VSync,
+ OUT UINT32* VBackPorch,
+ OUT UINT32* VFrontPorch
+ );
+
+EFI_STATUS
+LcdPlatformGetBpp (
+ IN UINT32 ModeNumber,
+ OUT LCD_BPP* Bpp
+ );
+
+#endif
diff --git a/Platform/ARM/VExpressPkg/Include/Platform/CTA15-A7/ArmPlatform.h b/Platform/ARM/VExpressPkg/Include/Platform/CTA15-A7/ArmPlatform.h new file mode 100644 index 0000000000..b52f89a5cb --- /dev/null +++ b/Platform/ARM/VExpressPkg/Include/Platform/CTA15-A7/ArmPlatform.h @@ -0,0 +1,154 @@ +/** @file
+* Header defining Versatile Express constants (Base addresses, sizes, flags)
+*
+* Copyright (c) 2012, ARM Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef __ARM_VEXPRESS_CTA15A7_H__
+#define __ARM_VEXPRESS_CTA15A7_H__
+
+#include <VExpressMotherBoard.h>
+
+/***********************************************************************************
+// Platform Memory Map
+************************************************************************************/
+
+// Motherboard Peripheral and On-chip peripheral
+#define ARM_VE_BOARD_PERIPH_BASE 0x1C010000
+
+#ifdef ARM_BIGLITTLE_TC2
+
+// Secure NOR Flash
+#define ARM_VE_SEC_NOR0_BASE 0x00000000
+#define ARM_VE_SEC_NOR0_SZ SIZE_64MB
+
+// Secure RAM
+#define ARM_VE_SEC_RAM0_BASE 0x04000000
+#define ARM_VE_SEC_RAM0_SZ SIZE_64MB
+
+#endif
+
+// NOR Flash 0
+#define ARM_VE_SMB_NOR0_BASE 0x08000000
+#define ARM_VE_SMB_NOR0_SZ SIZE_64MB
+// NOR Flash 1
+#define ARM_VE_SMB_NOR1_BASE 0x0C000000
+#define ARM_VE_SMB_NOR1_SZ SIZE_64MB
+
+// SRAM
+#define ARM_VE_SMB_SRAM_BASE 0x14000000
+#define ARM_VE_SMB_SRAM_SZ SIZE_32MB
+
+// USB, Ethernet, VRAM
+#ifdef ARM_BIGLITTLE_TC2
+#define ARM_VE_SMB_PERIPH_BASE 0x18000000
+#define ARM_VE_SMB_PERIPH_SZ (SIZE_64MB + SIZE_32MB + SIZE_16MB)
+#else
+#define ARM_VE_SMB_PERIPH_BASE 0x1C000000
+#define ARM_VE_SMB_PERIPH_SZ (SIZE_64MB + SIZE_16MB)
+#endif
+#define PL111_CLCD_VRAM_MOTHERBOARD_BASE ARM_VE_SMB_PERIPH_BASE
+
+// On-Chip non-secure ROM
+#ifdef ARM_BIGLITTLE_TC2
+#define ARM_VE_TC2_NON_SECURE_ROM_BASE 0x1F000000
+#define ARM_VE_TC2_NON_SECURE_ROM_SZ SIZE_16MB
+#endif
+
+// On-Chip Peripherals
+#define ARM_VE_ONCHIP_PERIPH_BASE 0x20000000
+#define ARM_VE_ONCHIP_PERIPH_SZ 0x10000000
+
+// On-Chip non-secure SRAM
+#ifdef ARM_BIGLITTLE_TC2
+#define ARM_VE_TC2_NON_SECURE_SRAM_BASE 0x2E000000
+#define ARM_VE_TC2_NON_SECURE_SRAM_SZ SIZE_64KB
+#endif
+
+// Allocate a section for the VRAM (Video RAM)
+// If 0 then allow random memory allocation
+#define LCD_VRAM_CORE_TILE_BASE 0
+
+// Define SEC phase sync point
+#define ARM_SEC_EVENT_BOOT_IMAGE_TABLE_IS_AVAILABLE (ARM_SEC_EVENT_MAX + 1)
+
+/***********************************************************************************
+ Core Tile memory-mapped Peripherals
+************************************************************************************/
+
+// PL354 Static Memory Controller Base
+#ifdef ARM_BIGLITTLE_TC2
+#define ARM_VE_SMC_CTRL_BASE 0x7FFD0000
+#else
+#define ARM_VE_SMC_CTRL_BASE (ARM_VE_BOARD_PERIPH_BASE + 0xE1000)
+#endif
+
+#define ARM_CTA15A7_SCC_BASE 0x7FFF0000
+#define ARM_CTA15A7_SCC_CFGREG48 (ARM_CTA15A7_SCC_BASE + 0x700)
+
+#define ARM_CTA15A7_SCC_SYSINFO ARM_CTA15A7_SCC_CFGREG48
+
+#define ARM_CTA15A7_SCC_SYSINFO_CLUSTER_A7_NUM_CPU(val) (((val) >> 20) & 0xF)
+#define ARM_CTA15A7_SCC_SYSINFO_CLUSTER_A15_NUM_CPU(val) (((val) >> 16) & 0xF)
+#define ARM_CTA15A7_SCC_SYSINFO_ACTIVE_CLUSTER_A15 (1 << 0)
+#define ARM_CTA15A7_SCC_SYSINFO_ACTIVE_CLUSTER_A7 (1 << 1)
+#define ARM_CTA15A7_SCC_SYSINFO_UEFI_RESTORE_DEFAULT_NORFLASH (1 << 4)
+
+#define ARM_CTA15A7_SPC_BASE 0x7FFF0B00
+#define ARM_CTA15A7_SPC_WAKE_INT_MASK (ARM_CTA15A7_SPC_BASE + 0x24)
+#define ARM_CTA15A7_SPC_STANDBYWFI_STAT (ARM_CTA15A7_SPC_BASE + 0x3C)
+#define ARM_CTA15A7_SPC_A15_BX_ADDR0 (ARM_CTA15A7_SPC_BASE + 0x68)
+#define ARM_CTA15A7_SPC_A15_BX_ADDR1 (ARM_CTA15A7_SPC_BASE + 0x6C)
+#define ARM_CTA15A7_SPC_A15_BX_ADDR2 (ARM_CTA15A7_SPC_BASE + 0x70)
+#define ARM_CTA15A7_SPC_A15_BX_ADDR3 (ARM_CTA15A7_SPC_BASE + 0x74)
+#define ARM_CTA15A7_SPC_A7_BX_ADDR0 (ARM_CTA15A7_SPC_BASE + 0x78)
+#define ARM_CTA15A7_SPC_A7_BX_ADDR1 (ARM_CTA15A7_SPC_BASE + 0x7C)
+#define ARM_CTA15A7_SPC_A7_BX_ADDR2 (ARM_CTA15A7_SPC_BASE + 0x80)
+#define ARM_CTA15A7_SPC_A7_BX_ADDR3 (ARM_CTA15A7_SPC_BASE + 0x84)
+
+#define ARM_CTA15A7_SPC_WAKE_INT_MASK_IRQ_A15_MASK_0 (1 << 0)
+#define ARM_CTA15A7_SPC_WAKE_INT_MASK_IRQ_A15_MASK_1 (1 << 1)
+#define ARM_CTA15A7_SPC_WAKE_INT_MASK_FIQ_A15_MASK_0 (1 << 2)
+#define ARM_CTA15A7_SPC_WAKE_INT_MASK_FIQ_A15_MASK_1 (1 << 3)
+#define ARM_CTA15A7_SPC_WAKE_INT_MASK_IRQ_A7_MASK_0 (1 << 4)
+#define ARM_CTA15A7_SPC_WAKE_INT_MASK_IRQ_A7_MASK_1 (1 << 5)
+#define ARM_CTA15A7_SPC_WAKE_INT_MASK_IRQ_A7_MASK_2 (1 << 6)
+#define ARM_CTA15A7_SPC_WAKE_INT_MASK_FIQ_A7_MASK_0 (1 << 7)
+#define ARM_CTA15A7_SPC_WAKE_INT_MASK_FIQ_A7_MASK_1 (1 << 8)
+#define ARM_CTA15A7_SPC_WAKE_INT_MASK_FIQ_A7_MASK_2 (1 << 9)
+
+#define ARM_CTA15A7_SPC_STANDBYWFI_STAT_A15_0 (1 << 0)
+#define ARM_CTA15A7_SPC_STANDBYWFI_STAT_A15_1 (1 << 1)
+#define ARM_CTA15A7_SPC_STANDBYWFI_STAT_A15_L2 (1 << 2)
+#define ARM_CTA15A7_SPC_STANDBYWFI_STAT_A7_0 (1 << 3)
+#define ARM_CTA15A7_SPC_STANDBYWFI_STAT_A7_1 (1 << 4)
+#define ARM_CTA15A7_SPC_STANDBYWFI_STAT_A7_2 (1 << 5)
+#define ARM_CTA15A7_SPC_STANDBYWFI_STAT_A7_L2 (1 << 6)
+
+
+/***********************************************************************************
+// Memory-mapped peripherals
+************************************************************************************/
+
+/*// SP810 Controller
+#undef SP810_CTRL_BASE
+#define SP810_CTRL_BASE 0x1C020000
+
+// PL111 Colour LCD Controller
+#define PL111_CLCD_SITE ARM_VE_MOTHERBOARD_SITE
+#define PL111_CLCD_MOTHERBOARD_VIDEO_MODE_OSC_ID 1
+#define PL111_CLCD_CORE_TILE_VIDEO_MODE_OSC_ID 1
+
+// VRAM offset for the PL111 Colour LCD Controller on the motherboard
+#define VRAM_MOTHERBOARD_BASE (ARM_VE_SMB_PERIPH_BASE + 0x00000)*/
+
+#endif
diff --git a/Platform/ARM/VExpressPkg/Include/Platform/RTSM/ArmPlatform.h b/Platform/ARM/VExpressPkg/Include/Platform/RTSM/ArmPlatform.h new file mode 100644 index 0000000000..d856b6daa1 --- /dev/null +++ b/Platform/ARM/VExpressPkg/Include/Platform/RTSM/ArmPlatform.h @@ -0,0 +1,79 @@ +/** @file
+* Header defining Versatile Express constants (Base addresses, sizes, flags)
+*
+* Copyright (c) 2011, ARM Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef __ARM_VEXPRESS_H__
+#define __ARM_VEXPRESS_H__
+
+#include <VExpressMotherBoard.h>
+
+/***********************************************************************************
+// Platform Memory Map
+************************************************************************************/
+
+// Can be NOR0, NOR1, DRAM
+#define ARM_VE_REMAP_BASE 0x00000000
+#define ARM_VE_REMAP_SZ SIZE_64MB
+
+// Motherboard Peripheral and On-chip peripheral
+#define ARM_VE_BOARD_PERIPH_BASE 0x1C010000
+
+// NOR Flash 1
+// There is typo in the reference manual for the Base address of NOR Flash 1
+#define ARM_VE_SMB_NOR0_BASE 0x08000000
+#define ARM_VE_SMB_NOR0_SZ SIZE_64MB
+// NOR Flash 2
+#define ARM_VE_SMB_NOR1_BASE 0x0C000000
+#define ARM_VE_SMB_NOR1_SZ SIZE_64MB
+// SRAM
+#define ARM_VE_SMB_SRAM_BASE 0x2E000000
+#define ARM_VE_SMB_SRAM_SZ SIZE_64KB
+// USB, Ethernet, VRAM
+#define ARM_VE_SMB_PERIPH_BASE 0x18800000
+#define ARM_VE_SMB_PERIPH_SZ (SIZE_64MB - SIZE_8MB)
+
+#define PL111_CLCD_VRAM_MOTHERBOARD_BASE 0x18000000
+#define PL111_CLCD_VRAM_MOTHERBOARD_SIZE 0x800000
+
+// DRAM
+#define ARM_VE_DRAM_BASE PcdGet64 (PcdSystemMemoryBase)
+#define ARM_VE_DRAM_SZ PcdGet64 (PcdSystemMemorySize)
+
+// This can be any value since we only support motherboard PL111
+#define LCD_VRAM_CORE_TILE_BASE 0x00000000
+
+// On-chip peripherals (Snoop Control Unit etc...)
+#define ARM_VE_ON_CHIP_PERIPH_BASE 0x2C000000
+// Note: The TRM says not all the peripherals are implemented
+#define ARM_VE_ON_CHIP_PERIPH_SZ SIZE_256MB
+
+
+// External AXI between daughterboards (Logic Tile)
+#define ARM_VE_EXT_AXI_BASE 0x2E010000 // Not modelled
+#define ARM_VE_EXT_AXI_SZ 0x20000000 /* 512 MB */
+
+/***********************************************************************************
+// Memory-mapped peripherals
+************************************************************************************/
+
+// SP810 Controller
+#undef SP810_CTRL_BASE
+#define SP810_CTRL_BASE 0x1C020000
+
+// PL111 Colour LCD Controller
+#define PL111_CLCD_SITE ARM_VE_MOTHERBOARD_SITE
+#define PL111_CLCD_MOTHERBOARD_VIDEO_MODE_OSC_ID 1
+#define PL111_CLCD_CORE_TILE_VIDEO_MODE_OSC_ID 1
+
+#endif
diff --git a/Platform/ARM/VExpressPkg/Include/VExpressMotherBoard.h b/Platform/ARM/VExpressPkg/Include/VExpressMotherBoard.h new file mode 100644 index 0000000000..38691c3582 --- /dev/null +++ b/Platform/ARM/VExpressPkg/Include/VExpressMotherBoard.h @@ -0,0 +1,140 @@ +/** @file
+* Header defining Versatile Express constants (Base addresses, sizes, flags)
+*
+* Copyright (c) 2011-2015, ARM Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef __VEXPRESSMOTHERBOARD_H_
+#define __VEXPRESSMOTHERBOARD_H_
+
+#include <ArmPlatform.h>
+
+/***********************************************************************************
+// Motherboard memory-mapped peripherals
+************************************************************************************/
+
+// Define MotherBoard SYS flags offsets (from ARM_VE_BOARD_PERIPH_BASE)
+#define ARM_VE_SYS_ID_REG (ARM_VE_BOARD_PERIPH_BASE + 0x00000)
+#define ARM_VE_SYS_SW_REG (ARM_VE_BOARD_PERIPH_BASE + 0x00004)
+#define ARM_VE_SYS_LED_REG (ARM_VE_BOARD_PERIPH_BASE + 0x00008)
+#define ARM_VE_SYS_FLAGS_REG (ARM_VE_BOARD_PERIPH_BASE + 0x00030)
+#define ARM_VE_SYS_FLAGS_SET_REG (ARM_VE_BOARD_PERIPH_BASE + 0x00030)
+#define ARM_VE_SYS_FLAGS_CLR_REG (ARM_VE_BOARD_PERIPH_BASE + 0x00034)
+#define ARM_VE_SYS_FLAGS_NV_REG (ARM_VE_BOARD_PERIPH_BASE + 0x00038)
+#define ARM_VE_SYS_FLAGS_NV_SET_REG (ARM_VE_BOARD_PERIPH_BASE + 0x00038)
+#define ARM_VE_SYS_FLAGS_NV_CLR_REG (ARM_VE_BOARD_PERIPH_BASE + 0x0003C)
+#define ARM_VE_SYS_FLASH (ARM_VE_BOARD_PERIPH_BASE + 0x0004C)
+#define ARM_VE_SYS_CFGSWR_REG (ARM_VE_BOARD_PERIPH_BASE + 0x00058)
+#define ARM_VE_SYS_MISC (ARM_VE_BOARD_PERIPH_BASE + 0x00060)
+#define ARM_VE_SYS_PROCID0_REG (ARM_VE_BOARD_PERIPH_BASE + 0x00084)
+#define ARM_VE_SYS_PROCID1_REG (ARM_VE_BOARD_PERIPH_BASE + 0x00088)
+#define ARM_VE_SYS_CFGDATA_REG (ARM_VE_BOARD_PERIPH_BASE + 0x000A0)
+#define ARM_VE_SYS_CFGCTRL_REG (ARM_VE_BOARD_PERIPH_BASE + 0x000A4)
+#define ARM_VE_SYS_CFGSTAT_REG (ARM_VE_BOARD_PERIPH_BASE + 0x000A8)
+
+// SP810 Controller
+#ifndef SP810_CTRL_BASE
+#define SP810_CTRL_BASE (ARM_VE_BOARD_PERIPH_BASE + 0x01000)
+#endif
+
+// PL111 Colour LCD Controller - motherboard
+#define PL111_CLCD_MOTHERBOARD_BASE (ARM_VE_BOARD_PERIPH_BASE + 0x1F000)
+#define PL111_CLCD_MOTHERBOARD_VIDEO_MODE_OSC_ID 1
+
+// VRAM offset for the PL111 Colour LCD Controller on the motherboard
+#define VRAM_MOTHERBOARD_BASE (ARM_VE_SMB_PERIPH_BASE + 0x00000)
+
+#define ARM_VE_SYS_PROC_ID_HBI 0xFFF
+#define ARM_VE_SYS_PROC_ID_MASK (UINT32)(0xFFU << 24)
+#define ARM_VE_SYS_PROC_ID_UNSUPPORTED (UINT32)(0xFFU << 24)
+#define ARM_VE_SYS_PROC_ID_CORTEX_A9 (UINT32)(0x0CU << 24)
+#define ARM_VE_SYS_PROC_ID_CORTEX_A5 (UINT32)(0x12U << 24)
+#define ARM_VE_SYS_PROC_ID_CORTEX_A15 (UINT32)(0x14U << 24)
+#define ARM_VE_SYS_PROC_ID_CORTEX_A7 (UINT32)(0x18U << 24)
+#define ARM_VE_SYS_PROC_ID_CORTEX_A12 (UINT32)(0x1CU << 24)
+
+// Boot Master Select:
+// 0 = Site 1 boot master
+// 1 = Site 2 boot master
+#define ARM_VE_SYS_MISC_MASTERSITE (1 << 14)
+//
+// Sites where the peripheral is fitted
+//
+#define ARM_VE_UNSUPPORTED ~0
+#define ARM_VE_MOTHERBOARD_SITE 0
+#define ARM_VE_DAUGHTERBOARD_1_SITE 1
+#define ARM_VE_DAUGHTERBOARD_2_SITE 2
+
+#define VIRTUAL_SYS_CFG(site,func) (((site) << 24) | (func))
+
+//
+// System Configuration Control Functions
+//
+#define SYS_CFG_OSC 1
+#define SYS_CFG_VOLT 2
+#define SYS_CFG_AMP 3
+#define SYS_CFG_TEMP 4
+#define SYS_CFG_RESET 5
+#define SYS_CFG_SCC 6
+#define SYS_CFG_MUXFPGA 7
+#define SYS_CFG_SHUTDOWN 8
+#define SYS_CFG_REBOOT 9
+#define SYS_CFG_DVIMODE 11
+#define SYS_CFG_POWER 12
+// Oscillator for Site 1
+#define SYS_CFG_OSC_SITE1 VIRTUAL_SYS_CFG(ARM_VE_DAUGHTERBOARD_1_SITE,SYS_CFG_OSC)
+// Oscillator for Site 2
+#define SYS_CFG_OSC_SITE2 VIRTUAL_SYS_CFG(ARM_VE_DAUGHTERBOARD_2_SITE,SYS_CFG_OSC)
+// Can not access the battery backed-up hardware clock on the Versatile Express motherboard
+#define SYS_CFG_RTC VIRTUAL_SYS_CFG(ARM_VE_UNSUPPORTED,1)
+
+//
+// System ID
+//
+// All RTSM VE models have the same System ID : 0x225F500
+//
+// FVP models have a different System ID.
+// Default Base model System ID : 0x00201100
+// [31:28] Rev - Board revision: 0x0 = Rev A
+// [27:16] HBI - HBI board number in BCD: 0x020 = v8 Base Platform
+// [15:12] Variant - Build variant of board: 0x1 = Variant B. (GIC 64k map)
+// [11:8] Plat - Platform type: 0x1 = Model
+// [7:0] FPGA - FPGA build, BCD coded: 0x00
+//
+//HBI = 010 = Foundation Model
+//HBI = 020 = Base Platform
+//
+// And specifically, the GIC register banks start at the following
+// addresses:
+// Variant = 0 Variant = 1
+//GICD 0x2c001000 0x2f000000
+//GICC 0x2c002000 0x2c000000
+//GICH 0x2c004000 0x2c010000
+//GICV 0x2c006000 0x2c020000
+
+#define ARM_FVP_BASE_BOARD_SYS_ID (0x00200100)
+#define ARM_FVP_FOUNDATION_BOARD_SYS_ID (0x00100100)
+
+#define ARM_FVP_SYS_ID_REV_MASK (UINT32)(0xFUL << 28)
+#define ARM_FVP_SYS_ID_HBI_MASK (UINT32)(0xFFFUL << 16)
+#define ARM_FVP_SYS_ID_VARIANT_MASK (UINT32)(0xFUL << 12)
+#define ARM_FVP_SYS_ID_PLAT_MASK (UINT32)(0xFUL << 8 )
+#define ARM_FVP_SYS_ID_FPGA_MASK (UINT32)(0xFFUL << 0 )
+#define ARM_FVP_GIC_VE_MMAP 0x0
+#define ARM_FVP_GIC_BASE_MMAP (UINT32)(1 << 12)
+
+// The default SYS_IDs. These can be changed when starting the model.
+#define ARM_RTSM_SYS_ID (0x225F500)
+#define ARM_FVP_BASE_SYS_ID (ARM_FVP_BASE_BOARD_SYS_ID | ARM_FVP_GIC_BASE_MMAP)
+#define ARM_FVP_FOUNDATION_SYS_ID (ARM_FVP_FOUNDATION_BOARD_SYS_ID | ARM_FVP_GIC_BASE_MMAP)
+
+#endif /* VEXPRESSMOTHERBOARD_H_ */
|