diff options
| author | zwei4 <david.wei@intel.com> | 2017-09-02 17:18:26 +0800 |
|---|---|---|
| committer | zwei4 <david.wei@intel.com> | 2017-09-02 17:18:26 +0800 |
| commit | c7fd86be57d7746457e7a2faf4dd0199a9a07342 (patch) | |
| tree | 9fd2335c42d01e788a94da2939e61aef2c893ecd /Platform/BroxtonPlatformPkg/Board | |
| parent | dbb279c54dbed80ec700cfbd61632a64c2c08b51 (diff) | |
| download | edk2-platforms-c7fd86be57d7746457e7a2faf4dd0199a9a07342.tar.xz | |
Enable GT RC6.
Remove code that disables GT RC6. This could allow GT to enter deep sleep when it is idle, so that more power could be saved for core to use. This temp solution allows core frequency maximally rise to 1100MHz.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: zwei4 <david.wei@intel.com>
Diffstat (limited to 'Platform/BroxtonPlatformPkg/Board')
| -rw-r--r-- | Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPreMem/BoardInitMiscs.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPreMem/BoardInitMiscs.c b/Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPreMem/BoardInitMiscs.c index 6abeb1d349..f124623ecb 100644 --- a/Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPreMem/BoardInitMiscs.c +++ b/Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPreMem/BoardInitMiscs.c @@ -116,7 +116,7 @@ LhUpdateFspmUpd ( FspUpdRgn->FspmConfig.MemoryDown = 1;
FspUpdRgn->FspmConfig.DDR3LPageSize = 0;
FspUpdRgn->FspmConfig.DDR3LASR = 0;
- FspUpdRgn->FspmConfig.MemorySizeLimit = 0x1800;
+ FspUpdRgn->FspmConfig.MemorySizeLimit = 0;
FspUpdRgn->FspmConfig.DIMM0SPDAddress = 0;
FspUpdRgn->FspmConfig.DIMM1SPDAddress = 0;
FspUpdRgn->FspmConfig.DDR3LPageSize = 0;
|